Lines Matching refs:REG2
40 ; CHECK: leaq arr1+4([[REG1]],[[REG1]],2), [[REG2:%[a-z]+]]
44 ; CHECK: movl ${{[1-4]+}}, ([[REG2]])
45 ; ENABLED: movl ${{[1-4]+}}, 4([[REG2]])
47 ; CHECK: movl ${{[1-4]+}}, ([[REG2]])
48 ; ENABLED: movl ${{[1-4]+}}, 4([[REG2]])
82 ; CHECK: leaq arr1+4([[REG1]],[[REG1]],2), [[REG2:%[a-z]+]]
83 ; ENABLED: movl -4([[REG2]]), {{.*}}
84 ; ENABLED: subl ([[REG2]]), {{.*}}
85 ; ENABLED: addl 4([[REG2]]), {{.*}}
89 ; CHECK: movl ${{[1-4]+}}, ([[REG2]])
90 ; ENABLED: movl ${{[1-4]+}}, 4([[REG2]])
92 ; CHECK: movl ${{[1-4]+}}, ([[REG2]])
93 ; ENABLED: movl ${{[1-4]+}}, 4([[REG2]])
129 ; CHECK: leaq arr2+132([[REG1]]), [[REG2:%[a-z]+]]
132 ; REG3's definition is closer to movl than REG2's, but the pass still chooses
133 ; REG2 because it provides the resultant address displacement fitting 1 byte.
135 ; ENABLED: movl ([[REG2]]), {{.*}}
139 ; CHECK: movl ${{[1-4]+}}, ([[REG2]])
141 ; CHECK: movl ${{[1-4]+}}, ([[REG2]])
175 ; CHECK: leaq arr1+4([[REG1]]), [[REG2:%[a-z]+]]
176 ; ENABLED: movl -4([[REG2]]), {{.*}}
177 ; ENABLED: subl ([[REG2]]), {{.*}}
178 ; ENABLED: addl 4([[REG2]]), {{.*}}
182 ; CHECK: movl ${{[1-4]+}}, ([[REG2]])
183 ; ENABLED: movl ${{[1-4]+}}, 4([[REG2]])
185 ; CHECK: movl ${{[1-4]+}}, ([[REG2]])
186 ; ENABLED: movl ${{[1-4]+}}, 4([[REG2]])