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Lines Matching refs:BOOL_32

176BOOL_32              stackedDepthSlices;           ///< TRUE if depth slices are treated as being
687 BOOL_32 isDepth; ///< TRUE if the surface uses depth sample ordering within
775 BOOL_32 isDepth; ///< Surface uses depth sample ordering within micro tile.
881 BOOL_32 isLinear; ///< Linear or tiled HTILE layout
914 BOOL_32 sliceInterleaved; ///< Flag to indicate if different slice's htile is interleaved
916 BOOL_32 nextMipLevelCompressible; ///< Flag to indicate whether HTILE can be enabled in
954 BOOL_32 isLinear; ///< Linear or tiled HTILE layout
1018 BOOL_32 isLinear; ///< Linear or tiled HTILE layout
1101 BOOL_32 isLinear; ///< Linear or tiled layout, Only SI can be linear
1171 BOOL_32 isLinear; ///< Linear or tiled layout, Only SI can be linear
1231 BOOL_32 isLinear; ///< Linear or tiled layout, Only SI can be linear
1530 BOOL_32 ADDR_API AddrUseTileIndex(ADDR_HANDLE hLib);
1540 BOOL_32 ADDR_API AddrUseCombinedSwizzle(ADDR_HANDLE hLib);
1843 BOOL_32 ADDR_API ElemGetExportNorm(
1988 BOOL_32 reverse; ///< Convert control flag.
2049 BOOL_32 tileInfoHw; ///< Set to TRUE if client wants HW enum, otherwise actual
2142 BOOL_32 tileInfoHw; ///< Set to TRUE if client wants HW enum, otherwise actual
2295 BOOL_32 subLvlCompressible; ///< Whether sub resource is compressiable
2296 BOOL_32 dccRamSizeAligned; ///< Whether the dcc key size is aligned
2515 BOOL_32 epitchIsHeight; ///< Whether to use height to program epitch register
2524 BOOL_32 mipChainInTail; ///< If whole mipchain falls into mip tail block
2714 BOOL_32 inMiptail;
3741 BOOL_32 noXor; ///< Do not use xor mode for this resource
3771 BOOL_32 canXor; ///< If client can use xor on a valid macro block