Lines Matching refs:surf
477 struct radeon_surf *surf, bool is_stencil, unsigned level, in gfx6_compute_level() argument
524 AddrSurfInfoIn->basePitch = surf->u.legacy.stencil_level[0].nblk_x; in gfx6_compute_level()
526 AddrSurfInfoIn->basePitch = surf->u.legacy.level[0].nblk_x; in gfx6_compute_level()
530 AddrSurfInfoIn->basePitch *= surf->blk_w; in gfx6_compute_level()
538 surf_level = is_stencil ? &surf->u.legacy.stencil_level[level] : &surf->u.legacy.level[level]; in gfx6_compute_level()
539 surf_level->offset = align64(surf->surf_size, AddrSurfInfoOut->baseAlign); in gfx6_compute_level()
559 surf->u.legacy.stencil_tiling_index[level] = AddrSurfInfoOut->tileIndex; in gfx6_compute_level()
561 surf->u.legacy.tiling_index[level] = AddrSurfInfoOut->tileIndex; in gfx6_compute_level()
563 surf->surf_size = surf_level->offset + AddrSurfInfoOut->surfSize; in gfx6_compute_level()
581 surf_level->dcc_offset = surf->dcc_size; in gfx6_compute_level()
582 surf->num_dcc_levels = level + 1; in gfx6_compute_level()
583 surf->dcc_size = surf_level->dcc_offset + AddrDccOut->dccRamSize; in gfx6_compute_level()
584 surf->dcc_alignment = MAX2(surf->dcc_alignment, AddrDccOut->dccRamBaseAlign); in gfx6_compute_level()
607 surf->dcc_slice_size = AddrDccOut->dccRamSize / config->info.array_size; in gfx6_compute_level()
632 if (surf->flags & RADEON_SURF_CONTIGUOUS_DCC_LAYERS && in gfx6_compute_level()
633 surf->dcc_slice_size != surf_level->dcc_slice_fast_clear_size) { in gfx6_compute_level()
634 surf->dcc_size = 0; in gfx6_compute_level()
635 surf->num_dcc_levels = 0; in gfx6_compute_level()
646 level == 0 && !(surf->flags & RADEON_SURF_NO_HTILE)) { in gfx6_compute_level()
660 surf->htile_size = AddrHtileOut->htileBytes; in gfx6_compute_level()
661 surf->htile_slice_size = AddrHtileOut->sliceSize; in gfx6_compute_level()
662 surf->htile_alignment = AddrHtileOut->baseAlign; in gfx6_compute_level()
669 static void gfx6_set_micro_tile_mode(struct radeon_surf *surf, const struct radeon_info *info) in gfx6_set_micro_tile_mode() argument
671 uint32_t tile_mode = info->si_tile_mode_array[surf->u.legacy.tiling_index[0]]; in gfx6_set_micro_tile_mode()
674 surf->micro_tile_mode = G_009910_MICRO_TILE_MODE_NEW(tile_mode); in gfx6_set_micro_tile_mode()
676 surf->micro_tile_mode = G_009910_MICRO_TILE_MODE(tile_mode); in gfx6_set_micro_tile_mode()
679 static unsigned cik_get_macro_tile_index(struct radeon_surf *surf) in cik_get_macro_tile_index() argument
683 tileb = 8 * 8 * surf->bpe; in cik_get_macro_tile_index()
684 tileb = MIN2(surf->u.legacy.tile_split, tileb); in cik_get_macro_tile_index()
693 static bool get_display_flag(const struct ac_surf_config *config, const struct radeon_surf *surf) in get_display_flag() argument
696 unsigned bpe = surf->bpe; in get_display_flag()
698 if (!config->is_3d && !config->is_cube && !(surf->flags & RADEON_SURF_Z_OR_SBUFFER) && in get_display_flag()
699 surf->flags & RADEON_SURF_SCANOUT && config->info.samples <= 1 && surf->blk_w <= 2 && in get_display_flag()
700 surf->blk_h == 1) { in get_display_flag()
702 if (surf->blk_w == 2 && surf->blk_h == 1) in get_display_flag()
724 ADDR_COMPUTE_SURFACE_INFO_OUTPUT *csio, struct radeon_surf *surf) in gfx6_surface_settings() argument
726 surf->surf_alignment = csio->baseAlign; in gfx6_surface_settings()
727 surf->u.legacy.pipe_config = csio->pTileInfo->pipeConfig - 1; in gfx6_surface_settings()
728 gfx6_set_micro_tile_mode(surf, info); in gfx6_surface_settings()
732 surf->u.legacy.bankw = csio->pTileInfo->bankWidth; in gfx6_surface_settings()
733 surf->u.legacy.bankh = csio->pTileInfo->bankHeight; in gfx6_surface_settings()
734 surf->u.legacy.mtilea = csio->pTileInfo->macroAspectRatio; in gfx6_surface_settings()
735 surf->u.legacy.tile_split = csio->pTileInfo->tileSplitBytes; in gfx6_surface_settings()
736 surf->u.legacy.num_banks = csio->pTileInfo->banks; in gfx6_surface_settings()
737 surf->u.legacy.macro_tile_index = csio->macroModeIndex; in gfx6_surface_settings()
739 surf->u.legacy.macro_tile_index = 0; in gfx6_surface_settings()
745 surf->u.legacy.level[0].mode == RADEON_SURF_MODE_2D && in gfx6_surface_settings()
746 !(surf->flags & (RADEON_SURF_Z_OR_SBUFFER | RADEON_SURF_SHAREABLE)) && in gfx6_surface_settings()
747 !get_display_flag(config, surf)) { in gfx6_surface_settings()
765 u_bit_consecutive(0, sizeof(surf->tile_swizzle) * 8)); in gfx6_surface_settings()
766 surf->tile_swizzle = AddrBaseSwizzleOut.tileSwizzle; in gfx6_surface_settings()
772 struct radeon_surf *surf) in ac_compute_cmask() argument
778 if (surf->flags & RADEON_SURF_Z_OR_SBUFFER || surf->is_linear || in ac_compute_cmask()
779 (config->info.samples >= 2 && !surf->fmask_size)) in ac_compute_cmask()
808 unsigned width = align(surf->u.legacy.level[0].nblk_x, cl_width * 8); in ac_compute_cmask()
809 unsigned height = align(surf->u.legacy.level[0].nblk_y, cl_height * 8); in ac_compute_cmask()
815 surf->u.legacy.cmask_slice_tile_max = (width * height) / (128 * 128); in ac_compute_cmask()
816 if (surf->u.legacy.cmask_slice_tile_max) in ac_compute_cmask()
817 surf->u.legacy.cmask_slice_tile_max -= 1; in ac_compute_cmask()
827 surf->cmask_alignment = MAX2(256, base_align); in ac_compute_cmask()
828 surf->cmask_slice_size = align(slice_bytes, base_align); in ac_compute_cmask()
829 surf->cmask_size = surf->cmask_slice_size * num_layers; in ac_compute_cmask()
840 struct radeon_surf *surf) in gfx6_compute_surface() argument
862 compressed = surf->blk_w == 4 && surf->blk_h == 4; in gfx6_compute_surface()
869 if (surf->flags & (RADEON_SURF_Z_OR_SBUFFER) && mode < RADEON_SURF_MODE_1D) in gfx6_compute_surface()
891 switch (surf->bpe) { in gfx6_compute_surface()
902 AddrDccIn.bpp = AddrSurfInfoIn.bpp = surf->bpe * 8; in gfx6_compute_surface()
908 if (!(surf->flags & RADEON_SURF_Z_OR_SBUFFER)) { in gfx6_compute_surface()
913 if (surf->flags & RADEON_SURF_SCANOUT) in gfx6_compute_surface()
915 else if (surf->flags & RADEON_SURF_Z_OR_SBUFFER) in gfx6_compute_surface()
920 AddrSurfInfoIn.flags.color = !(surf->flags & RADEON_SURF_Z_OR_SBUFFER); in gfx6_compute_surface()
921 AddrSurfInfoIn.flags.depth = (surf->flags & RADEON_SURF_ZBUFFER) != 0; in gfx6_compute_surface()
923 AddrSurfInfoIn.flags.display = get_display_flag(config, surf); in gfx6_compute_surface()
925 AddrSurfInfoIn.flags.tcCompatible = (surf->flags & RADEON_SURF_TC_COMPATIBLE_HTILE) != 0; in gfx6_compute_surface()
932 !(surf->flags & RADEON_SURF_FORCE_SWIZZLE_MODE); in gfx6_compute_surface()
942 !(surf->flags & RADEON_SURF_Z_OR_SBUFFER) && !(surf->flags & RADEON_SURF_DISABLE_DCC) && in gfx6_compute_surface()
946 AddrSurfInfoIn.flags.noStencil = (surf->flags & RADEON_SURF_SBUFFER) == 0; in gfx6_compute_surface()
947 AddrSurfInfoIn.flags.compressZ = !!(surf->flags & RADEON_SURF_Z_OR_SBUFFER); in gfx6_compute_surface()
981 if (!(surf->flags & RADEON_SURF_Z_OR_SBUFFER) && in gfx6_compute_surface()
982 AddrSurfInfoIn.tileMode >= ADDR_TM_2D_TILED_THIN1 && surf->u.legacy.bankw && in gfx6_compute_surface()
983 surf->u.legacy.bankh && surf->u.legacy.mtilea && surf->u.legacy.tile_split) { in gfx6_compute_surface()
986 AddrTileInfoIn.banks = surf->u.legacy.num_banks; in gfx6_compute_surface()
987 AddrTileInfoIn.bankWidth = surf->u.legacy.bankw; in gfx6_compute_surface()
988 AddrTileInfoIn.bankHeight = surf->u.legacy.bankh; in gfx6_compute_surface()
989 AddrTileInfoIn.macroAspectRatio = surf->u.legacy.mtilea; in gfx6_compute_surface()
990 AddrTileInfoIn.tileSplitBytes = surf->u.legacy.tile_split; in gfx6_compute_surface()
991 AddrTileInfoIn.pipeConfig = surf->u.legacy.pipe_config + 1; /* +1 compared to GB_TILE_MODE */ in gfx6_compute_surface()
1003 assert(!(surf->flags & RADEON_SURF_Z_OR_SBUFFER)); in gfx6_compute_surface()
1008 if (surf->bpe == 2) in gfx6_compute_surface()
1013 if (surf->bpe == 1) in gfx6_compute_surface()
1015 else if (surf->bpe == 2) in gfx6_compute_surface()
1017 else if (surf->bpe == 4) in gfx6_compute_surface()
1030 AddrSurfInfoOut.macroModeIndex = cik_get_macro_tile_index(surf); in gfx6_compute_surface()
1034 surf->has_stencil = !!(surf->flags & RADEON_SURF_SBUFFER); in gfx6_compute_surface()
1035 surf->num_dcc_levels = 0; in gfx6_compute_surface()
1036 surf->surf_size = 0; in gfx6_compute_surface()
1037 surf->dcc_size = 0; in gfx6_compute_surface()
1038 surf->dcc_alignment = 1; in gfx6_compute_surface()
1039 surf->htile_size = 0; in gfx6_compute_surface()
1040 surf->htile_slice_size = 0; in gfx6_compute_surface()
1041 surf->htile_alignment = 1; in gfx6_compute_surface()
1044 (surf->flags & RADEON_SURF_SBUFFER) && !(surf->flags & RADEON_SURF_ZBUFFER); in gfx6_compute_surface()
1049 r = gfx6_compute_level(addrlib, config, surf, false, level, compressed, &AddrSurfInfoIn, in gfx6_compute_surface()
1060 surf->flags &= ~RADEON_SURF_TC_COMPATIBLE_HTILE; in gfx6_compute_surface()
1071 r = gfx6_surface_settings(addrlib, info, config, &AddrSurfInfoOut, surf); in gfx6_compute_surface()
1078 if (surf->flags & RADEON_SURF_SBUFFER) { in gfx6_compute_surface()
1085 AddrTileInfoIn.tileSplitBytes = surf->u.legacy.stencil_tile_split; in gfx6_compute_surface()
1088 r = gfx6_compute_level(addrlib, config, surf, true, level, compressed, &AddrSurfInfoIn, in gfx6_compute_surface()
1095 if (surf->u.legacy.stencil_level[level].nblk_x != surf->u.legacy.level[level].nblk_x) in gfx6_compute_surface()
1096 surf->u.legacy.stencil_adjusted = true; in gfx6_compute_surface()
1098 surf->u.legacy.level[level].nblk_x = surf->u.legacy.stencil_level[level].nblk_x; in gfx6_compute_surface()
1103 r = gfx6_surface_settings(addrlib, info, config, &AddrSurfInfoOut, surf); in gfx6_compute_surface()
1110 surf->u.legacy.stencil_tile_split = AddrSurfInfoOut.pTileInfo->tileSplitBytes; in gfx6_compute_surface()
1118 !(surf->flags & RADEON_SURF_NO_FMASK)) { in gfx6_compute_surface()
1139 surf->fmask_size = fout.fmaskBytes; in gfx6_compute_surface()
1140 surf->fmask_alignment = fout.baseAlign; in gfx6_compute_surface()
1141 surf->fmask_tile_swizzle = 0; in gfx6_compute_surface()
1143 surf->u.legacy.fmask.slice_tile_max = (fout.pitch * fout.height) / 64; in gfx6_compute_surface()
1144 if (surf->u.legacy.fmask.slice_tile_max) in gfx6_compute_surface()
1145 surf->u.legacy.fmask.slice_tile_max -= 1; in gfx6_compute_surface()
1147 surf->u.legacy.fmask.tiling_index = fout.tileIndex; in gfx6_compute_surface()
1148 surf->u.legacy.fmask.bankh = fout.pTileInfo->bankHeight; in gfx6_compute_surface()
1149 surf->u.legacy.fmask.pitch_in_pixels = fout.pitch; in gfx6_compute_surface()
1150 surf->u.legacy.fmask.slice_size = fout.sliceSize; in gfx6_compute_surface()
1153 if (config->info.fmask_surf_index && !(surf->flags & RADEON_SURF_SHAREABLE)) { in gfx6_compute_surface()
1171 assert(xout.tileSwizzle <= u_bit_consecutive(0, sizeof(surf->tile_swizzle) * 8)); in gfx6_compute_surface()
1172 surf->fmask_tile_swizzle = xout.tileSwizzle; in gfx6_compute_surface()
1180 if (surf->dcc_size && config->info.levels > 1) { in gfx6_compute_surface()
1189 surf->dcc_size = align64(surf->surf_size >> 8, surf->dcc_alignment * 4); in gfx6_compute_surface()
1195 if (surf->htile_size && config->info.levels > 1 && in gfx6_compute_surface()
1196 surf->flags & RADEON_SURF_TC_COMPATIBLE_HTILE) { in gfx6_compute_surface()
1198 const unsigned total_pixels = surf->surf_size / surf->bpe; in gfx6_compute_surface()
1202 surf->htile_size = (total_pixels / htile_block_size) * htile_element_size; in gfx6_compute_surface()
1203 surf->htile_size = align(surf->htile_size, surf->htile_alignment); in gfx6_compute_surface()
1204 } else if (!surf->htile_size) { in gfx6_compute_surface()
1206 surf->flags &= ~RADEON_SURF_TC_COMPATIBLE_HTILE; in gfx6_compute_surface()
1209 surf->is_linear = surf->u.legacy.level[0].mode == RADEON_SURF_MODE_LINEAR_ALIGNED; in gfx6_compute_surface()
1210 surf->is_displayable = surf->is_linear || surf->micro_tile_mode == RADEON_MICRO_MODE_DISPLAY || in gfx6_compute_surface()
1211 surf->micro_tile_mode == RADEON_MICRO_MODE_RENDER; in gfx6_compute_surface()
1218 if (surf->micro_tile_mode == RADEON_MICRO_MODE_RENDER) { in gfx6_compute_surface()
1223 ac_compute_cmask(info, config, surf); in gfx6_compute_surface()
1228 static int gfx9_get_preferred_swizzle_mode(ADDR_HANDLE addrlib, struct radeon_surf *surf, in gfx9_get_preferred_swizzle_mode() argument
1260 if (surf->flags & RADEON_SURF_FORCE_MICRO_TILE_MODE) { in gfx9_get_preferred_swizzle_mode()
1263 if (surf->micro_tile_mode == RADEON_MICRO_MODE_DISPLAY) in gfx9_get_preferred_swizzle_mode()
1265 else if (surf->micro_tile_mode == RADEON_MICRO_MODE_STANDARD) in gfx9_get_preferred_swizzle_mode()
1267 else if (surf->micro_tile_mode == RADEON_MICRO_MODE_DEPTH) in gfx9_get_preferred_swizzle_mode()
1269 else if (surf->micro_tile_mode == RADEON_MICRO_MODE_RENDER) in gfx9_get_preferred_swizzle_mode()
1290 const struct radeon_surf *surf) in is_dcc_supported_by_L2() argument
1294 return surf->u.gfx9.dcc.independent_64B_blocks && !surf->u.gfx9.dcc.independent_128B_blocks && in is_dcc_supported_by_L2()
1295 surf->u.gfx9.dcc.max_compressed_block_size == V_028C78_MAX_BLOCK_SIZE_64B; in is_dcc_supported_by_L2()
1300 return !surf->u.gfx9.dcc.independent_64B_blocks && surf->u.gfx9.dcc.independent_128B_blocks && in is_dcc_supported_by_L2()
1301 surf->u.gfx9.dcc.max_compressed_block_size <= V_028C78_MAX_BLOCK_SIZE_128B; in is_dcc_supported_by_L2()
1308 return surf->u.gfx9.dcc.independent_64B_blocks != surf->u.gfx9.dcc.independent_128B_blocks && in is_dcc_supported_by_L2()
1309 (!surf->u.gfx9.dcc.independent_64B_blocks || in is_dcc_supported_by_L2()
1310 surf->u.gfx9.dcc.max_compressed_block_size == V_028C78_MAX_BLOCK_SIZE_64B) && in is_dcc_supported_by_L2()
1311 (!surf->u.gfx9.dcc.independent_128B_blocks || in is_dcc_supported_by_L2()
1312 surf->u.gfx9.dcc.max_compressed_block_size <= V_028C78_MAX_BLOCK_SIZE_128B); in is_dcc_supported_by_L2()
1319 return surf->u.gfx9.dcc.independent_128B_blocks && in is_dcc_supported_by_L2()
1320 surf->u.gfx9.dcc.max_compressed_block_size <= V_028C78_MAX_BLOCK_SIZE_128B; in is_dcc_supported_by_L2()
1325 const struct radeon_surf *surf, bool rb_aligned, in is_dcc_supported_by_DCN() argument
1332 if (surf->bpe != 4) in is_dcc_supported_by_DCN()
1345 assert(surf->u.gfx9.dcc.independent_64B_blocks && in is_dcc_supported_by_DCN()
1346 surf->u.gfx9.dcc.max_compressed_block_size == V_028C78_MAX_BLOCK_SIZE_64B); in is_dcc_supported_by_DCN()
1351 if (info->chip_class == GFX10 && surf->u.gfx9.dcc.independent_128B_blocks) in is_dcc_supported_by_DCN()
1356 (surf->u.gfx9.dcc.independent_64B_blocks && in is_dcc_supported_by_DCN()
1357 surf->u.gfx9.dcc.max_compressed_block_size == V_028C78_MAX_BLOCK_SIZE_64B)); in is_dcc_supported_by_DCN()
1365 const struct ac_surf_config *config, struct radeon_surf *surf, in gfx9_compute_miptree() argument
1380 surf->u.gfx9.stencil.swizzle_mode = in->swizzleMode; in gfx9_compute_miptree()
1381 surf->u.gfx9.stencil.epitch = in gfx9_compute_miptree()
1383 surf->surf_alignment = MAX2(surf->surf_alignment, out.baseAlign); in gfx9_compute_miptree()
1384 surf->u.gfx9.stencil_offset = align(surf->surf_size, out.baseAlign); in gfx9_compute_miptree()
1385 surf->surf_size = surf->u.gfx9.stencil_offset + out.surfSize; in gfx9_compute_miptree()
1389 surf->u.gfx9.surf.swizzle_mode = in->swizzleMode; in gfx9_compute_miptree()
1390 surf->u.gfx9.surf.epitch = out.epitchIsHeight ? out.mipChainHeight - 1 : out.mipChainPitch - 1; in gfx9_compute_miptree()
1395 surf->u.gfx9.fmask.swizzle_mode = surf->u.gfx9.surf.swizzle_mode & ~0x3; in gfx9_compute_miptree()
1396 surf->u.gfx9.fmask.epitch = surf->u.gfx9.surf.epitch; in gfx9_compute_miptree()
1398 surf->u.gfx9.surf_slice_size = out.sliceSize; in gfx9_compute_miptree()
1399 surf->u.gfx9.surf_pitch = out.pitch; in gfx9_compute_miptree()
1400 surf->u.gfx9.surf_height = out.height; in gfx9_compute_miptree()
1401 surf->surf_size = out.surfSize; in gfx9_compute_miptree()
1402 surf->surf_alignment = out.baseAlign; in gfx9_compute_miptree()
1404 if (!compressed && surf->blk_w > 1 && out.pitch == out.pixelPitch && in gfx9_compute_miptree()
1405 surf->u.gfx9.surf.swizzle_mode == ADDR_SW_LINEAR) { in gfx9_compute_miptree()
1407 surf->u.gfx9.surf_pitch = align(surf->u.gfx9.surf_pitch / surf->blk_w, 256 / surf->bpe); in gfx9_compute_miptree()
1408 surf->u.gfx9.surf.epitch = in gfx9_compute_miptree()
1409 MAX2(surf->u.gfx9.surf.epitch, surf->u.gfx9.surf_pitch * surf->blk_w - 1); in gfx9_compute_miptree()
1415 surf->u.gfx9.surf_slice_size = in gfx9_compute_miptree()
1416 MAX2(surf->u.gfx9.surf_slice_size, in gfx9_compute_miptree()
1417 surf->u.gfx9.surf_pitch * out.height * surf->bpe * surf->blk_w); in gfx9_compute_miptree()
1418 surf->surf_size = surf->u.gfx9.surf_slice_size * in->numSlices; in gfx9_compute_miptree()
1423 surf->u.gfx9.offset[i] = mip_info[i].offset; in gfx9_compute_miptree()
1424 surf->u.gfx9.pitch[i] = mip_info[i].pitch; in gfx9_compute_miptree()
1428 surf->u.gfx9.base_mip_width = mip_info[0].pitch; in gfx9_compute_miptree()
1429 surf->u.gfx9.base_mip_height = mip_info[0].height; in gfx9_compute_miptree()
1434 if (surf->flags & RADEON_SURF_NO_HTILE) in gfx9_compute_miptree()
1461 surf->htile_size = hout.htileBytes; in gfx9_compute_miptree()
1462 surf->htile_slice_size = hout.sliceSize; in gfx9_compute_miptree()
1463 surf->htile_alignment = hout.baseAlign; in gfx9_compute_miptree()
1472 !(surf->flags & RADEON_SURF_SHAREABLE) && !in->flags.display) { in gfx9_compute_miptree()
1491 assert(xout.pipeBankXor <= u_bit_consecutive(0, sizeof(surf->tile_swizzle) * 8)); in gfx9_compute_miptree()
1492 surf->tile_swizzle = xout.pipeBankXor; in gfx9_compute_miptree()
1496 if (info->has_graphics && !(surf->flags & RADEON_SURF_DISABLE_DCC) && !compressed && in gfx9_compute_miptree()
1499 is_dcc_supported_by_DCN(info, config, surf, !in->flags.metaRbUnaligned, in gfx9_compute_miptree()
1526 surf->u.gfx9.dcc.rb_aligned = din.dccKeyFlags.rbAligned; in gfx9_compute_miptree()
1527 surf->u.gfx9.dcc.pipe_aligned = din.dccKeyFlags.pipeAligned; in gfx9_compute_miptree()
1528 surf->u.gfx9.dcc_block_width = dout.compressBlkWidth; in gfx9_compute_miptree()
1529 surf->u.gfx9.dcc_block_height = dout.compressBlkHeight; in gfx9_compute_miptree()
1530 surf->u.gfx9.dcc_block_depth = dout.compressBlkDepth; in gfx9_compute_miptree()
1531 surf->dcc_size = dout.dccRamSize; in gfx9_compute_miptree()
1532 surf->dcc_alignment = dout.dccRamBaseAlign; in gfx9_compute_miptree()
1533 surf->num_dcc_levels = in->numMipLevels; in gfx9_compute_miptree()
1566 surf->num_dcc_levels = i + 1; in gfx9_compute_miptree()
1568 surf->num_dcc_levels = i; in gfx9_compute_miptree()
1573 if (!surf->num_dcc_levels) in gfx9_compute_miptree()
1574 surf->dcc_size = 0; in gfx9_compute_miptree()
1576 surf->u.gfx9.display_dcc_size = surf->dcc_size; in gfx9_compute_miptree()
1577 surf->u.gfx9.display_dcc_alignment = surf->dcc_alignment; in gfx9_compute_miptree()
1578 surf->u.gfx9.display_dcc_pitch_max = dout.pitch - 1; in gfx9_compute_miptree()
1579 surf->u.gfx9.dcc_pitch_max = dout.pitch - 1; in gfx9_compute_miptree()
1582 if (in->flags.display && surf->num_dcc_levels && info->use_display_dcc_with_retile_blit) { in gfx9_compute_miptree()
1590 assert(surf->tile_swizzle == 0); in gfx9_compute_miptree()
1591 assert(surf->u.gfx9.dcc.pipe_aligned || surf->u.gfx9.dcc.rb_aligned); in gfx9_compute_miptree()
1597 surf->u.gfx9.display_dcc_size = dout.dccRamSize; in gfx9_compute_miptree()
1598 surf->u.gfx9.display_dcc_alignment = dout.dccRamBaseAlign; in gfx9_compute_miptree()
1599 surf->u.gfx9.display_dcc_pitch_max = dout.pitch - 1; in gfx9_compute_miptree()
1600 assert(surf->u.gfx9.display_dcc_size <= surf->dcc_size); in gfx9_compute_miptree()
1602 surf->u.gfx9.dcc_retile_use_uint16 = in gfx9_compute_miptree()
1603 surf->u.gfx9.display_dcc_size <= UINT16_MAX + 1 && surf->dcc_size <= UINT16_MAX + 1; in gfx9_compute_miptree()
1646 surf->u.gfx9.dcc_retile_num_elements = in gfx9_compute_miptree()
1650 surf->u.gfx9.dcc_retile_num_elements = align(surf->u.gfx9.dcc_retile_num_elements, 4); in gfx9_compute_miptree()
1672 surf->u.gfx9.dcc_retile_map = ac_compute_dcc_retile_map( in gfx9_compute_miptree()
1673 addrlib, info, retile_dim[0], retile_dim[1], surf->u.gfx9.dcc.rb_aligned, in gfx9_compute_miptree()
1674 surf->u.gfx9.dcc.pipe_aligned, surf->u.gfx9.dcc_retile_use_uint16, in gfx9_compute_miptree()
1675 surf->u.gfx9.dcc_retile_num_elements, &addrin); in gfx9_compute_miptree()
1676 if (!surf->u.gfx9.dcc_retile_map) in gfx9_compute_miptree()
1682 if (in->numSamples > 1 && info->has_graphics && !(surf->flags & RADEON_SURF_NO_FMASK)) { in gfx9_compute_miptree()
1689 ret = gfx9_get_preferred_swizzle_mode(addrlib->handle, surf, in, true, &fin.swizzleMode); in gfx9_compute_miptree()
1703 surf->u.gfx9.fmask.swizzle_mode = fin.swizzleMode; in gfx9_compute_miptree()
1704 surf->u.gfx9.fmask.epitch = fout.pitch - 1; in gfx9_compute_miptree()
1705 surf->fmask_size = fout.fmaskBytes; in gfx9_compute_miptree()
1706 surf->fmask_alignment = fout.baseAlign; in gfx9_compute_miptree()
1710 !(surf->flags & RADEON_SURF_SHAREABLE)) { in gfx9_compute_miptree()
1730 assert(xout.pipeBankXor <= u_bit_consecutive(0, sizeof(surf->fmask_tile_swizzle) * 8)); in gfx9_compute_miptree()
1731 surf->fmask_tile_swizzle = xout.pipeBankXor; in gfx9_compute_miptree()
1739 (surf->fmask_size && in->numSamples >= 2))) { in gfx9_compute_miptree()
1757 cin.swizzleMode = surf->u.gfx9.fmask.swizzle_mode; in gfx9_compute_miptree()
1765 surf->cmask_size = cout.cmaskBytes; in gfx9_compute_miptree()
1766 surf->cmask_alignment = cout.baseAlign; in gfx9_compute_miptree()
1775 struct radeon_surf *surf) in gfx9_compute_surface() argument
1783 compressed = surf->blk_w == 4 && surf->blk_h == 4; in gfx9_compute_surface()
1788 switch (surf->bpe) { in gfx9_compute_surface()
1799 switch (surf->bpe) { in gfx9_compute_surface()
1801 assert(!(surf->flags & RADEON_SURF_ZBUFFER)); in gfx9_compute_surface()
1805 assert(surf->flags & RADEON_SURF_ZBUFFER || !(surf->flags & RADEON_SURF_SBUFFER)); in gfx9_compute_surface()
1809 assert(surf->flags & RADEON_SURF_ZBUFFER || !(surf->flags & RADEON_SURF_SBUFFER)); in gfx9_compute_surface()
1813 assert(!(surf->flags & RADEON_SURF_Z_OR_SBUFFER)); in gfx9_compute_surface()
1817 assert(!(surf->flags & RADEON_SURF_Z_OR_SBUFFER)); in gfx9_compute_surface()
1821 assert(!(surf->flags & RADEON_SURF_Z_OR_SBUFFER)); in gfx9_compute_surface()
1827 AddrSurfInfoIn.bpp = surf->bpe * 8; in gfx9_compute_surface()
1830 bool is_color_surface = !(surf->flags & RADEON_SURF_Z_OR_SBUFFER); in gfx9_compute_surface()
1831 AddrSurfInfoIn.flags.color = is_color_surface && !(surf->flags & RADEON_SURF_NO_RENDER_TARGET); in gfx9_compute_surface()
1832 AddrSurfInfoIn.flags.depth = (surf->flags & RADEON_SURF_ZBUFFER) != 0; in gfx9_compute_surface()
1833 AddrSurfInfoIn.flags.display = get_display_flag(config, surf); in gfx9_compute_surface()
1835 AddrSurfInfoIn.flags.texture = is_color_surface || surf->flags & RADEON_SURF_TC_COMPATIBLE_HTILE; in gfx9_compute_surface()
1842 if (!(surf->flags & RADEON_SURF_Z_OR_SBUFFER)) in gfx9_compute_surface()
1871 surf->u.gfx9.dcc.independent_64B_blocks = 1; in gfx9_compute_surface()
1872 surf->u.gfx9.dcc.independent_128B_blocks = 0; in gfx9_compute_surface()
1873 surf->u.gfx9.dcc.max_compressed_block_size = V_028C78_MAX_BLOCK_SIZE_64B; in gfx9_compute_surface()
1875 surf->u.gfx9.dcc.independent_64B_blocks = 0; in gfx9_compute_surface()
1876 surf->u.gfx9.dcc.independent_128B_blocks = 1; in gfx9_compute_surface()
1877 surf->u.gfx9.dcc.max_compressed_block_size = V_028C78_MAX_BLOCK_SIZE_128B; in gfx9_compute_surface()
1899 surf->u.gfx9.dcc.independent_64B_blocks = 1; in gfx9_compute_surface()
1900 surf->u.gfx9.dcc.independent_128B_blocks = 0; in gfx9_compute_surface()
1901 surf->u.gfx9.dcc.max_compressed_block_size = V_028C78_MAX_BLOCK_SIZE_64B; in gfx9_compute_surface()
1905 surf->u.gfx9.dcc.independent_64B_blocks = 1; in gfx9_compute_surface()
1906 surf->u.gfx9.dcc.independent_128B_blocks = 1; in gfx9_compute_surface()
1907 surf->u.gfx9.dcc.max_compressed_block_size = V_028C78_MAX_BLOCK_SIZE_64B; in gfx9_compute_surface()
1915 assert(!(surf->flags & RADEON_SURF_Z_OR_SBUFFER)); in gfx9_compute_surface()
1921 if (surf->flags & RADEON_SURF_IMPORTED || in gfx9_compute_surface()
1922 (info->chip_class >= GFX10 && surf->flags & RADEON_SURF_FORCE_SWIZZLE_MODE)) { in gfx9_compute_surface()
1923 AddrSurfInfoIn.swizzleMode = surf->u.gfx9.surf.swizzle_mode; in gfx9_compute_surface()
1927 r = gfx9_get_preferred_swizzle_mode(addrlib->handle, surf, &AddrSurfInfoIn, false, in gfx9_compute_surface()
1937 surf->u.gfx9.resource_type = AddrSurfInfoIn.resourceType; in gfx9_compute_surface()
1938 surf->has_stencil = !!(surf->flags & RADEON_SURF_SBUFFER); in gfx9_compute_surface()
1940 surf->num_dcc_levels = 0; in gfx9_compute_surface()
1941 surf->surf_size = 0; in gfx9_compute_surface()
1942 surf->fmask_size = 0; in gfx9_compute_surface()
1943 surf->dcc_size = 0; in gfx9_compute_surface()
1944 surf->htile_size = 0; in gfx9_compute_surface()
1945 surf->htile_slice_size = 0; in gfx9_compute_surface()
1946 surf->u.gfx9.surf_offset = 0; in gfx9_compute_surface()
1947 surf->u.gfx9.stencil_offset = 0; in gfx9_compute_surface()
1948 surf->cmask_size = 0; in gfx9_compute_surface()
1949 surf->u.gfx9.dcc_retile_use_uint16 = false; in gfx9_compute_surface()
1950 surf->u.gfx9.dcc_retile_num_elements = 0; in gfx9_compute_surface()
1951 surf->u.gfx9.dcc_retile_map = NULL; in gfx9_compute_surface()
1954 r = gfx9_compute_miptree(addrlib, info, config, surf, compressed, &AddrSurfInfoIn); in gfx9_compute_surface()
1959 if (surf->flags & RADEON_SURF_SBUFFER) { in gfx9_compute_surface()
1965 r = gfx9_get_preferred_swizzle_mode(addrlib->handle, surf, &AddrSurfInfoIn, false, in gfx9_compute_surface()
1972 r = gfx9_compute_miptree(addrlib, info, config, surf, compressed, &AddrSurfInfoIn); in gfx9_compute_surface()
1977 surf->is_linear = surf->u.gfx9.surf.swizzle_mode == ADDR_SW_LINEAR; in gfx9_compute_surface()
1983 r = Addr2IsValidDisplaySwizzleMode(addrlib->handle, surf->u.gfx9.surf.swizzle_mode, in gfx9_compute_surface()
1984 surf->bpe * 8, &displayable); in gfx9_compute_surface()
1989 if (surf->num_dcc_levels && in gfx9_compute_surface()
1990 (!is_dcc_supported_by_DCN(info, config, surf, surf->u.gfx9.dcc.rb_aligned, in gfx9_compute_surface()
1991 surf->u.gfx9.dcc.pipe_aligned) || in gfx9_compute_surface()
1993 (info->use_display_dcc_with_retile_blit && !surf->u.gfx9.dcc_retile_num_elements))) in gfx9_compute_surface()
1996 surf->is_displayable = displayable; in gfx9_compute_surface()
1999 assert(!AddrSurfInfoIn.flags.display || surf->is_displayable); in gfx9_compute_surface()
2002 if (surf->num_dcc_levels) { in gfx9_compute_surface()
2003 assert(is_dcc_supported_by_L2(info, surf)); in gfx9_compute_surface()
2005 assert(is_dcc_supported_by_CB(info, surf->u.gfx9.surf.swizzle_mode)); in gfx9_compute_surface()
2007 assert(is_dcc_supported_by_DCN(info, config, surf, surf->u.gfx9.dcc.rb_aligned, in gfx9_compute_surface()
2008 surf->u.gfx9.dcc.pipe_aligned)); in gfx9_compute_surface()
2013 AddrSurfInfoIn.flags.color && !surf->is_linear && in gfx9_compute_surface()
2014 surf->surf_alignment >= 64 * 1024 && /* 64KB tiling */ in gfx9_compute_surface()
2015 !(surf->flags & (RADEON_SURF_DISABLE_DCC | RADEON_SURF_FORCE_SWIZZLE_MODE | in gfx9_compute_surface()
2019 AddrSurfInfoIn.flags.display && surf->bpe == 4) { in gfx9_compute_surface()
2020 assert(surf->num_dcc_levels); in gfx9_compute_surface()
2025 assert(surf->num_dcc_levels); in gfx9_compute_surface()
2028 if (!surf->htile_size) { in gfx9_compute_surface()
2030 surf->flags &= ~RADEON_SURF_TC_COMPATIBLE_HTILE; in gfx9_compute_surface()
2033 switch (surf->u.gfx9.surf.swizzle_mode) { in gfx9_compute_surface()
2041 surf->micro_tile_mode = RADEON_MICRO_MODE_STANDARD; in gfx9_compute_surface()
2052 surf->micro_tile_mode = RADEON_MICRO_MODE_DISPLAY; in gfx9_compute_surface()
2068 surf->micro_tile_mode = RADEON_MICRO_MODE_RENDER; in gfx9_compute_surface()
2078 surf->micro_tile_mode = RADEON_MICRO_MODE_DEPTH; in gfx9_compute_surface()
2090 struct radeon_surf *surf) in ac_compute_surface() argument
2094 r = surf_config_sanity(config, surf->flags); in ac_compute_surface()
2099 r = gfx9_compute_surface(addrlib, info, config, mode, surf); in ac_compute_surface()
2101 r = gfx6_compute_surface(addrlib->handle, info, config, mode, surf); in ac_compute_surface()
2107 surf->total_size = surf->surf_size; in ac_compute_surface()
2108 surf->alignment = surf->surf_alignment; in ac_compute_surface()
2111 surf->dcc_offset = surf->display_dcc_offset = 0; in ac_compute_surface()
2112 surf->fmask_offset = surf->cmask_offset = 0; in ac_compute_surface()
2113 surf->htile_offset = 0; in ac_compute_surface()
2115 if (surf->htile_size) { in ac_compute_surface()
2116 surf->htile_offset = align64(surf->total_size, surf->htile_alignment); in ac_compute_surface()
2117 surf->total_size = surf->htile_offset + surf->htile_size; in ac_compute_surface()
2118 surf->alignment = MAX2(surf->alignment, surf->htile_alignment); in ac_compute_surface()
2121 if (surf->fmask_size) { in ac_compute_surface()
2123 surf->fmask_offset = align64(surf->total_size, surf->fmask_alignment); in ac_compute_surface()
2124 surf->total_size = surf->fmask_offset + surf->fmask_size; in ac_compute_surface()
2125 surf->alignment = MAX2(surf->alignment, surf->fmask_alignment); in ac_compute_surface()
2129 if (surf->cmask_size && config->info.samples >= 2) { in ac_compute_surface()
2130 surf->cmask_offset = align64(surf->total_size, surf->cmask_alignment); in ac_compute_surface()
2131 surf->total_size = surf->cmask_offset + surf->cmask_size; in ac_compute_surface()
2132 surf->alignment = MAX2(surf->alignment, surf->cmask_alignment); in ac_compute_surface()
2135 if (surf->is_displayable) in ac_compute_surface()
2136 surf->flags |= RADEON_SURF_SCANOUT; in ac_compute_surface()
2138 if (surf->dcc_size && in ac_compute_surface()
2140 (info->chip_class >= GFX9 || !get_display_flag(config, surf))) { in ac_compute_surface()
2144 if (info->chip_class >= GFX9 && surf->u.gfx9.dcc_retile_num_elements) { in ac_compute_surface()
2146 surf->display_dcc_offset = align64(surf->total_size, surf->u.gfx9.display_dcc_alignment); in ac_compute_surface()
2147 surf->total_size = surf->display_dcc_offset + surf->u.gfx9.display_dcc_size; in ac_compute_surface()
2150 surf->dcc_offset = align64(surf->total_size, surf->dcc_alignment); in ac_compute_surface()
2151 surf->total_size = surf->dcc_offset + surf->dcc_size; in ac_compute_surface()
2152 surf->alignment = MAX2(surf->alignment, surf->dcc_alignment); in ac_compute_surface()
2159 void ac_surface_zero_dcc_fields(struct radeon_surf *surf) in ac_surface_zero_dcc_fields() argument
2161 surf->dcc_offset = 0; in ac_surface_zero_dcc_fields()
2162 surf->display_dcc_offset = 0; in ac_surface_zero_dcc_fields()
2219 void ac_surface_set_bo_metadata(const struct radeon_info *info, struct radeon_surf *surf, in ac_surface_set_bo_metadata() argument
2225 surf->u.gfx9.surf.swizzle_mode = AMDGPU_TILING_GET(tiling_flags, SWIZZLE_MODE); in ac_surface_set_bo_metadata()
2226 surf->u.gfx9.dcc.independent_64B_blocks = in ac_surface_set_bo_metadata()
2228 surf->u.gfx9.dcc.independent_128B_blocks = in ac_surface_set_bo_metadata()
2230 surf->u.gfx9.dcc.max_compressed_block_size = in ac_surface_set_bo_metadata()
2232 surf->u.gfx9.display_dcc_pitch_max = AMDGPU_TILING_GET(tiling_flags, DCC_PITCH_MAX); in ac_surface_set_bo_metadata()
2235 surf->u.gfx9.surf.swizzle_mode > 0 ? RADEON_SURF_MODE_2D : RADEON_SURF_MODE_LINEAR_ALIGNED; in ac_surface_set_bo_metadata()
2237 surf->u.legacy.pipe_config = AMDGPU_TILING_GET(tiling_flags, PIPE_CONFIG); in ac_surface_set_bo_metadata()
2238 surf->u.legacy.bankw = 1 << AMDGPU_TILING_GET(tiling_flags, BANK_WIDTH); in ac_surface_set_bo_metadata()
2239 surf->u.legacy.bankh = 1 << AMDGPU_TILING_GET(tiling_flags, BANK_HEIGHT); in ac_surface_set_bo_metadata()
2240 surf->u.legacy.tile_split = eg_tile_split(AMDGPU_TILING_GET(tiling_flags, TILE_SPLIT)); in ac_surface_set_bo_metadata()
2241 surf->u.legacy.mtilea = 1 << AMDGPU_TILING_GET(tiling_flags, MACRO_TILE_ASPECT); in ac_surface_set_bo_metadata()
2242 surf->u.legacy.num_banks = 2 << AMDGPU_TILING_GET(tiling_flags, NUM_BANKS); in ac_surface_set_bo_metadata()
2254 surf->flags |= RADEON_SURF_SCANOUT; in ac_surface_set_bo_metadata()
2256 surf->flags &= ~RADEON_SURF_SCANOUT; in ac_surface_set_bo_metadata()
2259 void ac_surface_get_bo_metadata(const struct radeon_info *info, struct radeon_surf *surf, in ac_surface_get_bo_metadata() argument
2267 if (surf->dcc_offset) { in ac_surface_get_bo_metadata()
2268 dcc_offset = surf->display_dcc_offset ? surf->display_dcc_offset : surf->dcc_offset; in ac_surface_get_bo_metadata()
2272 *tiling_flags |= AMDGPU_TILING_SET(SWIZZLE_MODE, surf->u.gfx9.surf.swizzle_mode); in ac_surface_get_bo_metadata()
2274 *tiling_flags |= AMDGPU_TILING_SET(DCC_PITCH_MAX, surf->u.gfx9.display_dcc_pitch_max); in ac_surface_get_bo_metadata()
2276 AMDGPU_TILING_SET(DCC_INDEPENDENT_64B, surf->u.gfx9.dcc.independent_64B_blocks); in ac_surface_get_bo_metadata()
2278 AMDGPU_TILING_SET(DCC_INDEPENDENT_128B, surf->u.gfx9.dcc.independent_128B_blocks); in ac_surface_get_bo_metadata()
2280 surf->u.gfx9.dcc.max_compressed_block_size); in ac_surface_get_bo_metadata()
2281 *tiling_flags |= AMDGPU_TILING_SET(SCANOUT, (surf->flags & RADEON_SURF_SCANOUT) != 0); in ac_surface_get_bo_metadata()
2283 if (surf->u.legacy.level[0].mode >= RADEON_SURF_MODE_2D) in ac_surface_get_bo_metadata()
2285 else if (surf->u.legacy.level[0].mode >= RADEON_SURF_MODE_1D) in ac_surface_get_bo_metadata()
2290 *tiling_flags |= AMDGPU_TILING_SET(PIPE_CONFIG, surf->u.legacy.pipe_config); in ac_surface_get_bo_metadata()
2291 *tiling_flags |= AMDGPU_TILING_SET(BANK_WIDTH, util_logbase2(surf->u.legacy.bankw)); in ac_surface_get_bo_metadata()
2292 *tiling_flags |= AMDGPU_TILING_SET(BANK_HEIGHT, util_logbase2(surf->u.legacy.bankh)); in ac_surface_get_bo_metadata()
2293 if (surf->u.legacy.tile_split) in ac_surface_get_bo_metadata()
2295 AMDGPU_TILING_SET(TILE_SPLIT, eg_tile_split_rev(surf->u.legacy.tile_split)); in ac_surface_get_bo_metadata()
2296 *tiling_flags |= AMDGPU_TILING_SET(MACRO_TILE_ASPECT, util_logbase2(surf->u.legacy.mtilea)); in ac_surface_get_bo_metadata()
2297 *tiling_flags |= AMDGPU_TILING_SET(NUM_BANKS, util_logbase2(surf->u.legacy.num_banks) - 1); in ac_surface_get_bo_metadata()
2299 if (surf->flags & RADEON_SURF_SCANOUT) in ac_surface_get_bo_metadata()
2312 bool ac_surface_set_umd_metadata(const struct radeon_info *info, struct radeon_surf *surf, in ac_surface_set_umd_metadata() argument
2320 offset = surf->u.gfx9.surf_offset; in ac_surface_set_umd_metadata()
2322 offset = surf->u.legacy.level[0].offset; in ac_surface_set_umd_metadata()
2329 ac_surface_zero_dcc_fields(surf); in ac_surface_set_umd_metadata()
2365 surf->dcc_offset = (uint64_t)desc[7] << 8; in ac_surface_set_umd_metadata()
2369 surf->dcc_offset = in ac_surface_set_umd_metadata()
2371 surf->u.gfx9.dcc.pipe_aligned = G_008F24_META_PIPE_ALIGNED(desc[5]); in ac_surface_set_umd_metadata()
2372 surf->u.gfx9.dcc.rb_aligned = G_008F24_META_RB_ALIGNED(desc[5]); in ac_surface_set_umd_metadata()
2375 if (!surf->u.gfx9.dcc.pipe_aligned && !surf->u.gfx9.dcc.rb_aligned) in ac_surface_set_umd_metadata()
2376 assert(surf->is_displayable); in ac_surface_set_umd_metadata()
2381 surf->dcc_offset = in ac_surface_set_umd_metadata()
2383 surf->u.gfx9.dcc.pipe_aligned = G_00A018_META_PIPE_ALIGNED(desc[6]); in ac_surface_set_umd_metadata()
2394 ac_surface_zero_dcc_fields(surf); in ac_surface_set_umd_metadata()
2400 void ac_surface_get_umd_metadata(const struct radeon_info *info, struct radeon_surf *surf, in ac_surface_get_umd_metadata() argument
2413 desc[7] = surf->dcc_offset >> 8; in ac_surface_get_umd_metadata()
2416 desc[7] = surf->dcc_offset >> 8; in ac_surface_get_umd_metadata()
2418 desc[5] |= S_008F24_META_DATA_ADDRESS(surf->dcc_offset >> 40); in ac_surface_get_umd_metadata()
2423 desc[6] |= S_00A018_META_DATA_ADDRESS_LO(surf->dcc_offset >> 8); in ac_surface_get_umd_metadata()
2424 desc[7] = surf->dcc_offset >> 16; in ac_surface_get_umd_metadata()
2452 metadata[10 + i] = surf->u.legacy.level[i].offset >> 8; in ac_surface_get_umd_metadata()
2458 void ac_surface_override_offset_stride(const struct radeon_info *info, struct radeon_surf *surf, in ac_surface_override_offset_stride() argument
2463 surf->u.gfx9.surf_pitch = pitch; in ac_surface_override_offset_stride()
2465 surf->u.gfx9.surf.epitch = pitch - 1; in ac_surface_override_offset_stride()
2466 surf->u.gfx9.surf_slice_size = (uint64_t)pitch * surf->u.gfx9.surf_height * surf->bpe; in ac_surface_override_offset_stride()
2468 surf->u.gfx9.surf_offset = offset; in ac_surface_override_offset_stride()
2469 if (surf->u.gfx9.stencil_offset) in ac_surface_override_offset_stride()
2470 surf->u.gfx9.stencil_offset += offset; in ac_surface_override_offset_stride()
2473 surf->u.legacy.level[0].nblk_x = pitch; in ac_surface_override_offset_stride()
2474 surf->u.legacy.level[0].slice_size_dw = in ac_surface_override_offset_stride()
2475 ((uint64_t)pitch * surf->u.legacy.level[0].nblk_y * surf->bpe) / 4; in ac_surface_override_offset_stride()
2479 for (unsigned i = 0; i < ARRAY_SIZE(surf->u.legacy.level); ++i) in ac_surface_override_offset_stride()
2480 surf->u.legacy.level[i].offset += offset; in ac_surface_override_offset_stride()
2484 if (surf->htile_offset) in ac_surface_override_offset_stride()
2485 surf->htile_offset += offset; in ac_surface_override_offset_stride()
2486 if (surf->fmask_offset) in ac_surface_override_offset_stride()
2487 surf->fmask_offset += offset; in ac_surface_override_offset_stride()
2488 if (surf->cmask_offset) in ac_surface_override_offset_stride()
2489 surf->cmask_offset += offset; in ac_surface_override_offset_stride()
2490 if (surf->dcc_offset) in ac_surface_override_offset_stride()
2491 surf->dcc_offset += offset; in ac_surface_override_offset_stride()
2492 if (surf->display_dcc_offset) in ac_surface_override_offset_stride()
2493 surf->display_dcc_offset += offset; in ac_surface_override_offset_stride()