Lines Matching refs:SMEM

47 ## SMEM stores
50 the offset for SMEM stores must be in m0 if IMM == 0.
52 The RDNA ISA doesn't mention SMEM stores at all, but they seem to be supported
56 ## SMEM atomics
58 RDNA ISA: same as the SMEM stores, the ISA pretends they don't exist, but they
135 ## SMEM corrupts VCCZ on SI/CI
139 After issuing a SMEM instructions, we need to wait for the SMEM instructions to
155 ### SMEM store followed by a load with the same address
161 SMEM stores, so it's not surprising that they didn't notice it.
167 Then, a SALU/SMEM instruction writes the same SGPR.
175 An SMEM instruction reads an SGPR. Then, a VALU instruction writes that same SGPR.