48         radeon_emit(cs, PKT3(PKT3_SET_CONFIG_REG, num, 0));  in radeon_set_config_reg_seq()
49         radeon_emit(cs, (reg - SI_CONFIG_REG_OFFSET) >> 2);  in radeon_set_config_reg_seq()
55         radeon_emit(cs, value);  in radeon_set_config_reg()
63         radeon_emit(cs, PKT3(PKT3_SET_CONTEXT_REG, num, 0));  in radeon_set_context_reg_seq()
64         radeon_emit(cs, (reg - SI_CONTEXT_REG_OFFSET) >> 2);  in radeon_set_context_reg_seq()
70         radeon_emit(cs, value);  in radeon_set_context_reg()
80 	radeon_emit(cs, PKT3(PKT3_SET_CONTEXT_REG, 1, 0));  in radeon_set_context_reg_idx()
81 	radeon_emit(cs, (reg - SI_CONTEXT_REG_OFFSET) >> 2 | (idx << 28));  in radeon_set_context_reg_idx()
82 	radeon_emit(cs, value);  in radeon_set_context_reg_idx()
91 	radeon_emit(cs, PKT3(PKT3_CONTEXT_REG_RMW, 2, 0));  in radeon_set_context_reg_rmw()
92 	radeon_emit(cs, (reg - SI_CONTEXT_REG_OFFSET) >> 2);  in radeon_set_context_reg_rmw()
93 	radeon_emit(cs, mask);  in radeon_set_context_reg_rmw()
94 	radeon_emit(cs, value);  in radeon_set_context_reg_rmw()
102 	radeon_emit(cs, PKT3(PKT3_SET_SH_REG, num, 0));  in radeon_set_sh_reg_seq()
103 	radeon_emit(cs, (reg - SI_SH_REG_OFFSET) >> 2);  in radeon_set_sh_reg_seq()
109 	radeon_emit(cs, value);  in radeon_set_sh_reg()
125 	radeon_emit(cs, PKT3(opcode, 1, 0));  in radeon_set_sh_reg_idx()
126 	radeon_emit(cs, (reg - SI_SH_REG_OFFSET) >> 2 | (idx << 28));  in radeon_set_sh_reg_idx()
127 	radeon_emit(cs, value);  in radeon_set_sh_reg_idx()
135 	radeon_emit(cs, PKT3(PKT3_SET_UCONFIG_REG, num, 0));  in radeon_set_uconfig_reg_seq()
136 	radeon_emit(cs, (reg - CIK_UCONFIG_REG_OFFSET) >> 2);  in radeon_set_uconfig_reg_seq()
145 	radeon_emit(cs, PKT3(PKT3_SET_UCONFIG_REG, num, 1));  in radeon_set_uconfig_reg_seq_perfctr()
146 	radeon_emit(cs, (reg - CIK_UCONFIG_REG_OFFSET) >> 2);  in radeon_set_uconfig_reg_seq_perfctr()
152 	radeon_emit(cs, value);  in radeon_set_uconfig_reg()
169 	radeon_emit(cs, PKT3(opcode, 1, 0));  in radeon_set_uconfig_reg_idx()
170 	radeon_emit(cs, (reg - CIK_UCONFIG_REG_OFFSET) >> 2 | (idx << 28));  in radeon_set_uconfig_reg_idx()
171 	radeon_emit(cs, value);  in radeon_set_uconfig_reg_idx()
181 	radeon_emit(cs, PKT3(PKT3_COPY_DATA, 4, 0));  in radeon_set_privileged_config_reg()
182 	radeon_emit(cs, COPY_DATA_SRC_SEL(COPY_DATA_IMM) |  in radeon_set_privileged_config_reg()
184 	radeon_emit(cs, value);  in radeon_set_privileged_config_reg()
185 	radeon_emit(cs, 0); /* unused */  in radeon_set_privileged_config_reg()
186 	radeon_emit(cs, reg >> 2);  in radeon_set_privileged_config_reg()
187 	radeon_emit(cs, 0); /* unused */  in radeon_set_privileged_config_reg()