Lines Matching refs:ctx_cs
3986 radv_pipeline_generate_depth_stencil_state(struct radeon_cmdbuf *ctx_cs, in radv_pipeline_generate_depth_stencil_state() argument
4041 radeon_set_context_reg(ctx_cs, R_028000_DB_RENDER_CONTROL, db_render_control); in radv_pipeline_generate_depth_stencil_state()
4042 radeon_set_context_reg(ctx_cs, R_02800C_DB_RENDER_OVERRIDE, db_render_override); in radv_pipeline_generate_depth_stencil_state()
4043 radeon_set_context_reg(ctx_cs, R_028010_DB_RENDER_OVERRIDE2, db_render_override2); in radv_pipeline_generate_depth_stencil_state()
4047 radv_pipeline_generate_blend_state(struct radeon_cmdbuf *ctx_cs, in radv_pipeline_generate_blend_state() argument
4051 radeon_set_context_reg_seq(ctx_cs, R_028780_CB_BLEND0_CONTROL, 8); in radv_pipeline_generate_blend_state()
4052 radeon_emit_array(ctx_cs, blend->cb_blend_control, in radv_pipeline_generate_blend_state()
4054 radeon_set_context_reg(ctx_cs, R_028808_CB_COLOR_CONTROL, blend->cb_color_control); in radv_pipeline_generate_blend_state()
4055 radeon_set_context_reg(ctx_cs, R_028B70_DB_ALPHA_TO_MASK, blend->db_alpha_to_mask); in radv_pipeline_generate_blend_state()
4059 radeon_set_context_reg_seq(ctx_cs, R_028760_SX_MRT0_BLEND_OPT, 8); in radv_pipeline_generate_blend_state()
4060 radeon_emit_array(ctx_cs, blend->sx_mrt_blend_opt, 8); in radv_pipeline_generate_blend_state()
4063 radeon_set_context_reg(ctx_cs, R_028714_SPI_SHADER_COL_FORMAT, blend->spi_shader_col_format); in radv_pipeline_generate_blend_state()
4065 radeon_set_context_reg(ctx_cs, R_028238_CB_TARGET_MASK, blend->cb_target_mask); in radv_pipeline_generate_blend_state()
4066 radeon_set_context_reg(ctx_cs, R_02823C_CB_SHADER_MASK, blend->cb_shader_mask); in radv_pipeline_generate_blend_state()
4070 radv_pipeline_generate_raster_state(struct radeon_cmdbuf *ctx_cs, in radv_pipeline_generate_raster_state() argument
4086 radeon_set_context_reg(ctx_cs, R_028810_PA_CL_CLIP_CNTL, in radv_pipeline_generate_raster_state()
4093 radeon_set_context_reg(ctx_cs, R_028BDC_PA_SC_LINE_CNTL, in radv_pipeline_generate_raster_state()
4120 radeon_set_context_reg(ctx_cs, R_028C4C_PA_SC_CONSERVATIVE_RASTERIZATION_CNTL, in radv_pipeline_generate_raster_state()
4126 radv_pipeline_generate_multisample_state(struct radeon_cmdbuf *ctx_cs, in radv_pipeline_generate_multisample_state() argument
4131 radeon_set_context_reg_seq(ctx_cs, R_028C38_PA_SC_AA_MASK_X0Y0_X1Y0, 2); in radv_pipeline_generate_multisample_state()
4132 radeon_emit(ctx_cs, ms->pa_sc_aa_mask[0]); in radv_pipeline_generate_multisample_state()
4133 radeon_emit(ctx_cs, ms->pa_sc_aa_mask[1]); in radv_pipeline_generate_multisample_state()
4135 radeon_set_context_reg(ctx_cs, R_028804_DB_EQAA, ms->db_eqaa); in radv_pipeline_generate_multisample_state()
4136 radeon_set_context_reg(ctx_cs, R_028A48_PA_SC_MODE_CNTL_0, ms->pa_sc_mode_cntl_0); in radv_pipeline_generate_multisample_state()
4137 radeon_set_context_reg(ctx_cs, R_028A4C_PA_SC_MODE_CNTL_1, ms->pa_sc_mode_cntl_1); in radv_pipeline_generate_multisample_state()
4138 radeon_set_context_reg(ctx_cs, R_028BE0_PA_SC_AA_CONFIG, ms->pa_sc_aa_config); in radv_pipeline_generate_multisample_state()
4145 radeon_set_context_reg(ctx_cs, R_02882C_PA_SU_PRIM_FILTER_CNTL, in radv_pipeline_generate_multisample_state()
4151 radeon_emit(ctx_cs, PKT3(PKT3_EVENT_WRITE, 0, 0)); in radv_pipeline_generate_multisample_state()
4152 radeon_emit(ctx_cs, EVENT_TYPE(V_028A90_FLUSH_DFSM) | EVENT_INDEX(0)); in radv_pipeline_generate_multisample_state()
4157 radv_pipeline_generate_vgt_gs_mode(struct radeon_cmdbuf *ctx_cs, in radv_pipeline_generate_vgt_gs_mode() argument
4182 radeon_set_context_reg(ctx_cs, R_028A84_VGT_PRIMITIVEID_EN, vgt_primitiveid_en); in radv_pipeline_generate_vgt_gs_mode()
4183 radeon_set_context_reg(ctx_cs, R_028A40_VGT_GS_MODE, vgt_gs_mode); in radv_pipeline_generate_vgt_gs_mode()
4187 radv_pipeline_generate_hw_vs(struct radeon_cmdbuf *ctx_cs, in radv_pipeline_generate_hw_vs() argument
4218 radeon_set_context_reg(ctx_cs, R_0286C4_SPI_VS_OUT_CONFIG, spi_vs_out_config); in radv_pipeline_generate_hw_vs()
4220 radeon_set_context_reg(ctx_cs, R_02870C_SPI_SHADER_POS_FORMAT, in radv_pipeline_generate_hw_vs()
4232 radeon_set_context_reg(ctx_cs, R_02881C_PA_CL_VS_OUT_CNTL, in radv_pipeline_generate_hw_vs()
4246 radeon_set_context_reg(ctx_cs, R_028AB4_VGT_REUSE_OFF, in radv_pipeline_generate_hw_vs()
4288 radv_pipeline_generate_hw_ngg(struct radeon_cmdbuf *ctx_cs, in radv_pipeline_generate_hw_ngg() argument
4330 radeon_set_context_reg(ctx_cs, R_0286C4_SPI_VS_OUT_CONFIG, in radv_pipeline_generate_hw_ngg()
4334 radeon_set_context_reg(ctx_cs, R_028708_SPI_SHADER_IDX_FORMAT, in radv_pipeline_generate_hw_ngg()
4336 radeon_set_context_reg(ctx_cs, R_02870C_SPI_SHADER_POS_FORMAT, in radv_pipeline_generate_hw_ngg()
4348 radeon_set_context_reg(ctx_cs, R_02881C_PA_CL_VS_OUT_CNTL, in radv_pipeline_generate_hw_ngg()
4361 radeon_set_context_reg(ctx_cs, R_028A84_VGT_PRIMITIVEID_EN, in radv_pipeline_generate_hw_ngg()
4365 radeon_set_context_reg(ctx_cs, R_028AAC_VGT_ESGS_RING_ITEMSIZE, in radv_pipeline_generate_hw_ngg()
4372 radeon_set_context_reg(ctx_cs, R_028A44_VGT_GS_ONCHIP_CNTL, in radv_pipeline_generate_hw_ngg()
4376 radeon_set_context_reg(ctx_cs, R_0287FC_GE_MAX_OUTPUT_PER_SUBGROUP, in radv_pipeline_generate_hw_ngg()
4378 radeon_set_context_reg(ctx_cs, R_028B4C_GE_NGG_SUBGRP_CNTL, in radv_pipeline_generate_hw_ngg()
4381 radeon_set_context_reg(ctx_cs, R_028B90_VGT_GS_INSTANCE_CNT, in radv_pipeline_generate_hw_ngg()
4394 radeon_set_context_reg(ctx_cs, R_028838_PA_CL_NGG_CNTL, in radv_pipeline_generate_hw_ngg()
4419 radeon_set_uconfig_reg(ctx_cs, R_03096C_GE_CNTL, ge_cntl); in radv_pipeline_generate_hw_ngg()
4453 radv_pipeline_generate_vertex_shader(struct radeon_cmdbuf *ctx_cs, in radv_pipeline_generate_vertex_shader() argument
4469 radv_pipeline_generate_hw_ngg(ctx_cs, cs, pipeline, vs); in radv_pipeline_generate_vertex_shader()
4471 radv_pipeline_generate_hw_vs(ctx_cs, cs, pipeline, vs); in radv_pipeline_generate_vertex_shader()
4475 radv_pipeline_generate_tess_shaders(struct radeon_cmdbuf *ctx_cs, in radv_pipeline_generate_tess_shaders() argument
4486 radv_pipeline_generate_hw_ngg(ctx_cs, cs, pipeline, tes); in radv_pipeline_generate_tess_shaders()
4490 radv_pipeline_generate_hw_vs(ctx_cs, cs, pipeline, tes); in radv_pipeline_generate_tess_shaders()
4497 radeon_set_context_reg(ctx_cs, R_028A44_VGT_GS_ONCHIP_CNTL, in radv_pipeline_generate_tess_shaders()
4505 radv_pipeline_generate_tess_state(struct radeon_cmdbuf *ctx_cs, in radv_pipeline_generate_tess_state() argument
4523 radeon_set_context_reg_idx(ctx_cs, R_028B58_VGT_LS_HS_CONFIG, in radv_pipeline_generate_tess_state()
4526 radeon_set_context_reg(ctx_cs, R_028B58_VGT_LS_HS_CONFIG, in radv_pipeline_generate_tess_state()
4582 radeon_set_context_reg(ctx_cs, R_028B6C_VGT_TF_PARAM, in radv_pipeline_generate_tess_state()
4590 radv_pipeline_generate_hw_gs(struct radeon_cmdbuf *ctx_cs, in radv_pipeline_generate_hw_gs() argument
4608 radeon_set_context_reg_seq(ctx_cs, R_028A60_VGT_GSVS_RING_OFFSET_1, 3); in radv_pipeline_generate_hw_gs()
4609 radeon_emit(ctx_cs, offset); in radv_pipeline_generate_hw_gs()
4612 radeon_emit(ctx_cs, offset); in radv_pipeline_generate_hw_gs()
4615 radeon_emit(ctx_cs, offset); in radv_pipeline_generate_hw_gs()
4618 radeon_set_context_reg(ctx_cs, R_028AB0_VGT_GSVS_RING_ITEMSIZE, offset); in radv_pipeline_generate_hw_gs()
4620 radeon_set_context_reg_seq(ctx_cs, R_028B5C_VGT_GS_VERT_ITEMSIZE, 4); in radv_pipeline_generate_hw_gs()
4621 radeon_emit(ctx_cs, num_components[0]); in radv_pipeline_generate_hw_gs()
4622 radeon_emit(ctx_cs, (max_stream >= 1) ? num_components[1] : 0); in radv_pipeline_generate_hw_gs()
4623 radeon_emit(ctx_cs, (max_stream >= 2) ? num_components[2] : 0); in radv_pipeline_generate_hw_gs()
4624 radeon_emit(ctx_cs, (max_stream >= 3) ? num_components[3] : 0); in radv_pipeline_generate_hw_gs()
4627 radeon_set_context_reg(ctx_cs, R_028B90_VGT_GS_INSTANCE_CNT, in radv_pipeline_generate_hw_gs()
4631 radeon_set_context_reg(ctx_cs, R_028AAC_VGT_ESGS_RING_ITEMSIZE, in radv_pipeline_generate_hw_gs()
4651 radeon_set_context_reg(ctx_cs, R_028A44_VGT_GS_ONCHIP_CNTL, gs_state->vgt_gs_onchip_cntl); in radv_pipeline_generate_hw_gs()
4652 …radeon_set_context_reg(ctx_cs, R_028A94_VGT_GS_MAX_PRIMS_PER_SUBGROUP, gs_state->vgt_gs_max_prims_… in radv_pipeline_generate_hw_gs()
4661 radv_pipeline_generate_hw_vs(ctx_cs, cs, pipeline, pipeline->gs_copy_shader); in radv_pipeline_generate_hw_gs()
4665 radv_pipeline_generate_geometry_shader(struct radeon_cmdbuf *ctx_cs, in radv_pipeline_generate_geometry_shader() argument
4676 radv_pipeline_generate_hw_ngg(ctx_cs, cs, pipeline, gs); in radv_pipeline_generate_geometry_shader()
4678 radv_pipeline_generate_hw_gs(ctx_cs, cs, pipeline, gs); in radv_pipeline_generate_geometry_shader()
4680 radeon_set_context_reg(ctx_cs, R_028B38_VGT_GS_MAX_VERT_OUT, in radv_pipeline_generate_geometry_shader()
4714 radv_pipeline_generate_ps_inputs(struct radeon_cmdbuf *ctx_cs, in radv_pipeline_generate_ps_inputs() argument
4798 radeon_set_context_reg_seq(ctx_cs, R_028644_SPI_PS_INPUT_CNTL_0, ps_offset); in radv_pipeline_generate_ps_inputs()
4800 radeon_emit(ctx_cs, ps_input_cntl[i]); in radv_pipeline_generate_ps_inputs()
4845 radv_pipeline_generate_fragment_shader(struct radeon_cmdbuf *ctx_cs, in radv_pipeline_generate_fragment_shader() argument
4862 radeon_set_context_reg(ctx_cs, R_02880C_DB_SHADER_CONTROL, in radv_pipeline_generate_fragment_shader()
4866 radeon_set_context_reg(ctx_cs, R_0286CC_SPI_PS_INPUT_ENA, in radv_pipeline_generate_fragment_shader()
4869 radeon_set_context_reg(ctx_cs, R_0286D0_SPI_PS_INPUT_ADDR, in radv_pipeline_generate_fragment_shader()
4872 radeon_set_context_reg(ctx_cs, R_0286D8_SPI_PS_IN_CONTROL, in radv_pipeline_generate_fragment_shader()
4876 radeon_set_context_reg(ctx_cs, R_0286E0_SPI_BARYC_CNTL, pipeline->graphics.spi_baryc_cntl); in radv_pipeline_generate_fragment_shader()
4878 radeon_set_context_reg(ctx_cs, R_028710_SPI_SHADER_Z_FORMAT, in radv_pipeline_generate_fragment_shader()
4891 radv_pipeline_generate_vgt_vertex_reuse(struct radeon_cmdbuf *ctx_cs, in radv_pipeline_generate_vgt_vertex_reuse() argument
4903 radeon_set_context_reg(ctx_cs, R_028C58_VGT_VERTEX_REUSE_BLOCK_CNTL, in radv_pipeline_generate_vgt_vertex_reuse()
4908 radv_pipeline_generate_vgt_shader_config(struct radeon_cmdbuf *ctx_cs, in radv_pipeline_generate_vgt_shader_config() argument
4967 radeon_set_context_reg(ctx_cs, R_028B54_VGT_SHADER_STAGES_EN, stages); in radv_pipeline_generate_vgt_shader_config()
4971 radv_pipeline_generate_cliprect_rule(struct radeon_cmdbuf *ctx_cs, in radv_pipeline_generate_cliprect_rule() argument
5001 radeon_set_context_reg(ctx_cs, R_02820C_PA_SC_CLIPRECT_RULE, cliprect_rule); in radv_pipeline_generate_cliprect_rule()
5005 gfx10_pipeline_generate_ge_cntl(struct radeon_cmdbuf *ctx_cs, in gfx10_pipeline_generate_ge_cntl() argument
5029 radeon_set_uconfig_reg(ctx_cs, R_03096C_GE_CNTL, in gfx10_pipeline_generate_ge_cntl()
5037 radv_pipeline_generate_vgt_gs_out(struct radeon_cmdbuf *ctx_cs, in radv_pipeline_generate_vgt_gs_out() argument
5062 radeon_set_context_reg(ctx_cs, R_028A6C_VGT_GS_OUT_PRIM_TYPE, gs_out); in radv_pipeline_generate_vgt_gs_out()
5071 struct radeon_cmdbuf *ctx_cs = &pipeline->ctx_cs; in radv_pipeline_generate_pm4() local
5075 ctx_cs->max_dw = 256; in radv_pipeline_generate_pm4()
5076 cs->buf = malloc(4 * (cs->max_dw + ctx_cs->max_dw)); in radv_pipeline_generate_pm4()
5077 ctx_cs->buf = cs->buf + cs->max_dw; in radv_pipeline_generate_pm4()
5079 radv_pipeline_generate_depth_stencil_state(ctx_cs, pipeline, pCreateInfo, extra); in radv_pipeline_generate_pm4()
5080 radv_pipeline_generate_blend_state(ctx_cs, pipeline, blend); in radv_pipeline_generate_pm4()
5081 radv_pipeline_generate_raster_state(ctx_cs, pipeline, pCreateInfo); in radv_pipeline_generate_pm4()
5082 radv_pipeline_generate_multisample_state(ctx_cs, pipeline); in radv_pipeline_generate_pm4()
5083 radv_pipeline_generate_vgt_gs_mode(ctx_cs, pipeline); in radv_pipeline_generate_pm4()
5084 radv_pipeline_generate_vertex_shader(ctx_cs, cs, pipeline); in radv_pipeline_generate_pm4()
5087 radv_pipeline_generate_tess_shaders(ctx_cs, cs, pipeline); in radv_pipeline_generate_pm4()
5088 radv_pipeline_generate_tess_state(ctx_cs, pipeline, pCreateInfo); in radv_pipeline_generate_pm4()
5091 radv_pipeline_generate_geometry_shader(ctx_cs, cs, pipeline); in radv_pipeline_generate_pm4()
5092 radv_pipeline_generate_fragment_shader(ctx_cs, cs, pipeline); in radv_pipeline_generate_pm4()
5093 radv_pipeline_generate_ps_inputs(ctx_cs, pipeline); in radv_pipeline_generate_pm4()
5094 radv_pipeline_generate_vgt_vertex_reuse(ctx_cs, pipeline); in radv_pipeline_generate_pm4()
5095 radv_pipeline_generate_vgt_shader_config(ctx_cs, pipeline); in radv_pipeline_generate_pm4()
5096 radv_pipeline_generate_cliprect_rule(ctx_cs, pCreateInfo); in radv_pipeline_generate_pm4()
5097 radv_pipeline_generate_vgt_gs_out(ctx_cs, pipeline, pCreateInfo, extra); in radv_pipeline_generate_pm4()
5100 gfx10_pipeline_generate_ge_cntl(ctx_cs, pipeline); in radv_pipeline_generate_pm4()
5102 pipeline->ctx_cs_hash = _mesa_hash_data(ctx_cs->buf, ctx_cs->cdw * 4); in radv_pipeline_generate_pm4()
5104 assert(ctx_cs->cdw <= ctx_cs->max_dw); in radv_pipeline_generate_pm4()