Lines Matching full:info
29 struct radv_shader_info *info) in mark_sampler_desc() argument
31 info->desc_set_used_mask |= (1u << var->data.descriptor_set); in mark_sampler_desc()
37 struct radv_shader_info *info) in gather_intrinsic_load_input_info() argument
39 switch (nir->info.stage) { in gather_intrinsic_load_input_info()
45 info->vs.input_usage_mask[idx] |= mask << component; in gather_intrinsic_load_input_info()
63 set_writes_memory(const nir_shader *nir, struct radv_shader_info *info) in set_writes_memory() argument
65 if (nir->info.stage == MESA_SHADER_FRAGMENT) in set_writes_memory()
66 info->ps.writes_memory = true; in set_writes_memory()
72 struct radv_shader_info *info) in gather_intrinsic_store_output_info() argument
83 switch (nir->info.stage) { in gather_intrinsic_store_output_info()
85 output_usage_mask = info->vs.output_usage_mask; in gather_intrinsic_store_output_info()
88 output_usage_mask = info->tes.output_usage_mask; in gather_intrinsic_store_output_info()
91 output_usage_mask = info->gs.output_usage_mask; in gather_intrinsic_store_output_info()
108 struct radv_shader_info *info) in gather_push_constant_info() argument
113 info->has_indirect_push_constants = true; in gather_push_constant_info()
118 info->max_push_constant_used = in gather_push_constant_info()
119 MAX2(max, info->max_push_constant_used); in gather_push_constant_info()
120 info->min_push_constant_used = in gather_push_constant_info()
121 MIN2(min, info->min_push_constant_used); in gather_push_constant_info()
125 info->has_only_32bit_push_constants = false; in gather_push_constant_info()
127 info->loads_push_constants = true; in gather_push_constant_info()
132 struct radv_shader_info *info) in gather_intrinsic_info() argument
136 info->ps.needs_sample_positions = true; in gather_intrinsic_info()
139 info->vs.needs_draw_id = true; in gather_intrinsic_info()
142 info->vs.needs_instance_id = true; in gather_intrinsic_info()
145 info->cs.uses_grid_size = true; in gather_intrinsic_info()
154 info->cs.uses_block_id[i] = true; in gather_intrinsic_info()
156 info->cs.uses_thread_id[i] = true; in gather_intrinsic_info()
163 info->cs.uses_local_invocation_idx = true; in gather_intrinsic_info()
166 info->ps.force_persample = true; in gather_intrinsic_info()
169 info->ps.force_persample = true; in gather_intrinsic_info()
172 info->needs_multiview_view_index = true; in gather_intrinsic_info()
173 if (nir->info.stage == MESA_SHADER_FRAGMENT) in gather_intrinsic_info()
174 info->ps.layer_input = true; in gather_intrinsic_info()
177 if (nir->info.stage == MESA_SHADER_FRAGMENT) in gather_intrinsic_info()
178 info->ps.layer_input = true; in gather_intrinsic_info()
181 info->uses_invocation_id = true; in gather_intrinsic_info()
184 info->uses_prim_id = true; in gather_intrinsic_info()
187 gather_push_constant_info(nir, instr, info); in gather_intrinsic_info()
190 info->desc_set_used_mask |= (1u << nir_intrinsic_desc_set(instr)); in gather_intrinsic_info()
206 mark_sampler_desc(var, info); in gather_intrinsic_info()
219 set_writes_memory(nir, info); in gather_intrinsic_info()
245 set_writes_memory(nir, info); in gather_intrinsic_info()
248 gather_intrinsic_load_input_info(nir, instr, info); in gather_intrinsic_info()
251 gather_intrinsic_store_output_info(nir, instr, info); in gather_intrinsic_info()
260 struct radv_shader_info *info) in gather_tex_info() argument
265 mark_sampler_desc(nir_deref_instr_get_variable(nir_src_as_deref(instr->src[i].src)), info); in gather_tex_info()
268 mark_sampler_desc(nir_deref_instr_get_variable(nir_src_as_deref(instr->src[i].src)), info); in gather_tex_info()
278 struct radv_shader_info *info) in gather_info_block() argument
283 gather_intrinsic_info(nir, nir_instr_as_intrinsic(instr), info); in gather_info_block()
286 gather_tex_info(nir, nir_instr_as_tex(instr), info); in gather_info_block()
296 struct radv_shader_info *info, in gather_info_input_decl_vs() argument
303 info->vs.has_vertex_buffers = true; in gather_info_input_decl_vs()
309 info->vs.needs_instance_id = true; in gather_info_input_decl_vs()
314 mark_16bit_ps_input(struct radv_shader_info *info, const struct glsl_type *type, in mark_16bit_ps_input() argument
320 info->ps.float16_shaded_mask |= ((1ull << attrib_count) - 1) << location; in mark_16bit_ps_input()
325 mark_16bit_ps_input(info, glsl_get_array_element(type), location + i * stride); in mark_16bit_ps_input()
330 mark_16bit_ps_input(info, glsl_get_struct_field(type, i), location); in mark_16bit_ps_input()
337 struct radv_shader_info *info) in gather_info_input_decl_ps() argument
345 info->ps.has_pcoord = true; in gather_info_input_decl_ps()
348 info->ps.prim_id_input = true; in gather_info_input_decl_ps()
351 info->ps.layer_input = true; in gather_info_input_decl_ps()
355 info->ps.num_input_clips_culls += attrib_count; in gather_info_input_decl_ps()
358 info->ps.viewport_index_input = true; in gather_info_input_decl_ps()
366 info->ps.force_persample = true; in gather_info_input_decl_ps()
374 mark_16bit_ps_input(info, var->type, var->data.driver_location); in gather_info_input_decl_ps()
380 info->ps.flat_shaded_mask |= mask << var->data.driver_location; in gather_info_input_decl_ps()
382 info->ps.explicit_shaded_mask |= mask << var->data.driver_location; in gather_info_input_decl_ps()
385 info->ps.input_mask |= mask << (var->data.location - VARYING_SLOT_VAR0); in gather_info_input_decl_ps()
390 struct radv_shader_info *info, in gather_info_input_decl() argument
393 switch (nir->info.stage) { in gather_info_input_decl()
395 gather_info_input_decl_vs(nir, var, info, key); in gather_info_input_decl()
398 gather_info_input_decl_ps(nir, var, info); in gather_info_input_decl()
407 struct radv_shader_info *info) in gather_info_output_decl_ps() argument
413 info->ps.writes_z = true; in gather_info_output_decl_ps()
416 info->ps.writes_stencil = true; in gather_info_output_decl_ps()
419 info->ps.writes_sample_mask = true; in gather_info_output_decl_ps()
432 info->ps.cb_shader_mask |= write_mask << ((slot + i) * 4); in gather_info_output_decl_ps()
439 struct radv_shader_info *info) in gather_info_output_decl_gs() argument
447 info->gs.max_stream = MAX2(info->gs.max_stream, stream); in gather_info_output_decl_gs()
448 info->gs.num_stream_output_components[stream] += num_components; in gather_info_output_decl_gs()
449 info->gs.output_streams[idx] = stream; in gather_info_output_decl_gs()
454 struct radv_shader_info *info, in gather_info_output_decl() argument
459 switch (nir->info.stage) { in gather_info_output_decl()
461 gather_info_output_decl_ps(nir, var, info); in gather_info_output_decl()
466 vs_info = &info->vs.outinfo; in gather_info_output_decl()
470 gather_info_output_decl_gs(nir, var, info); in gather_info_output_decl()
473 vs_info = &info->vs.outinfo; in gather_info_output_decl()
474 gather_info_output_decl_gs(nir, var, info); in gather_info_output_decl()
478 vs_info = &info->tes.outinfo; in gather_info_output_decl()
488 (1 << nir->info.clip_distance_array_size) - 1; in gather_info_output_decl()
490 (1 << nir->info.cull_distance_array_size) - 1; in gather_info_output_decl()
491 vs_info->cull_dist_mask <<= nir->info.clip_distance_array_size; in gather_info_output_decl()
509 gather_xfb_info(const nir_shader *nir, struct radv_shader_info *info) in gather_xfb_info() argument
512 struct radv_streamout_info *so = &info->so; in gather_xfb_info()
542 radv_nir_shader_info_init(struct radv_shader_info *info) in radv_nir_shader_info_init() argument
545 info->min_push_constant_used = UINT8_MAX; in radv_nir_shader_info_init()
546 info->has_only_32bit_push_constants = true; in radv_nir_shader_info_init()
553 struct radv_shader_info *info) in radv_nir_shader_info_pass() argument
559 (layout->dynamic_shader_stages & mesa_to_vk_shader_stage(nir->info.stage))) { in radv_nir_shader_info_pass()
560 info->loads_push_constants = true; in radv_nir_shader_info_pass()
561 info->loads_dynamic_offsets = true; in radv_nir_shader_info_pass()
565 gather_info_input_decl(nir, variable, info, key); in radv_nir_shader_info_pass()
568 gather_info_block(nir, block, info); in radv_nir_shader_info_pass()
572 gather_info_output_decl(nir, variable, info, key); in radv_nir_shader_info_pass()
574 if (nir->info.stage == MESA_SHADER_VERTEX || in radv_nir_shader_info_pass()
575 nir->info.stage == MESA_SHADER_TESS_EVAL || in radv_nir_shader_info_pass()
576 nir->info.stage == MESA_SHADER_GEOMETRY) in radv_nir_shader_info_pass()
577 gather_xfb_info(nir, info); in radv_nir_shader_info_pass()
581 switch (nir->info.stage) { in radv_nir_shader_info_pass()
583 info->vs.output_usage_mask[VARYING_SLOT_LAYER] |= 0x1; in radv_nir_shader_info_pass()
586 info->tes.output_usage_mask[VARYING_SLOT_LAYER] |= 0x1; in radv_nir_shader_info_pass()
589 info->gs.output_usage_mask[VARYING_SLOT_LAYER] |= 0x1; in radv_nir_shader_info_pass()
598 switch (nir->info.stage) { in radv_nir_shader_info_pass()
600 info->vs.outinfo.writes_layer = true; in radv_nir_shader_info_pass()
603 info->tes.outinfo.writes_layer = true; in radv_nir_shader_info_pass()
606 info->vs.outinfo.writes_layer = true; in radv_nir_shader_info_pass()
615 switch (nir->info.stage) { in radv_nir_shader_info_pass()
617 info->vs.outinfo.export_prim_id = true; in radv_nir_shader_info_pass()
620 info->tes.outinfo.export_prim_id = true; in radv_nir_shader_info_pass()
623 info->vs.outinfo.export_prim_id = true; in radv_nir_shader_info_pass()
632 switch (nir->info.stage) { in radv_nir_shader_info_pass()
634 info->vs.output_usage_mask[VARYING_SLOT_VIEWPORT] |= 0x1; in radv_nir_shader_info_pass()
637 info->tes.output_usage_mask[VARYING_SLOT_VIEWPORT] |= 0x1; in radv_nir_shader_info_pass()
640 info->gs.output_usage_mask[VARYING_SLOT_VIEWPORT] |= 0x1; in radv_nir_shader_info_pass()
647 if (nir->info.stage == MESA_SHADER_FRAGMENT) in radv_nir_shader_info_pass()
648 info->ps.num_interp = nir->num_inputs; in radv_nir_shader_info_pass()
650 switch (nir->info.stage) { in radv_nir_shader_info_pass()
653 info->cs.block_size[i] = nir->info.cs.local_size[i]; in radv_nir_shader_info_pass()
656 info->ps.can_discard = nir->info.fs.uses_discard; in radv_nir_shader_info_pass()
657 info->ps.early_fragment_test = nir->info.fs.early_fragment_tests; in radv_nir_shader_info_pass()
658 info->ps.post_depth_coverage = nir->info.fs.post_depth_coverage; in radv_nir_shader_info_pass()
659 info->ps.depth_layout = nir->info.fs.depth_layout; in radv_nir_shader_info_pass()
662 info->gs.vertices_in = nir->info.gs.vertices_in; in radv_nir_shader_info_pass()
663 info->gs.vertices_out = nir->info.gs.vertices_out; in radv_nir_shader_info_pass()
664 info->gs.output_prim = nir->info.gs.output_primitive; in radv_nir_shader_info_pass()
665 info->gs.invocations = nir->info.gs.invocations; in radv_nir_shader_info_pass()
668 info->tes.primitive_mode = nir->info.tess.primitive_mode; in radv_nir_shader_info_pass()
669 info->tes.spacing = nir->info.tess.spacing; in radv_nir_shader_info_pass()
670 info->tes.ccw = nir->info.tess.ccw; in radv_nir_shader_info_pass()
671 info->tes.point_mode = nir->info.tess.point_mode; in radv_nir_shader_info_pass()
672 info->tes.as_es = key->vs_common_out.as_es; in radv_nir_shader_info_pass()
673 info->tes.export_prim_id = key->vs_common_out.export_prim_id; in radv_nir_shader_info_pass()
674 info->is_ngg = key->vs_common_out.as_ngg; in radv_nir_shader_info_pass()
675 info->is_ngg_passthrough = key->vs_common_out.as_ngg_passthrough; in radv_nir_shader_info_pass()
678 info->tcs.tcs_vertices_out = nir->info.tess.tcs_vertices_out; in radv_nir_shader_info_pass()
681 info->vs.as_es = key->vs_common_out.as_es; in radv_nir_shader_info_pass()
682 info->vs.as_ls = key->vs_common_out.as_ls; in radv_nir_shader_info_pass()
683 info->vs.export_prim_id = key->vs_common_out.export_prim_id; in radv_nir_shader_info_pass()
684 info->is_ngg = key->vs_common_out.as_ngg; in radv_nir_shader_info_pass()
685 info->is_ngg_passthrough = key->vs_common_out.as_ngg_passthrough; in radv_nir_shader_info_pass()
691 if (nir->info.stage == MESA_SHADER_GEOMETRY) { in radv_nir_shader_info_pass()
692 unsigned add_clip = nir->info.clip_distance_array_size + in radv_nir_shader_info_pass()
693 nir->info.cull_distance_array_size > 4; in radv_nir_shader_info_pass()
694 info->gs.gsvs_vertex_size = in radv_nir_shader_info_pass()
695 (util_bitcount64(nir->info.outputs_written) + add_clip) * 16; in radv_nir_shader_info_pass()
696 info->gs.max_gsvs_emit_size = in radv_nir_shader_info_pass()
697 info->gs.gsvs_vertex_size * nir->info.gs.vertices_out; in radv_nir_shader_info_pass()
701 if ((nir->info.stage == MESA_SHADER_VERTEX || in radv_nir_shader_info_pass()
702 nir->info.stage == MESA_SHADER_TESS_EVAL) && in radv_nir_shader_info_pass()
705 nir->info.stage == MESA_SHADER_VERTEX ? &info->vs.es_info : &info->tes.es_info; in radv_nir_shader_info_pass()
706 uint32_t num_outputs_written = nir->info.stage == MESA_SHADER_VERTEX in radv_nir_shader_info_pass()
707 ? info->vs.num_linked_outputs in radv_nir_shader_info_pass()
708 : info->tes.num_linked_outputs; in radv_nir_shader_info_pass()
712 info->float_controls_mode = nir->info.float_controls_execution_mode; in radv_nir_shader_info_pass()
714 if (nir->info.stage == MESA_SHADER_FRAGMENT) { in radv_nir_shader_info_pass()
720 unsigned num_targets = (util_last_bit(info->ps.cb_shader_mask) + 3) / 4; in radv_nir_shader_info_pass()
722 if (!(info->ps.cb_shader_mask & (0xfu << (i * 4)))) { in radv_nir_shader_info_pass()
723 info->ps.cb_shader_mask |= 0xfu << (i * 4); in radv_nir_shader_info_pass()
728 info->ps.cb_shader_mask |= (info->ps.cb_shader_mask & 0xf) << 4; in radv_nir_shader_info_pass()