943                  const struct v3d_qpu_instr *instr, uint64_t *packed_instr)  in v3d_qpu_add_pack()  argument
998                 *packed_instr |= VC5_QPU_MA;  in v3d_qpu_add_pack()
1148         *packed_instr |= QPU_SET_FIELD(mux_a, VC5_QPU_ADD_A);  in v3d_qpu_add_pack()
1149         *packed_instr |= QPU_SET_FIELD(mux_b, VC5_QPU_ADD_B);  in v3d_qpu_add_pack()
1150         *packed_instr |= QPU_SET_FIELD(opcode, VC5_QPU_OP_ADD);  in v3d_qpu_add_pack()
1151         *packed_instr |= QPU_SET_FIELD(waddr, V3D_QPU_WADDR_A);  in v3d_qpu_add_pack()
1153                 *packed_instr |= VC5_QPU_MA;  in v3d_qpu_add_pack()
1160                  const struct v3d_qpu_instr *instr, uint64_t *packed_instr)  in v3d_qpu_mul_pack()  argument
1256         *packed_instr |= QPU_SET_FIELD(mux_a, VC5_QPU_MUL_A);  in v3d_qpu_mul_pack()
1257         *packed_instr |= QPU_SET_FIELD(mux_b, VC5_QPU_MUL_B);  in v3d_qpu_mul_pack()
1259         *packed_instr |= QPU_SET_FIELD(opcode, VC5_QPU_OP_MUL);  in v3d_qpu_mul_pack()
1260         *packed_instr |= QPU_SET_FIELD(instr->alu.mul.waddr, V3D_QPU_WADDR_M);  in v3d_qpu_mul_pack()
1262                 *packed_instr |= VC5_QPU_MM;  in v3d_qpu_mul_pack()
1269                          uint64_t packed_instr,  in v3d_qpu_instr_unpack_alu()  argument
1275                                 QPU_GET_FIELD(packed_instr, VC5_QPU_SIG),  in v3d_qpu_instr_unpack_alu()
1279         uint32_t packed_cond = QPU_GET_FIELD(packed_instr, VC5_QPU_COND);  in v3d_qpu_instr_unpack_alu()
1295         instr->raddr_a = QPU_GET_FIELD(packed_instr, VC5_QPU_RADDR_A);  in v3d_qpu_instr_unpack_alu()
1296         instr->raddr_b = QPU_GET_FIELD(packed_instr, VC5_QPU_RADDR_B);  in v3d_qpu_instr_unpack_alu()
1298         if (!v3d_qpu_add_unpack(devinfo, packed_instr, instr))  in v3d_qpu_instr_unpack_alu()
1301         if (!v3d_qpu_mul_unpack(devinfo, packed_instr, instr))  in v3d_qpu_instr_unpack_alu()
1309                             uint64_t packed_instr,  in v3d_qpu_instr_unpack_branch()  argument
1314         uint32_t cond = QPU_GET_FIELD(packed_instr, VC5_QPU_BRANCH_COND);  in v3d_qpu_instr_unpack_branch()
1323         uint32_t msfign = QPU_GET_FIELD(packed_instr, VC5_QPU_BRANCH_MSFIGN);  in v3d_qpu_instr_unpack_branch()
1328         instr->branch.bdi = QPU_GET_FIELD(packed_instr, VC5_QPU_BRANCH_BDI);  in v3d_qpu_instr_unpack_branch()
1330         instr->branch.ub = packed_instr & VC5_QPU_BRANCH_UB;  in v3d_qpu_instr_unpack_branch()
1332                 instr->branch.bdu = QPU_GET_FIELD(packed_instr,  in v3d_qpu_instr_unpack_branch()
1336         instr->branch.raddr_a = QPU_GET_FIELD(packed_instr,  in v3d_qpu_instr_unpack_branch()
1342                 QPU_GET_FIELD(packed_instr,  in v3d_qpu_instr_unpack_branch()
1346                 QPU_GET_FIELD(packed_instr,  in v3d_qpu_instr_unpack_branch()
1354                      uint64_t packed_instr,  in v3d_qpu_instr_unpack()  argument
1357         if (QPU_GET_FIELD(packed_instr, VC5_QPU_OP_MUL) != 0) {  in v3d_qpu_instr_unpack()
1358                 return v3d_qpu_instr_unpack_alu(devinfo, packed_instr, instr);  in v3d_qpu_instr_unpack()
1360                 uint32_t sig = QPU_GET_FIELD(packed_instr, VC5_QPU_SIG);  in v3d_qpu_instr_unpack()
1363                         return v3d_qpu_instr_unpack_branch(devinfo, packed_instr,  in v3d_qpu_instr_unpack()
1374                        uint64_t *packed_instr)  in v3d_qpu_instr_pack_alu()  argument
1379         *packed_instr |= QPU_SET_FIELD(sig, VC5_QPU_SIG);  in v3d_qpu_instr_pack_alu()
1382                 *packed_instr |= QPU_SET_FIELD(instr->raddr_a, VC5_QPU_RADDR_A);  in v3d_qpu_instr_pack_alu()
1383                 *packed_instr |= QPU_SET_FIELD(instr->raddr_b, VC5_QPU_RADDR_B);  in v3d_qpu_instr_pack_alu()
1385                 if (!v3d_qpu_add_pack(devinfo, instr, packed_instr))  in v3d_qpu_instr_pack_alu()
1387                 if (!v3d_qpu_mul_pack(devinfo, instr, packed_instr))  in v3d_qpu_instr_pack_alu()
1409                 *packed_instr |= QPU_SET_FIELD(flags, VC5_QPU_COND);  in v3d_qpu_instr_pack_alu()
1421                           uint64_t *packed_instr)  in v3d_qpu_instr_pack_branch()  argument
1423         *packed_instr |= QPU_SET_FIELD(16, VC5_QPU_SIG);  in v3d_qpu_instr_pack_branch()
1426                 *packed_instr |= QPU_SET_FIELD(2 + (instr->branch.cond -  in v3d_qpu_instr_pack_branch()
1431         *packed_instr |= QPU_SET_FIELD(instr->branch.msfign,  in v3d_qpu_instr_pack_branch()
1434         *packed_instr |= QPU_SET_FIELD(instr->branch.bdi,  in v3d_qpu_instr_pack_branch()
1438                 *packed_instr |= VC5_QPU_BRANCH_UB;  in v3d_qpu_instr_pack_branch()
1439                 *packed_instr |= QPU_SET_FIELD(instr->branch.bdu,  in v3d_qpu_instr_pack_branch()
1446                 *packed_instr |= QPU_SET_FIELD(instr->branch.msfign,  in v3d_qpu_instr_pack_branch()
1449                 *packed_instr |= QPU_SET_FIELD((instr->branch.offset &  in v3d_qpu_instr_pack_branch()
1453                 *packed_instr |= QPU_SET_FIELD(instr->branch.offset >> 24,  in v3d_qpu_instr_pack_branch()
1461                 *packed_instr |= QPU_SET_FIELD(instr->branch.raddr_a,  in v3d_qpu_instr_pack_branch()
1471                    uint64_t *packed_instr)  in v3d_qpu_instr_pack()  argument
1473         *packed_instr = 0;  in v3d_qpu_instr_pack()
1477                 return v3d_qpu_instr_pack_alu(devinfo, instr, packed_instr);  in v3d_qpu_instr_pack()
1479                 return v3d_qpu_instr_pack_branch(devinfo, instr, packed_instr);  in v3d_qpu_instr_pack()