146    struct ureg_src vpos;  in create_mismatch_vert_shader()  local
155    vpos = ureg_DECL_vs_input(shader, VS_I_VPOS);  in create_mismatch_vert_shader()
178    ureg_MAD(shader, ureg_writemask(o_vpos, TGSI_WRITEMASK_XY), vpos, scale, scale);  in create_mismatch_vert_shader()
181    ureg_MUL(shader, ureg_writemask(t_tex, TGSI_WRITEMASK_XY), vpos, scale);  in create_mismatch_vert_shader()
262    struct ureg_src vrect, vpos;  in create_stage1_vert_shader()  local
272    vpos = ureg_DECL_vs_input(shader, VS_I_VPOS);  in create_stage1_vert_shader()
301    ureg_ADD(shader, ureg_writemask(t_tex, TGSI_WRITEMASK_XY), vpos, vrect);  in create_stage1_vert_shader()
307    ureg_MUL(shader, ureg_writemask(t_start, TGSI_WRITEMASK_XY), vpos, scale);  in create_stage1_vert_shader()
396    struct ureg_src vrect, vpos;  in vl_idct_stage2_vert_shader()  local
402    vpos = ureg_DECL_vs_input(shader, VS_I_VPOS);  in vl_idct_stage2_vert_shader()
421    ureg_MUL(shader, ureg_writemask(t_start, TGSI_WRITEMASK_XY), vpos, scale);  in vl_idct_stage2_vert_shader()