Lines Matching refs:rctx
127 struct r600_context *rctx = NULL; in evergreen_set_rat() local
133 rctx = pipe->ctx; in evergreen_set_rat()
135 COMPUTE_DBG(rctx->screen, "bind rat: %i \n", id); in evergreen_set_rat()
161 evergreen_init_color_surface_rat(rctx, surf); in evergreen_set_rat()
164 static void evergreen_cs_set_vertex_buffer(struct r600_context *rctx, in evergreen_cs_set_vertex_buffer() argument
169 struct r600_vertexbuf_state *state = &rctx->cs_vertex_buffer_state; in evergreen_cs_set_vertex_buffer()
178 rctx->b.flags |= R600_CONTEXT_INV_VERTEX_CACHE; in evergreen_cs_set_vertex_buffer()
181 r600_mark_atom_dirty(rctx, &state->atom); in evergreen_cs_set_vertex_buffer()
184 static void evergreen_cs_set_constant_buffer(struct r600_context *rctx, in evergreen_cs_set_constant_buffer() argument
196 rctx->b.b.set_constant_buffer(&rctx->b.b, PIPE_SHADER_COMPUTE, cb_index, &cb); in evergreen_cs_set_constant_buffer()
429 struct r600_context *rctx = (struct r600_context *)ctx; in evergreen_create_compute_state() local
437 shader->ctx = rctx; in evergreen_create_compute_state()
450 COMPUTE_DBG(rctx->screen, "*** evergreen_create_compute_state\n"); in evergreen_create_compute_state()
457 shader->code_bo = r600_compute_buffer_alloc_vram(rctx->screen, in evergreen_create_compute_state()
460 &rctx->b, shader->code_bo, in evergreen_create_compute_state()
464 rctx->b.ws->buffer_unmap(shader->code_bo->buf); in evergreen_create_compute_state()
472 struct r600_context *rctx = (struct r600_context *)ctx; in evergreen_delete_compute_state() local
475 COMPUTE_DBG(rctx->screen, "*** evergreen_delete_compute_state\n"); in evergreen_delete_compute_state()
496 struct r600_context *rctx = (struct r600_context *)ctx; in evergreen_bind_compute_state() local
498 COMPUTE_DBG(rctx->screen, "*** evergreen_bind_compute_state\n"); in evergreen_bind_compute_state()
501 rctx->cs_shader_state.shader = (struct r600_pipe_compute *)state; in evergreen_bind_compute_state()
513 rctx->cs_shader_state.shader = (struct r600_pipe_compute *)state; in evergreen_bind_compute_state()
530 struct r600_context *rctx = (struct r600_context *)ctx; in evergreen_compute_upload_input() local
531 struct r600_pipe_compute *shader = rctx->cs_shader_state.shader; in evergreen_compute_upload_input()
581 COMPUTE_DBG(rctx->screen, "input %i : %u\n", i, in evergreen_compute_upload_input()
590 evergreen_cs_set_vertex_buffer(rctx, 3, 0, in evergreen_compute_upload_input()
592 evergreen_cs_set_constant_buffer(rctx, 0, 0, input_size, in evergreen_compute_upload_input()
596 static void evergreen_emit_dispatch(struct r600_context *rctx, in evergreen_emit_dispatch() argument
601 struct radeon_cmdbuf *cs = rctx->b.gfx.cs; in evergreen_emit_dispatch()
602 struct r600_pipe_compute *shader = rctx->cs_shader_state.shader; in evergreen_emit_dispatch()
603 bool render_cond_bit = rctx->b.render_cond && !rctx->b.render_cond_force_off; in evergreen_emit_dispatch()
605 unsigned num_pipes = rctx->screen->b.info.r600_max_quad_pipes; in evergreen_emit_dispatch()
628 COMPUTE_DBG(rctx->screen, "Using %u pipes, " in evergreen_emit_dispatch()
648 if (rctx->b.chip_class < CAYMAN) { in evergreen_emit_dispatch()
675 if (rctx->is_debug) in evergreen_emit_dispatch()
676 eg_trace_emit(rctx); in evergreen_emit_dispatch()
679 static void compute_setup_cbs(struct r600_context *rctx) in compute_setup_cbs() argument
681 struct radeon_cmdbuf *cs = rctx->b.gfx.cs; in compute_setup_cbs()
686 for (i = 0; i < 8 && i < rctx->framebuffer.state.nr_cbufs; i++) { in compute_setup_cbs()
687 struct r600_surface *cb = (struct r600_surface*)rctx->framebuffer.state.cbufs[i]; in compute_setup_cbs()
688 unsigned reloc = radeon_add_to_buffer_list(&rctx->b, &rctx->b.gfx, in compute_setup_cbs()
717 rctx->compute_cb_target_mask); in compute_setup_cbs()
720 static void compute_emit_cs(struct r600_context *rctx, in compute_emit_cs() argument
723 struct radeon_cmdbuf *cs = rctx->b.gfx.cs; in compute_emit_cs()
731 if (radeon_emitted(rctx->b.dma.cs, 0)) { in compute_emit_cs()
732 rctx->b.dma.flush(rctx, PIPE_FLUSH_ASYNC, NULL); in compute_emit_cs()
735 r600_update_compressed_resource_state(rctx, true); in compute_emit_cs()
737 if (!rctx->cmd_buf_is_compute) { in compute_emit_cs()
738 rctx->b.gfx.flush(rctx, PIPE_FLUSH_ASYNC, NULL); in compute_emit_cs()
739 rctx->cmd_buf_is_compute = true; in compute_emit_cs()
742 if (rctx->cs_shader_state.shader->ir_type == PIPE_SHADER_IR_TGSI|| in compute_emit_cs()
743 rctx->cs_shader_state.shader->ir_type == PIPE_SHADER_IR_NIR) { in compute_emit_cs()
744 if (r600_shader_select(&rctx->b.b, rctx->cs_shader_state.shader->sel, &compute_dirty)) { in compute_emit_cs()
749 current = rctx->cs_shader_state.shader->sel->current; in compute_emit_cs()
751 rctx->cs_shader_state.atom.num_dw = current->command_buffer.num_dw; in compute_emit_cs()
752 r600_context_add_resource_size(&rctx->b.b, (struct pipe_resource *)current->bo); in compute_emit_cs()
753 r600_set_atom_dirty(rctx, &rctx->cs_shader_state.atom, true); in compute_emit_cs()
761 unsigned *data = r600_buffer_map_sync_with_rings(&rctx->b, indirect_resource, PIPE_MAP_READ); in compute_emit_cs()
768 rctx->cs_block_grid_sizes[i] = info->block[i]; in compute_emit_cs()
769 rctx->cs_block_grid_sizes[i + 4] = info->indirect ? indirect_grid[i] : info->grid[i]; in compute_emit_cs()
771 rctx->cs_block_grid_sizes[3] = rctx->cs_block_grid_sizes[7] = 0; in compute_emit_cs()
772 rctx->driver_consts[PIPE_SHADER_COMPUTE].cs_block_grid_size_dirty = true; in compute_emit_cs()
774 evergreen_emit_atomic_buffer_setup_count(rctx, current, combined_atomics, &atomic_used_mask); in compute_emit_cs()
775 r600_need_cs_space(rctx, 0, true, util_bitcount(atomic_used_mask)); in compute_emit_cs()
778 eg_setup_buffer_constants(rctx, PIPE_SHADER_COMPUTE); in compute_emit_cs()
780 r600_update_driver_const_buffers(rctx, true); in compute_emit_cs()
782 evergreen_emit_atomic_buffer_setup(rctx, true, combined_atomics, atomic_used_mask); in compute_emit_cs()
788 r600_need_cs_space(rctx, 0, true, 0); in compute_emit_cs()
795 r600_emit_command_buffer(cs, &rctx->start_compute_cs_cmd); in compute_emit_cs()
798 if (rctx->b.chip_class == EVERGREEN) { in compute_emit_cs()
799 if (rctx->cs_shader_state.shader->ir_type == PIPE_SHADER_IR_TGSI|| in compute_emit_cs()
800 rctx->cs_shader_state.shader->ir_type == PIPE_SHADER_IR_NIR) { in compute_emit_cs()
802 radeon_emit(cs, S_008C04_NUM_CLAUSE_TEMP_GPRS(rctx->r6xx_num_clause_temp_gprs)); in compute_emit_cs()
807 r600_emit_atom(rctx, &rctx->config_state.atom); in compute_emit_cs()
810 rctx->b.flags |= R600_CONTEXT_WAIT_3D_IDLE | R600_CONTEXT_FLUSH_AND_INV; in compute_emit_cs()
811 r600_flush_emit(rctx); in compute_emit_cs()
813 if (rctx->cs_shader_state.shader->ir_type != PIPE_SHADER_IR_TGSI && in compute_emit_cs()
814 rctx->cs_shader_state.shader->ir_type != PIPE_SHADER_IR_NIR) { in compute_emit_cs()
816 compute_setup_cbs(rctx); in compute_emit_cs()
819 …rctx->cs_vertex_buffer_state.atom.num_dw = 12 * util_bitcount(rctx->cs_vertex_buffer_state.dirty_m… in compute_emit_cs()
820 r600_emit_atom(rctx, &rctx->cs_vertex_buffer_state.atom); in compute_emit_cs()
824 rat_mask = evergreen_construct_rat_mask(rctx, &rctx->cb_misc_state, 0); in compute_emit_cs()
829 r600_emit_atom(rctx, &rctx->b.render_cond_atom); in compute_emit_cs()
832 r600_emit_atom(rctx, &rctx->constbuf_state[PIPE_SHADER_COMPUTE].atom); in compute_emit_cs()
835 r600_emit_atom(rctx, &rctx->samplers[PIPE_SHADER_COMPUTE].states.atom); in compute_emit_cs()
838 r600_emit_atom(rctx, &rctx->samplers[PIPE_SHADER_COMPUTE].views.atom); in compute_emit_cs()
841 r600_emit_atom(rctx, &rctx->compute_images.atom); in compute_emit_cs()
844 r600_emit_atom(rctx, &rctx->compute_buffers.atom); in compute_emit_cs()
847 r600_emit_atom(rctx, &rctx->cs_shader_state.atom); in compute_emit_cs()
850 evergreen_emit_dispatch(rctx, info, indirect_grid); in compute_emit_cs()
854 rctx->b.flags |= R600_CONTEXT_INV_CONST_CACHE | in compute_emit_cs()
857 r600_flush_emit(rctx); in compute_emit_cs()
858 rctx->b.flags = 0; in compute_emit_cs()
860 if (rctx->b.chip_class >= CAYMAN) { in compute_emit_cs()
870 if (rctx->cs_shader_state.shader->ir_type == PIPE_SHADER_IR_TGSI || in compute_emit_cs()
871 rctx->cs_shader_state.shader->ir_type == PIPE_SHADER_IR_NIR) in compute_emit_cs()
872 evergreen_emit_atomic_buffer_save(rctx, true, combined_atomics, &atomic_used_mask); in compute_emit_cs()
875 COMPUTE_DBG(rctx->screen, "cdw: %i\n", cs->cdw); in compute_emit_cs()
877 COMPUTE_DBG(rctx->screen, "%4i : 0x%08X\n", i, cs->buf[i]); in compute_emit_cs()
887 void evergreen_emit_cs_shader(struct r600_context *rctx, in evergreen_emit_cs_shader() argument
893 struct radeon_cmdbuf *cs = rctx->b.gfx.cs; in evergreen_emit_cs_shader()
920 radeon_emit(cs, radeon_add_to_buffer_list(&rctx->b, &rctx->b.gfx, in evergreen_emit_cs_shader()
928 struct r600_context *rctx = (struct r600_context *)ctx; in evergreen_launch_grid() local
930 struct r600_pipe_compute *shader = rctx->cs_shader_state.shader; in evergreen_launch_grid()
935 rctx->cs_shader_state.pc = info->pc; in evergreen_launch_grid()
941 rctx->cs_shader_state.pc = 0; in evergreen_launch_grid()
945 COMPUTE_DBG(rctx->screen, "*** evergreen_launch_grid: pc = %u\n", info->pc); in evergreen_launch_grid()
949 compute_emit_cs(rctx, info); in evergreen_launch_grid()
956 struct r600_context *rctx = (struct r600_context *)ctx; in evergreen_set_compute_resources() local
959 COMPUTE_DBG(rctx->screen, "*** evergreen_set_compute_resources: start = %u count = %u\n", in evergreen_set_compute_resources()
973 evergreen_set_rat(rctx->cs_shader_state.shader, i+1, in evergreen_set_compute_resources()
979 evergreen_cs_set_vertex_buffer(rctx, vtx_id, in evergreen_set_compute_resources()
991 struct r600_context *rctx = (struct r600_context *)ctx; in evergreen_set_global_binding() local
992 struct compute_memory_pool *pool = rctx->screen->global_pool; in evergreen_set_global_binding()
997 COMPUTE_DBG(rctx->screen, "*** evergreen_set_global_binding first = %u n = %u\n", in evergreen_set_global_binding()
1033 evergreen_set_rat(rctx->cs_shader_state.shader, 0, pool->bo, 0, pool->size_in_dw * 4); in evergreen_set_global_binding()
1035 evergreen_cs_set_vertex_buffer(rctx, 1, 0, in evergreen_set_global_binding()
1039 evergreen_cs_set_vertex_buffer(rctx, 2, 0, in evergreen_set_global_binding()
1040 (struct pipe_resource*)rctx->cs_shader_state.shader->code_bo); in evergreen_set_global_binding()
1054 void evergreen_init_atom_start_compute_cs(struct r600_context *rctx) in evergreen_init_atom_start_compute_cs() argument
1056 struct r600_command_buffer *cb = &rctx->start_compute_cs_cmd; in evergreen_init_atom_start_compute_cs()
1070 switch (rctx->b.family) { in evergreen_init_atom_start_compute_cs()
1119 if (rctx->b.chip_class < CAYMAN) { in evergreen_init_atom_start_compute_cs()
1169 if (rctx->b.chip_class < CAYMAN) { in evergreen_init_atom_start_compute_cs()
1180 if (rctx->b.chip_class < CAYMAN) { in evergreen_init_atom_start_compute_cs()
1221 void evergreen_init_compute_state_functions(struct r600_context *rctx) in evergreen_init_compute_state_functions() argument
1223 rctx->b.b.create_compute_state = evergreen_create_compute_state; in evergreen_init_compute_state_functions()
1224 rctx->b.b.delete_compute_state = evergreen_delete_compute_state; in evergreen_init_compute_state_functions()
1225 rctx->b.b.bind_compute_state = evergreen_bind_compute_state; in evergreen_init_compute_state_functions()
1227 rctx->b.b.set_compute_resources = evergreen_set_compute_resources; in evergreen_init_compute_state_functions()
1228 rctx->b.b.set_global_binding = evergreen_set_global_binding; in evergreen_init_compute_state_functions()
1229 rctx->b.b.launch_grid = evergreen_launch_grid; in evergreen_init_compute_state_functions()
1240 struct r600_context *rctx = (struct r600_context*)ctx; in r600_compute_global_transfer_map() local
1241 struct compute_memory_pool *pool = rctx->screen->global_pool; in r600_compute_global_transfer_map()
1264 COMPUTE_DBG(rctx->screen, "* r600_compute_global_transfer_map()\n" in r600_compute_global_transfer_map()
1269 COMPUTE_DBG(rctx->screen, "Buffer id = %"PRIi64" offset = " in r600_compute_global_transfer_map()