Lines Matching refs:tex
37 static void si_alloc_separate_cmask(struct si_screen *sscreen, struct si_texture *tex) in si_alloc_separate_cmask() argument
42 if (tex->cmask_buffer || !tex->surface.cmask_size || tex->buffer.b.b.nr_samples >= 2) in si_alloc_separate_cmask()
45 tex->cmask_buffer = in si_alloc_separate_cmask()
47 tex->surface.cmask_size, tex->surface.cmask_alignment); in si_alloc_separate_cmask()
48 if (tex->cmask_buffer == NULL) in si_alloc_separate_cmask()
51 tex->cmask_base_address_reg = tex->cmask_buffer->gpu_address >> 8; in si_alloc_separate_cmask()
52 tex->cb_color_info |= S_028C70_FAST_CLEAR(1); in si_alloc_separate_cmask()
57 static bool si_set_clear_color(struct si_texture *tex, enum pipe_format surface_format, in si_set_clear_color() argument
64 if (tex->surface.bpe == 16) { in si_set_clear_color()
76 if (memcmp(tex->color_clear_value, &uc, 2 * sizeof(uint32_t)) == 0) in si_set_clear_color()
79 memcpy(tex->color_clear_value, &uc, 2 * sizeof(uint32_t)); in si_set_clear_color()
216 bool vi_dcc_clear_level(struct si_context *sctx, struct si_texture *tex, unsigned level, in vi_dcc_clear_level() argument
222 assert(vi_dcc_enabled(tex, level)); in vi_dcc_clear_level()
224 if (tex->dcc_separate_buffer) { in vi_dcc_clear_level()
225 dcc_buffer = &tex->dcc_separate_buffer->b.b; in vi_dcc_clear_level()
228 dcc_buffer = &tex->buffer.b.b; in vi_dcc_clear_level()
229 dcc_offset = tex->surface.dcc_offset; in vi_dcc_clear_level()
234 if (tex->buffer.b.b.last_level > 0) in vi_dcc_clear_level()
239 if (tex->buffer.b.b.nr_storage_samples >= 4) in vi_dcc_clear_level()
242 clear_size = tex->surface.dcc_size; in vi_dcc_clear_level()
244 unsigned num_layers = util_num_layers(&tex->buffer.b.b, level); in vi_dcc_clear_level()
247 if (!tex->surface.u.legacy.level[level].dcc_fast_clear_size) in vi_dcc_clear_level()
254 if (tex->buffer.b.b.nr_storage_samples >= 4 && num_layers > 1) in vi_dcc_clear_level()
257 dcc_offset += tex->surface.u.legacy.level[level].dcc_offset; in vi_dcc_clear_level()
258 clear_size = tex->surface.u.legacy.level[level].dcc_fast_clear_size * num_layers; in vi_dcc_clear_level()
270 static void si_set_optimal_micro_tile_mode(struct si_screen *sscreen, struct si_texture *tex) in si_set_optimal_micro_tile_mode() argument
272 if (sscreen->info.chip_class >= GFX10 || tex->buffer.b.is_shared || in si_set_optimal_micro_tile_mode()
273 tex->buffer.b.b.nr_samples <= 1 || in si_set_optimal_micro_tile_mode()
274 tex->surface.micro_tile_mode == tex->last_msaa_resolve_target_micro_mode) in si_set_optimal_micro_tile_mode()
278 tex->surface.u.legacy.level[0].mode == RADEON_SURF_MODE_2D); in si_set_optimal_micro_tile_mode()
279 assert(tex->buffer.b.b.last_level == 0); in si_set_optimal_micro_tile_mode()
283 assert(tex->surface.u.gfx9.surf.swizzle_mode >= 4); in si_set_optimal_micro_tile_mode()
293 assert(tex->surface.u.gfx9.surf.swizzle_mode % 4 != 0); in si_set_optimal_micro_tile_mode()
295 switch (tex->last_msaa_resolve_target_micro_mode) { in si_set_optimal_micro_tile_mode()
297 tex->surface.u.gfx9.surf.swizzle_mode &= ~0x3; in si_set_optimal_micro_tile_mode()
298 tex->surface.u.gfx9.surf.swizzle_mode += 2; /* D */ in si_set_optimal_micro_tile_mode()
301 tex->surface.u.gfx9.surf.swizzle_mode &= ~0x3; in si_set_optimal_micro_tile_mode()
302 tex->surface.u.gfx9.surf.swizzle_mode += 1; /* S */ in si_set_optimal_micro_tile_mode()
305 tex->surface.u.gfx9.surf.swizzle_mode &= ~0x3; in si_set_optimal_micro_tile_mode()
306 tex->surface.u.gfx9.surf.swizzle_mode += 3; /* R */ in si_set_optimal_micro_tile_mode()
317 switch (tex->last_msaa_resolve_target_micro_mode) { in si_set_optimal_micro_tile_mode()
319 tex->surface.u.legacy.tiling_index[0] = 10; in si_set_optimal_micro_tile_mode()
322 tex->surface.u.legacy.tiling_index[0] = 14; in si_set_optimal_micro_tile_mode()
325 tex->surface.u.legacy.tiling_index[0] = 28; in si_set_optimal_micro_tile_mode()
332 switch (tex->last_msaa_resolve_target_micro_mode) { in si_set_optimal_micro_tile_mode()
334 switch (tex->surface.bpe) { in si_set_optimal_micro_tile_mode()
336 tex->surface.u.legacy.tiling_index[0] = 10; in si_set_optimal_micro_tile_mode()
339 tex->surface.u.legacy.tiling_index[0] = 11; in si_set_optimal_micro_tile_mode()
342 tex->surface.u.legacy.tiling_index[0] = 12; in si_set_optimal_micro_tile_mode()
347 switch (tex->surface.bpe) { in si_set_optimal_micro_tile_mode()
349 tex->surface.u.legacy.tiling_index[0] = 14; in si_set_optimal_micro_tile_mode()
352 tex->surface.u.legacy.tiling_index[0] = 15; in si_set_optimal_micro_tile_mode()
355 tex->surface.u.legacy.tiling_index[0] = 16; in si_set_optimal_micro_tile_mode()
358 tex->surface.u.legacy.tiling_index[0] = 17; in si_set_optimal_micro_tile_mode()
368 tex->surface.micro_tile_mode = tex->last_msaa_resolve_target_micro_mode; in si_set_optimal_micro_tile_mode()
388 struct si_texture *tex; in si_do_fast_color_clear() local
398 unsigned level = fb->cbufs[i]->u.tex.level; in si_do_fast_color_clear()
402 tex = (struct si_texture *)fb->cbufs[i]->texture; in si_do_fast_color_clear()
409 if (sctx->chip_class >= GFX9 && tex->buffer.b.b.last_level > 0) in si_do_fast_color_clear()
413 if (fb->cbufs[i]->u.tex.first_layer != 0 || in si_do_fast_color_clear()
414 fb->cbufs[i]->u.tex.last_layer != util_max_layer(&tex->buffer.b.b, 0)) { in si_do_fast_color_clear()
419 if (tex->surface.is_linear) { in si_do_fast_color_clear()
427 if (tex->buffer.b.is_shared && in si_do_fast_color_clear()
428 !(tex->buffer.external_usage & PIPE_HANDLE_USAGE_EXPLICIT_FLUSH)) in si_do_fast_color_clear()
431 if (sctx->chip_class <= GFX8 && tex->surface.u.legacy.level[0].mode == RADEON_SURF_MODE_1D && in si_do_fast_color_clear()
441 bool too_small = tex->buffer.b.b.nr_samples <= 1 && in si_do_fast_color_clear()
442 tex->buffer.b.b.width0 * tex->buffer.b.b.height0 <= 512 * 512; in si_do_fast_color_clear()
450 vi_separate_dcc_try_enable(sctx, tex); in si_do_fast_color_clear()
457 if (tex->dcc_gather_statistics) /* only for Stoney */ in si_do_fast_color_clear()
458 tex->num_slow_clears++; in si_do_fast_color_clear()
462 if (vi_dcc_enabled(tex, 0)) { in si_do_fast_color_clear()
468 if (!vi_get_fast_clear_parameters(sctx->screen, tex->buffer.b.b.format, in si_do_fast_color_clear()
477 if (tex->buffer.b.b.nr_samples >= 2 && tex->cmask_buffer && eliminate_needed) in si_do_fast_color_clear()
480 if (!vi_dcc_clear_level(sctx, tex, 0, reset_value)) in si_do_fast_color_clear()
483 tex->separate_dcc_dirty = true; in si_do_fast_color_clear()
484 tex->displayable_dcc_dirty = true; in si_do_fast_color_clear()
487 if (tex->buffer.b.b.nr_samples >= 2 && tex->cmask_buffer) { in si_do_fast_color_clear()
489 si_clear_buffer(sctx, &tex->cmask_buffer->b.b, tex->surface.cmask_offset, in si_do_fast_color_clear()
490 tex->surface.cmask_size, &clear_value, 4, SI_COHERENCY_CB_META, false); in si_do_fast_color_clear()
498 if (tex->surface.bpe > 8) { in si_do_fast_color_clear()
507 if (tex->buffer.flags & RADEON_FLAG_ENCRYPTED) in si_do_fast_color_clear()
511 si_alloc_separate_cmask(sctx->screen, tex); in si_do_fast_color_clear()
512 if (!tex->cmask_buffer) in si_do_fast_color_clear()
517 si_clear_buffer(sctx, &tex->cmask_buffer->b.b, tex->surface.cmask_offset, in si_do_fast_color_clear()
518 tex->surface.cmask_size, &clear_value, 4, SI_COHERENCY_CB_META, false); in si_do_fast_color_clear()
523 !(tex->dirty_level_mask & (1 << level))) { in si_do_fast_color_clear()
524 tex->dirty_level_mask |= 1 << level; in si_do_fast_color_clear()
529 si_set_optimal_micro_tile_mode(sctx->screen, tex); in si_do_fast_color_clear()
539 if (si_set_clear_color(tex, fb->cbufs[i]->format, color)) { in si_do_fast_color_clear()
563 struct si_texture *tex; in si_clear() local
569 tex = (struct si_texture *)fb->cbufs[i]->texture; in si_clear()
570 if (tex->surface.fmask_size == 0) in si_clear()
571 tex->dirty_level_mask &= ~(1 << fb->cbufs[i]->u.tex.level); in si_clear()
575 if (zstex && zsbuf->u.tex.first_layer == 0 && in si_clear()
576 zsbuf->u.tex.last_layer == util_max_layer(&zstex->buffer.b.b, 0)) { in si_clear()
580 si_htile_enabled(zstex, zsbuf->u.tex.level, PIPE_MASK_ZS) && in si_clear()
615 if (buffers & PIPE_CLEAR_DEPTH && si_htile_enabled(zstex, zsbuf->u.tex.level, PIPE_MASK_Z) && in si_clear()
640 si_htile_enabled(zstex, zsbuf->u.tex.level, PIPE_MASK_S) && in si_clear()
692 if (dst->texture->nr_samples <= 1 && !vi_dcc_enabled(sdst, dst->u.tex.level)) { in si_clear_render_target()
718 static void si_clear_texture(struct pipe_context *pipe, struct pipe_resource *tex, unsigned level, in si_clear_texture() argument
722 struct si_texture *stex = (struct si_texture *)tex; in si_clear_texture()
726 tmpl.format = tex->format; in si_clear_texture()
727 tmpl.u.tex.first_layer = box->z; in si_clear_texture()
728 tmpl.u.tex.last_layer = box->z + box->depth - 1; in si_clear_texture()
729 tmpl.u.tex.level = level; in si_clear_texture()
730 sf = pipe->create_surface(pipe, tex, &tmpl); in si_clear_texture()
741 util_format_unpack_z_float(tex->format, &depth, data, 1); in si_clear_texture()
745 util_format_unpack_s_8uint(tex->format, &stencil, data, 1); in si_clear_texture()
753 util_format_unpack_rgba(tex->format, color.ui, data, 1); in si_clear_texture()
755 if (screen->is_format_supported(screen, tex->format, tex->target, 0, 0, in si_clear_texture()