Lines Matching refs:sctx
38 static void si_dump_bo_list(struct si_context *sctx, const struct radeon_saved_cs *saved, FILE *f);
294 static void si_dump_mmapped_reg(struct si_context *sctx, FILE *f, unsigned offset) in si_dump_mmapped_reg() argument
296 struct radeon_winsys *ws = sctx->ws; in si_dump_mmapped_reg()
300 ac_dump_reg(f, sctx->chip_class, offset, value, ~0); in si_dump_mmapped_reg()
303 static void si_dump_debug_registers(struct si_context *sctx, FILE *f) in si_dump_debug_registers() argument
305 if (!sctx->screen->info.has_read_registers_query) in si_dump_debug_registers()
309 si_dump_mmapped_reg(sctx, f, R_008010_GRBM_STATUS); in si_dump_debug_registers()
312 if (!sctx->screen->info.is_amdgpu || sctx->screen->info.drm_minor < 1) { in si_dump_debug_registers()
317 si_dump_mmapped_reg(sctx, f, R_008008_GRBM_STATUS2); in si_dump_debug_registers()
318 si_dump_mmapped_reg(sctx, f, R_008014_GRBM_STATUS_SE0); in si_dump_debug_registers()
319 si_dump_mmapped_reg(sctx, f, R_008018_GRBM_STATUS_SE1); in si_dump_debug_registers()
320 si_dump_mmapped_reg(sctx, f, R_008038_GRBM_STATUS_SE2); in si_dump_debug_registers()
321 si_dump_mmapped_reg(sctx, f, R_00803C_GRBM_STATUS_SE3); in si_dump_debug_registers()
322 si_dump_mmapped_reg(sctx, f, R_00D034_SDMA0_STATUS_REG); in si_dump_debug_registers()
323 si_dump_mmapped_reg(sctx, f, R_00D834_SDMA1_STATUS_REG); in si_dump_debug_registers()
324 if (sctx->chip_class <= GFX8) { in si_dump_debug_registers()
325 si_dump_mmapped_reg(sctx, f, R_000E50_SRBM_STATUS); in si_dump_debug_registers()
326 si_dump_mmapped_reg(sctx, f, R_000E4C_SRBM_STATUS2); in si_dump_debug_registers()
327 si_dump_mmapped_reg(sctx, f, R_000E54_SRBM_STATUS3); in si_dump_debug_registers()
329 si_dump_mmapped_reg(sctx, f, R_008680_CP_STAT); in si_dump_debug_registers()
330 si_dump_mmapped_reg(sctx, f, R_008674_CP_STALLED_STAT1); in si_dump_debug_registers()
331 si_dump_mmapped_reg(sctx, f, R_008678_CP_STALLED_STAT2); in si_dump_debug_registers()
332 si_dump_mmapped_reg(sctx, f, R_008670_CP_STALLED_STAT3); in si_dump_debug_registers()
333 si_dump_mmapped_reg(sctx, f, R_008210_CP_CPC_STATUS); in si_dump_debug_registers()
334 si_dump_mmapped_reg(sctx, f, R_008214_CP_CPC_BUSY_STAT); in si_dump_debug_registers()
335 si_dump_mmapped_reg(sctx, f, R_008218_CP_CPC_STALLED_STAT1); in si_dump_debug_registers()
336 si_dump_mmapped_reg(sctx, f, R_00821C_CP_CPF_STATUS); in si_dump_debug_registers()
337 si_dump_mmapped_reg(sctx, f, R_008220_CP_CPF_BUSY_STAT); in si_dump_debug_registers()
338 si_dump_mmapped_reg(sctx, f, R_008224_CP_CPF_STALLED_STAT1); in si_dump_debug_registers()
497 void si_log_hw_flush(struct si_context *sctx) in si_log_hw_flush() argument
499 if (!sctx->log) in si_log_hw_flush()
502 si_log_cs(sctx, sctx->log, true); in si_log_hw_flush()
504 if (&sctx->b == sctx->screen->aux_context) { in si_log_hw_flush()
512 dd_write_header(f, &sctx->screen->b, 0); in si_log_hw_flush()
515 u_log_new_page_print(sctx->log, f); in si_log_hw_flush()
566 static void si_dump_bo_list(struct si_context *sctx, const struct radeon_saved_cs *saved, FILE *f) in si_dump_bo_list() argument
582 const unsigned page_size = sctx->screen->info.gart_page_size; in si_dump_bo_list()
615 static void si_dump_framebuffer(struct si_context *sctx, struct u_log_context *log) in si_dump_framebuffer() argument
617 struct pipe_framebuffer_state *state = &sctx->framebuffer.state; in si_dump_framebuffer()
627 si_print_texture_info(sctx->screen, tex, log); in si_dump_framebuffer()
634 si_print_texture_info(sctx->screen, tex, log); in si_dump_framebuffer()
780 static void si_dump_descriptors(struct si_context *sctx, gl_shader_stage stage, in si_dump_descriptors() argument
785 &sctx->descriptors[SI_DESCS_FIRST_SHADER + processor * SI_NUM_SHADER_DESCS]; in si_dump_descriptors()
798 sctx->const_and_shader_buffers[processor].enabled_mask >> SI_NUM_SHADER_BUFFERS; in si_dump_descriptors()
799 enabled_shaderbuf = sctx->const_and_shader_buffers[processor].enabled_mask & in si_dump_descriptors()
804 (sctx->const_and_shader_buffers[processor].enabled_mask & in si_dump_descriptors()
807 enabled_samplers = sctx->samplers[processor].enabled_mask; in si_dump_descriptors()
808 enabled_images = sctx->images[processor].enabled_mask; in si_dump_descriptors()
811 if (stage == MESA_SHADER_VERTEX && sctx->vb_descriptors_buffer && in si_dump_descriptors()
812 sctx->vb_descriptors_gpu_list && sctx->vertex_elements) { in si_dump_descriptors()
816 desc.buffer = sctx->vb_descriptors_buffer; in si_dump_descriptors()
817 desc.list = sctx->vb_descriptors_gpu_list; in si_dump_descriptors()
818 desc.gpu_list = sctx->vb_descriptors_gpu_list; in si_dump_descriptors()
820 desc.num_active_slots = sctx->vertex_elements->vb_desc_list_alloc_size / 16; in si_dump_descriptors()
822 si_dump_descriptor_list(sctx->screen, &desc, name, " - Vertex buffer", 4, info->num_inputs, in si_dump_descriptors()
826 si_dump_descriptor_list(sctx->screen, &descs[SI_SHADER_DESCS_CONST_AND_SHADER_BUFFERS], name, in si_dump_descriptors()
829 si_dump_descriptor_list(sctx->screen, &descs[SI_SHADER_DESCS_CONST_AND_SHADER_BUFFERS], name, in si_dump_descriptors()
832 si_dump_descriptor_list(sctx->screen, &descs[SI_SHADER_DESCS_SAMPLERS_AND_IMAGES], name, in si_dump_descriptors()
835 si_dump_descriptor_list(sctx->screen, &descs[SI_SHADER_DESCS_SAMPLERS_AND_IMAGES], name, in si_dump_descriptors()
839 static void si_dump_gfx_descriptors(struct si_context *sctx, in si_dump_gfx_descriptors() argument
846 si_dump_descriptors(sctx, state->cso->info.stage, &state->cso->info, log); in si_dump_gfx_descriptors()
849 static void si_dump_compute_descriptors(struct si_context *sctx, struct u_log_context *log) in si_dump_compute_descriptors() argument
851 if (!sctx->cs_shader_state.program) in si_dump_compute_descriptors()
854 si_dump_descriptors(sctx, MESA_SHADER_COMPUTE, NULL, log); in si_dump_compute_descriptors()
1010 static void si_dump_annotated_shaders(struct si_context *sctx, FILE *f) in si_dump_annotated_shaders() argument
1013 unsigned num_waves = ac_get_wave_info(sctx->chip_class, waves); in si_dump_annotated_shaders()
1017 si_print_annotated_shader(sctx->vs_shader.current, waves, num_waves, f); in si_dump_annotated_shaders()
1018 si_print_annotated_shader(sctx->tcs_shader.current, waves, num_waves, f); in si_dump_annotated_shaders()
1019 si_print_annotated_shader(sctx->tes_shader.current, waves, num_waves, f); in si_dump_annotated_shaders()
1020 si_print_annotated_shader(sctx->gs_shader.current, waves, num_waves, f); in si_dump_annotated_shaders()
1021 si_print_annotated_shader(sctx->ps_shader.current, waves, num_waves, f); in si_dump_annotated_shaders()
1061 struct si_context *sctx = (struct si_context *)ctx; in si_dump_debug_state() local
1063 if (sctx->log) in si_dump_debug_state()
1064 u_log_flush(sctx->log); in si_dump_debug_state()
1067 si_dump_debug_registers(sctx, f); in si_dump_debug_state()
1069 si_dump_annotated_shaders(sctx, f); in si_dump_debug_state()
1075 void si_log_draw_state(struct si_context *sctx, struct u_log_context *log) in si_log_draw_state() argument
1082 tcs_shader = &sctx->tcs_shader; in si_log_draw_state()
1083 if (sctx->tes_shader.cso && !sctx->tcs_shader.cso) in si_log_draw_state()
1084 tcs_shader = &sctx->fixed_func_tcs_shader; in si_log_draw_state()
1086 si_dump_framebuffer(sctx, log); in si_log_draw_state()
1088 si_dump_gfx_shader(sctx, &sctx->vs_shader, log); in si_log_draw_state()
1089 si_dump_gfx_shader(sctx, tcs_shader, log); in si_log_draw_state()
1090 si_dump_gfx_shader(sctx, &sctx->tes_shader, log); in si_log_draw_state()
1091 si_dump_gfx_shader(sctx, &sctx->gs_shader, log); in si_log_draw_state()
1092 si_dump_gfx_shader(sctx, &sctx->ps_shader, log); in si_log_draw_state()
1094 si_dump_descriptor_list(sctx->screen, &sctx->descriptors[SI_DESCS_RW_BUFFERS], "", "RW buffers", in si_log_draw_state()
1095 4, sctx->descriptors[SI_DESCS_RW_BUFFERS].num_active_slots, si_identity, in si_log_draw_state()
1097 si_dump_gfx_descriptors(sctx, &sctx->vs_shader, log); in si_log_draw_state()
1098 si_dump_gfx_descriptors(sctx, tcs_shader, log); in si_log_draw_state()
1099 si_dump_gfx_descriptors(sctx, &sctx->tes_shader, log); in si_log_draw_state()
1100 si_dump_gfx_descriptors(sctx, &sctx->gs_shader, log); in si_log_draw_state()
1101 si_dump_gfx_descriptors(sctx, &sctx->ps_shader, log); in si_log_draw_state()
1104 void si_log_compute_state(struct si_context *sctx, struct u_log_context *log) in si_log_compute_state() argument
1109 si_dump_compute_shader(sctx, log); in si_log_compute_state()
1110 si_dump_compute_descriptors(sctx, log); in si_log_compute_state()
1113 static void si_dump_dma(struct si_context *sctx, struct radeon_saved_cs *saved, FILE *f) in si_dump_dma() argument
1118 si_dump_bo_list(sctx, saved, f); in si_dump_dma()
1132 void si_check_vm_faults(struct si_context *sctx, struct radeon_saved_cs *saved, enum ring_type ring) in si_check_vm_faults() argument
1134 struct pipe_screen *screen = sctx->b.screen; in si_check_vm_faults()
1139 if (!ac_vm_fault_occured(sctx->chip_class, &sctx->dmesg_timestamp, &addr)) in si_check_vm_faults()
1154 if (sctx->apitrace_call_number) in si_check_vm_faults()
1155 fprintf(f, "Last apitrace call: %u\n\n", sctx->apitrace_call_number); in si_check_vm_faults()
1162 si_log_draw_state(sctx, &log); in si_check_vm_faults()
1163 si_log_compute_state(sctx, &log); in si_check_vm_faults()
1164 si_log_cs(sctx, &log, true); in si_check_vm_faults()
1171 si_dump_dma(sctx, saved, f); in si_check_vm_faults()
1184 void si_init_debug_functions(struct si_context *sctx) in si_init_debug_functions() argument
1186 sctx->b.dump_debug_state = si_dump_debug_state; in si_init_debug_functions()
1191 if (sctx->screen->debug_flags & DBG(CHECK_VM)) in si_init_debug_functions()
1192 ac_vm_fault_occured(sctx->chip_class, &sctx->dmesg_timestamp, NULL); in si_init_debug_functions()