Lines Matching refs:sscreen
139 void si_init_compiler(struct si_screen *sscreen, struct ac_llvm_compiler *compiler) in si_init_compiler() argument
144 !sscreen->info.has_dedicated_vram && sscreen->info.chip_class <= GFX8; in si_init_compiler()
147 (sscreen->debug_flags & DBG(GISEL) ? AC_TM_ENABLE_GLOBAL_ISEL : 0) | in si_init_compiler()
148 (sscreen->info.chip_class <= GFX8 ? AC_TM_FORCE_DISABLE_XNACK : in si_init_compiler()
149 sscreen->info.chip_class <= GFX10 ? AC_TM_FORCE_ENABLE_XNACK : 0) | in si_init_compiler()
150 (!sscreen->llvm_has_working_vgpr_indexing ? AC_TM_PROMOTE_ALLOCA_TO_SCRATCH : 0) | in si_init_compiler()
151 (sscreen->debug_flags & DBG(CHECK_IR) ? AC_TM_CHECK_IR : 0) | in si_init_compiler()
155 ac_init_llvm_compiler(compiler, sscreen->info.family, tm_options); in si_init_compiler()
334 struct si_screen *sscreen = sctx->screen; in si_get_reset_status() local
346 simple_mtx_lock(&sscreen->aux_context_lock); in si_get_reset_status()
348 struct u_log_context *aux_log = ((struct si_context *)sscreen->aux_context)->log; in si_get_reset_status()
349 sscreen->aux_context->set_log_context(sscreen->aux_context, NULL); in si_get_reset_status()
350 sscreen->aux_context->destroy(sscreen->aux_context); in si_get_reset_status()
352 sscreen->aux_context = si_create_context( in si_get_reset_status()
353 &sscreen->b, (sscreen->options.aux_debug ? PIPE_CONTEXT_DEBUG : 0) | in si_get_reset_status()
354 (sscreen->info.has_graphics ? 0 : PIPE_CONTEXT_COMPUTE_ONLY)); in si_get_reset_status()
355 sscreen->aux_context->set_log_context(sscreen->aux_context, aux_log); in si_get_reset_status()
356 simple_mtx_unlock(&sscreen->aux_context_lock); in si_get_reset_status()
436 struct si_screen *sscreen = (struct si_screen *)screen; in si_create_context() local
440 if (!sscreen->info.has_graphics && !(flags & PIPE_CONTEXT_COMPUTE_ONLY)) in si_create_context()
444 struct radeon_winsys *ws = sscreen->ws; in si_create_context()
451 sctx->has_graphics = sscreen->info.chip_class == GFX6 || !(flags & PIPE_CONTEXT_COMPUTE_ONLY); in si_create_context()
454 sscreen->record_llvm_ir = true; /* racy but not critical */ in si_create_context()
459 sctx->screen = sscreen; /* Easy accessing of screen/winsys. */ in si_create_context()
462 slab_create_child(&sctx->pool_transfers, &sscreen->pool_transfers); in si_create_context()
463 slab_create_child(&sctx->pool_transfers_unsync, &sscreen->pool_transfers); in si_create_context()
465 sctx->ws = sscreen->ws; in si_create_context()
466 sctx->family = sscreen->info.family; in si_create_context()
467 sctx->chip_class = sscreen->info.chip_class; in si_create_context()
471 &sscreen->b, SI_RESOURCE_FLAG_DRIVER_INTERNAL, in si_create_context()
472 PIPE_USAGE_DEFAULT, 16 * sscreen->info.num_render_backends, 256); in si_create_context()
475 &sscreen->b, PIPE_RESOURCE_FLAG_ENCRYPTED | SI_RESOURCE_FLAG_DRIVER_INTERNAL, in si_create_context()
476 PIPE_USAGE_DEFAULT, 16 * sscreen->info.num_render_backends, 256); in si_create_context()
515 if (sscreen->info.num_rings[RING_DMA] && !(sscreen->debug_flags & DBG(NO_SDMA)) && in si_create_context()
516 sscreen->debug_flags & DBG(FORCE_SDMA)) { in si_create_context()
521 bool use_sdma_upload = sscreen->info.has_dedicated_vram && sctx->sdma_cs; in si_create_context()
550 sctx->ngg = sscreen->use_ngg; in si_create_context()
606 bool is_aux_context = !sscreen->aux_context; in si_create_context()
607 si_initialize_prim_discard_tunables(sscreen, is_aux_context, in si_create_context()
620 if (sscreen->debug_flags & DBG(FORCE_SDMA)) in si_create_context()
626 if (sscreen->info.has_hw_decode) { in si_create_context()
639 sscreen->info.tcc_cache_line_size); in si_create_context()
643 if (sscreen->info.has_tmz_support) { in si_create_context()
649 sscreen->info.tcc_cache_line_size); in si_create_context()
698 MAX2(32 * sscreen->info.num_good_compute_units, max_threads_per_block / 64); in si_create_context()
754 struct si_screen *sscreen = (struct si_screen *)screen; in si_pipe_create_context() local
758 if (sscreen->debug_flags & DBG(CHECK_VM)) in si_pipe_create_context()
772 if (sscreen->debug_flags & DBG_ALL_SHADERS) in si_pipe_create_context()
778 ctx, &sscreen->pool_transfers, si_replace_buffer_storage, in si_pipe_create_context()
779 sscreen->info.is_amdgpu ? si_create_fence : NULL, in si_pipe_create_context()
794 struct si_screen *sscreen = (struct si_screen *)pscreen; in si_destroy_screen() local
795 struct si_shader_part *parts[] = {sscreen->vs_prologs, sscreen->tcs_epilogs, sscreen->gs_prologs, in si_destroy_screen()
796 sscreen->ps_prologs, sscreen->ps_epilogs}; in si_destroy_screen()
799 if (!sscreen->ws->unref(sscreen->ws)) in si_destroy_screen()
802 if (sscreen->debug_flags & DBG(CACHE_STATS)) { in si_destroy_screen()
803 printf("live shader cache: hits = %u, misses = %u\n", sscreen->live_shader_cache.hits, in si_destroy_screen()
804 sscreen->live_shader_cache.misses); in si_destroy_screen()
805 printf("memory shader cache: hits = %u, misses = %u\n", sscreen->num_memory_shader_cache_hits, in si_destroy_screen()
806 sscreen->num_memory_shader_cache_misses); in si_destroy_screen()
807 printf("disk shader cache: hits = %u, misses = %u\n", sscreen->num_disk_shader_cache_hits, in si_destroy_screen()
808 sscreen->num_disk_shader_cache_misses); in si_destroy_screen()
811 simple_mtx_destroy(&sscreen->aux_context_lock); in si_destroy_screen()
813 struct u_log_context *aux_log = ((struct si_context *)sscreen->aux_context)->log; in si_destroy_screen()
815 sscreen->aux_context->set_log_context(sscreen->aux_context, NULL); in si_destroy_screen()
820 sscreen->aux_context->destroy(sscreen->aux_context); in si_destroy_screen()
822 util_queue_destroy(&sscreen->shader_compiler_queue); in si_destroy_screen()
823 util_queue_destroy(&sscreen->shader_compiler_queue_low_priority); in si_destroy_screen()
828 for (i = 0; i < ARRAY_SIZE(sscreen->compiler); i++) in si_destroy_screen()
829 si_destroy_compiler(&sscreen->compiler[i]); in si_destroy_screen()
831 for (i = 0; i < ARRAY_SIZE(sscreen->compiler_lowp); i++) in si_destroy_screen()
832 si_destroy_compiler(&sscreen->compiler_lowp[i]); in si_destroy_screen()
844 simple_mtx_destroy(&sscreen->shader_parts_mutex); in si_destroy_screen()
845 si_destroy_shader_cache(sscreen); in si_destroy_screen()
847 si_destroy_perfcounters(sscreen); in si_destroy_screen()
848 si_gpu_load_kill_thread(sscreen); in si_destroy_screen()
850 simple_mtx_destroy(&sscreen->gpu_load_mutex); in si_destroy_screen()
852 slab_destroy_parent(&sscreen->pool_transfers); in si_destroy_screen()
854 disk_cache_destroy(sscreen->disk_shader_cache); in si_destroy_screen()
855 util_live_shader_cache_deinit(&sscreen->live_shader_cache); in si_destroy_screen()
856 sscreen->ws->destroy(sscreen->ws); in si_destroy_screen()
857 FREE(sscreen); in si_destroy_screen()
860 static void si_init_gs_info(struct si_screen *sscreen) in si_init_gs_info() argument
862 sscreen->gs_table_depth = ac_get_gs_table_depth(sscreen->info.chip_class, sscreen->info.family); in si_init_gs_info()
865 static void si_test_vmfault(struct si_screen *sscreen, uint64_t test_flags) in si_test_vmfault() argument
867 struct pipe_context *ctx = sscreen->aux_context; in si_test_vmfault()
869 struct pipe_resource *buf = pipe_buffer_create_const0(&sscreen->b, 0, PIPE_USAGE_DEFAULT, 64); in si_test_vmfault()
927 static void si_disk_cache_create(struct si_screen *sscreen) in si_disk_cache_create() argument
930 if (sscreen->debug_flags & DBG_ALL_SHADERS) in si_disk_cache_create()
946 sscreen->disk_shader_cache = disk_cache_create(sscreen->info.name, cache_id, in si_disk_cache_create()
947 sscreen->info.address32_hi); in si_disk_cache_create()
952 struct si_screen *sscreen = (struct si_screen *)screen; in si_set_max_shader_compiler_threads() local
956 util_queue_adjust_num_threads(&sscreen->shader_compiler_queue, max_threads); in si_set_max_shader_compiler_threads()
971 struct si_screen *sscreen = CALLOC_STRUCT(si_screen); in radeonsi_screen_create_impl() local
975 if (!sscreen) { in radeonsi_screen_create_impl()
979 sscreen->ws = ws; in radeonsi_screen_create_impl()
980 ws->query_info(ws, &sscreen->info); in radeonsi_screen_create_impl()
983 sscreen->info.has_packed_math_16bit &= LLVM_VERSION_MAJOR >= 11; in radeonsi_screen_create_impl()
985 if (sscreen->info.chip_class == GFX10_3 && LLVM_VERSION_MAJOR < 11) { in radeonsi_screen_create_impl()
987 FREE(sscreen); in radeonsi_screen_create_impl()
991 if (sscreen->info.chip_class == GFX10 && LLVM_VERSION_MAJOR < 9) { in radeonsi_screen_create_impl()
993 FREE(sscreen); in radeonsi_screen_create_impl()
997 if (sscreen->info.chip_class >= GFX9) { in radeonsi_screen_create_impl()
998 sscreen->se_tile_repeat = 32 * sscreen->info.max_se; in radeonsi_screen_create_impl()
1000 ac_get_raster_config(&sscreen->info, &sscreen->pa_sc_raster_config, in radeonsi_screen_create_impl()
1001 &sscreen->pa_sc_raster_config_1, &sscreen->se_tile_repeat); in radeonsi_screen_create_impl()
1004 sscreen->debug_flags = debug_get_flags_option("R600_DEBUG", debug_options, 0); in radeonsi_screen_create_impl()
1005 sscreen->debug_flags |= debug_get_flags_option("AMD_DEBUG", debug_options, 0); in radeonsi_screen_create_impl()
1008 if (sscreen->debug_flags & DBG(NO_GFX)) in radeonsi_screen_create_impl()
1009 sscreen->info.has_graphics = false; in radeonsi_screen_create_impl()
1011 if ((sscreen->debug_flags & DBG(TMZ)) && in radeonsi_screen_create_impl()
1012 !sscreen->info.has_tmz_support) { in radeonsi_screen_create_impl()
1014 FREE(sscreen); in radeonsi_screen_create_impl()
1020 sscreen->b.context_create = si_pipe_create_context; in radeonsi_screen_create_impl()
1021 sscreen->b.destroy = si_destroy_screen; in radeonsi_screen_create_impl()
1022 sscreen->b.set_max_shader_compiler_threads = si_set_max_shader_compiler_threads; in radeonsi_screen_create_impl()
1023 sscreen->b.is_parallel_shader_compilation_finished = si_is_parallel_shader_compilation_finished; in radeonsi_screen_create_impl()
1024 sscreen->b.finalize_nir = si_finalize_nir; in radeonsi_screen_create_impl()
1026 si_init_screen_get_functions(sscreen); in radeonsi_screen_create_impl()
1027 si_init_screen_buffer_functions(sscreen); in radeonsi_screen_create_impl()
1028 si_init_screen_fence_functions(sscreen); in radeonsi_screen_create_impl()
1029 si_init_screen_state_functions(sscreen); in radeonsi_screen_create_impl()
1030 si_init_screen_texture_functions(sscreen); in radeonsi_screen_create_impl()
1031 si_init_screen_query_functions(sscreen); in radeonsi_screen_create_impl()
1032 si_init_screen_live_shader_cache(sscreen); in radeonsi_screen_create_impl()
1038 sscreen->debug_flags |= DBG(FS_CORRECT_DERIVS_AFTER_KILL); in radeonsi_screen_create_impl()
1040 if (sscreen->debug_flags & DBG(INFO)) in radeonsi_screen_create_impl()
1041 ac_print_gpu_info(&sscreen->info, stdout); in radeonsi_screen_create_impl()
1043 slab_create_parent(&sscreen->pool_transfers, sizeof(struct si_transfer), 64); in radeonsi_screen_create_impl()
1045 sscreen->force_aniso = MIN2(16, debug_get_num_option("R600_TEX_ANISO", -1)); in radeonsi_screen_create_impl()
1046 if (sscreen->force_aniso == -1) { in radeonsi_screen_create_impl()
1047 sscreen->force_aniso = MIN2(16, debug_get_num_option("AMD_TEX_ANISO", -1)); in radeonsi_screen_create_impl()
1050 if (sscreen->force_aniso >= 0) { in radeonsi_screen_create_impl()
1053 1 << util_logbase2(sscreen->force_aniso)); in radeonsi_screen_create_impl()
1056 (void)simple_mtx_init(&sscreen->aux_context_lock, mtx_plain); in radeonsi_screen_create_impl()
1057 (void)simple_mtx_init(&sscreen->gpu_load_mutex, mtx_plain); in radeonsi_screen_create_impl()
1059 si_init_gs_info(sscreen); in radeonsi_screen_create_impl()
1060 if (!si_init_shader_cache(sscreen)) { in radeonsi_screen_create_impl()
1061 FREE(sscreen); in radeonsi_screen_create_impl()
1067 sscreen->options.name = driQueryOptionb(config->options, "radeonsi_" #name); in radeonsi_screen_create_impl()
1071 si_disk_cache_create(sscreen); in radeonsi_screen_create_impl()
1090 num_comp_hi_threads = MIN2(num_comp_hi_threads, ARRAY_SIZE(sscreen->compiler)); in radeonsi_screen_create_impl()
1091 num_comp_lo_threads = MIN2(num_comp_lo_threads, ARRAY_SIZE(sscreen->compiler_lowp)); in radeonsi_screen_create_impl()
1097 &sscreen->shader_compiler_queue, "sh", 64, num_comp_hi_threads, in radeonsi_screen_create_impl()
1099 si_destroy_shader_cache(sscreen); in radeonsi_screen_create_impl()
1100 FREE(sscreen); in radeonsi_screen_create_impl()
1105 if (!util_queue_init(&sscreen->shader_compiler_queue_low_priority, "shlo", 64, in radeonsi_screen_create_impl()
1109 si_destroy_shader_cache(sscreen); in radeonsi_screen_create_impl()
1110 FREE(sscreen); in radeonsi_screen_create_impl()
1116 si_init_perfcounters(sscreen); in radeonsi_screen_create_impl()
1119 si_initialize_prim_discard_tunables(sscreen, false, &prim_discard_vertex_count_threshold, &tmp); in radeonsi_screen_create_impl()
1122 sscreen->num_vbos_in_user_sgprs = sscreen->info.chip_class >= GFX9 ? 5 : 1; in radeonsi_screen_create_impl()
1125 bool double_offchip_buffers = sscreen->info.chip_class >= GFX7 && in radeonsi_screen_create_impl()
1126 sscreen->info.family != CHIP_CARRIZO && in radeonsi_screen_create_impl()
1127 sscreen->info.family != CHIP_STONEY; in radeonsi_screen_create_impl()
1133 if (sscreen->info.chip_class >= GFX10) in radeonsi_screen_create_impl()
1136 else if (sscreen->info.family == CHIP_VEGA12 || sscreen->info.family == CHIP_VEGA20) in radeonsi_screen_create_impl()
1141 unsigned max_offchip_buffers = max_offchip_buffers_per_se * sscreen->info.max_se; in radeonsi_screen_create_impl()
1147 if (sscreen->info.family == CHIP_HAWAII) { in radeonsi_screen_create_impl()
1148 sscreen->tess_offchip_block_dw_size = 4096; in radeonsi_screen_create_impl()
1151 sscreen->tess_offchip_block_dw_size = 8192; in radeonsi_screen_create_impl()
1155 sscreen->tess_factor_ring_size = 32768 * sscreen->info.max_se; in radeonsi_screen_create_impl()
1156 sscreen->tess_offchip_ring_size = max_offchip_buffers * sscreen->tess_offchip_block_dw_size * 4; in radeonsi_screen_create_impl()
1158 if (sscreen->info.chip_class >= GFX10_3) { in radeonsi_screen_create_impl()
1159 sscreen->vgt_hs_offchip_param = in radeonsi_screen_create_impl()
1162 } else if (sscreen->info.chip_class >= GFX7) { in radeonsi_screen_create_impl()
1163 if (sscreen->info.chip_class >= GFX8) in radeonsi_screen_create_impl()
1165 sscreen->vgt_hs_offchip_param = S_03093C_OFFCHIP_BUFFERING_GFX7(max_offchip_buffers) | in radeonsi_screen_create_impl()
1169 sscreen->vgt_hs_offchip_param = S_0089B0_OFFCHIP_BUFFERING(max_offchip_buffers); in radeonsi_screen_create_impl()
1172 sscreen->has_draw_indirect_multi = in radeonsi_screen_create_impl()
1173 (sscreen->info.family >= CHIP_POLARIS10) || in radeonsi_screen_create_impl()
1174 (sscreen->info.chip_class == GFX8 && sscreen->info.pfp_fw_version >= 121 && in radeonsi_screen_create_impl()
1175 sscreen->info.me_fw_version >= 87) || in radeonsi_screen_create_impl()
1176 (sscreen->info.chip_class == GFX7 && sscreen->info.pfp_fw_version >= 211 && in radeonsi_screen_create_impl()
1177 sscreen->info.me_fw_version >= 173) || in radeonsi_screen_create_impl()
1178 (sscreen->info.chip_class == GFX6 && sscreen->info.pfp_fw_version >= 79 && in radeonsi_screen_create_impl()
1179 sscreen->info.me_fw_version >= 142); in radeonsi_screen_create_impl()
1181 sscreen->has_out_of_order_rast = in radeonsi_screen_create_impl()
1182 sscreen->info.has_out_of_order_rast && !(sscreen->debug_flags & DBG(NO_OUT_OF_ORDER)); in radeonsi_screen_create_impl()
1183 sscreen->assume_no_z_fights = driQueryOptionb(config->options, "radeonsi_assume_no_z_fights") || in radeonsi_screen_create_impl()
1185 sscreen->commutative_blend_add = in radeonsi_screen_create_impl()
1189 sscreen->use_ngg = !(sscreen->debug_flags & DBG(NO_NGG)) && in radeonsi_screen_create_impl()
1190 sscreen->info.chip_class >= GFX10 && in radeonsi_screen_create_impl()
1191 (sscreen->info.family != CHIP_NAVI14 || in radeonsi_screen_create_impl()
1192 sscreen->info.is_pro_graphics) && in radeonsi_screen_create_impl()
1193 sscreen->info.has_dedicated_vram; in radeonsi_screen_create_impl()
1194 sscreen->use_ngg_culling = sscreen->use_ngg && !(sscreen->debug_flags & DBG(NO_NGG_CULLING)); in radeonsi_screen_create_impl()
1195 sscreen->use_ngg_streamout = false; in radeonsi_screen_create_impl()
1198 if (sscreen->info.chip_class >= GFX10) { in radeonsi_screen_create_impl()
1199 sscreen->dpbb_allowed = true; in radeonsi_screen_create_impl()
1201 } else if (sscreen->info.chip_class == GFX9) { in radeonsi_screen_create_impl()
1202 sscreen->dpbb_allowed = !sscreen->info.has_dedicated_vram; in radeonsi_screen_create_impl()
1203 sscreen->dfsm_allowed = !sscreen->info.has_dedicated_vram; in radeonsi_screen_create_impl()
1207 if (sscreen->debug_flags & DBG(DPBB)) { in radeonsi_screen_create_impl()
1208 sscreen->dpbb_allowed = true; in radeonsi_screen_create_impl()
1209 if (sscreen->debug_flags & DBG(DFSM)) in radeonsi_screen_create_impl()
1210 sscreen->dfsm_allowed = true; in radeonsi_screen_create_impl()
1214 if (sscreen->debug_flags & DBG(NO_DPBB)) { in radeonsi_screen_create_impl()
1215 sscreen->dpbb_allowed = false; in radeonsi_screen_create_impl()
1216 sscreen->dfsm_allowed = false; in radeonsi_screen_create_impl()
1217 } else if (sscreen->debug_flags & DBG(NO_DFSM)) { in radeonsi_screen_create_impl()
1218 sscreen->dfsm_allowed = false; in radeonsi_screen_create_impl()
1221 if (sscreen->dpbb_allowed) { in radeonsi_screen_create_impl()
1222 if (sscreen->info.has_dedicated_vram) { in radeonsi_screen_create_impl()
1223 if (sscreen->info.num_render_backends > 4) { in radeonsi_screen_create_impl()
1224 sscreen->pbb_context_states_per_bin = 1; in radeonsi_screen_create_impl()
1225 sscreen->pbb_persistent_states_per_bin = 1; in radeonsi_screen_create_impl()
1227 sscreen->pbb_context_states_per_bin = 3; in radeonsi_screen_create_impl()
1228 sscreen->pbb_persistent_states_per_bin = 8; in radeonsi_screen_create_impl()
1235 sscreen->pbb_context_states_per_bin = sscreen->info.has_gfx9_scissor_bug ? 1 : 6; in radeonsi_screen_create_impl()
1237 sscreen->pbb_persistent_states_per_bin = 16; in radeonsi_screen_create_impl()
1240 assert(sscreen->pbb_context_states_per_bin >= 1 && in radeonsi_screen_create_impl()
1241 sscreen->pbb_context_states_per_bin <= 6); in radeonsi_screen_create_impl()
1242 assert(sscreen->pbb_persistent_states_per_bin >= 1 && in radeonsi_screen_create_impl()
1243 sscreen->pbb_persistent_states_per_bin <= 32); in radeonsi_screen_create_impl()
1249 sscreen->llvm_has_working_vgpr_indexing = sscreen->info.chip_class != GFX9; in radeonsi_screen_create_impl()
1251 sscreen->dcc_msaa_allowed = !(sscreen->debug_flags & DBG(NO_DCC_MSAA)); in radeonsi_screen_create_impl()
1253 (void)simple_mtx_init(&sscreen->shader_parts_mutex, mtx_plain); in radeonsi_screen_create_impl()
1254 sscreen->use_monolithic_shaders = (sscreen->debug_flags & DBG(MONOLITHIC_SHADERS)) != 0; in radeonsi_screen_create_impl()
1256 sscreen->barrier_flags.cp_to_L2 = SI_CONTEXT_INV_SCACHE | SI_CONTEXT_INV_VCACHE; in radeonsi_screen_create_impl()
1257 if (sscreen->info.chip_class <= GFX8) { in radeonsi_screen_create_impl()
1258 sscreen->barrier_flags.cp_to_L2 |= SI_CONTEXT_INV_L2; in radeonsi_screen_create_impl()
1259 sscreen->barrier_flags.L2_to_cp |= SI_CONTEXT_WB_L2; in radeonsi_screen_create_impl()
1263 sscreen->debug_flags |= DBG_ALL_SHADERS; in radeonsi_screen_create_impl()
1279 if (sscreen->info.has_eqaa_surface_allocator) { in radeonsi_screen_create_impl()
1284 sscreen->eqaa_force_coverage_samples = s; in radeonsi_screen_create_impl()
1285 sscreen->eqaa_force_z_samples = z; in radeonsi_screen_create_impl()
1286 sscreen->eqaa_force_color_samples = f; in radeonsi_screen_create_impl()
1290 sscreen->ge_wave_size = 64; in radeonsi_screen_create_impl()
1291 sscreen->ps_wave_size = 64; in radeonsi_screen_create_impl()
1292 sscreen->compute_wave_size = 64; in radeonsi_screen_create_impl()
1294 if (sscreen->info.chip_class >= GFX10) { in radeonsi_screen_create_impl()
1304 if (sscreen->debug_flags & DBG(W32_GE)) in radeonsi_screen_create_impl()
1305 sscreen->ge_wave_size = 32; in radeonsi_screen_create_impl()
1306 if (sscreen->debug_flags & DBG(W32_PS)) in radeonsi_screen_create_impl()
1307 sscreen->ps_wave_size = 32; in radeonsi_screen_create_impl()
1308 if (sscreen->debug_flags & DBG(W32_CS)) in radeonsi_screen_create_impl()
1309 sscreen->compute_wave_size = 32; in radeonsi_screen_create_impl()
1311 if (sscreen->debug_flags & DBG(W64_GE)) in radeonsi_screen_create_impl()
1312 sscreen->ge_wave_size = 64; in radeonsi_screen_create_impl()
1313 if (sscreen->debug_flags & DBG(W64_PS)) in radeonsi_screen_create_impl()
1314 sscreen->ps_wave_size = 64; in radeonsi_screen_create_impl()
1315 if (sscreen->debug_flags & DBG(W64_CS)) in radeonsi_screen_create_impl()
1316 sscreen->compute_wave_size = 64; in radeonsi_screen_create_impl()
1320 sscreen->aux_context = si_create_context( in radeonsi_screen_create_impl()
1321 &sscreen->b, (sscreen->options.aux_debug ? PIPE_CONTEXT_DEBUG : 0) | in radeonsi_screen_create_impl()
1322 (sscreen->info.has_graphics ? 0 : PIPE_CONTEXT_COMPUTE_ONLY)); in radeonsi_screen_create_impl()
1323 if (sscreen->options.aux_debug) { in radeonsi_screen_create_impl()
1326 sscreen->aux_context->set_log_context(sscreen->aux_context, log); in radeonsi_screen_create_impl()
1330 si_test_dma(sscreen); in radeonsi_screen_create_impl()
1333 si_test_dma_perf(sscreen); in radeonsi_screen_create_impl()
1337 si_test_vmfault(sscreen, test_flags); in radeonsi_screen_create_impl()
1340 si_test_gds((struct si_context *)sscreen->aux_context); in radeonsi_screen_create_impl()
1343 si_test_gds_memory_management((struct si_context *)sscreen->aux_context, 32 * 1024, 4, in radeonsi_screen_create_impl()
1347 si_test_gds_memory_management((struct si_context *)sscreen->aux_context, 4, 1, in radeonsi_screen_create_impl()
1351 ac_print_shadowed_regs(&sscreen->info); in radeonsi_screen_create_impl()
1354 return &sscreen->b; in radeonsi_screen_create_impl()