Lines Matching refs:sctx
1288 void cik_init_sdma_functions(struct si_context *sctx);
1299 void si_blitter_begin(struct si_context *sctx, enum si_blitter_op op);
1300 void si_blitter_end(struct si_context *sctx);
1301 void si_init_blit_functions(struct si_context *sctx);
1302 void si_decompress_textures(struct si_context *sctx, unsigned shader_mask);
1309 void si_decompress_dcc(struct si_context *sctx, struct si_texture *tex);
1312 bool si_rings_is_buffer_referenced(struct si_context *sctx, struct pb_buffer *buf,
1314 void *si_buffer_map_sync_with_rings(struct si_context *sctx, struct si_resource *resource,
1326 void si_init_buffer_functions(struct si_context *sctx);
1331 bool vi_dcc_clear_level(struct si_context *sctx, struct si_texture *tex, unsigned level,
1333 void si_init_clear_functions(struct si_context *sctx);
1336 unsigned si_get_flush_flags(struct si_context *sctx, enum si_coherency coher,
1338 void si_clear_buffer(struct si_context *sctx, struct pipe_resource *dst, uint64_t offset,
1341 void si_copy_buffer(struct si_context *sctx, struct pipe_resource *dst, struct pipe_resource *src,
1343 void si_compute_copy_image(struct si_context *sctx, struct pipe_resource *dst, unsigned dst_level,
1351 void si_retile_dcc(struct si_context *sctx, struct si_texture *tex);
1353 void si_init_compute_blit_functions(struct si_context *sctx);
1366 void si_cp_dma_wait_for_idle(struct si_context *sctx);
1367 void si_cp_dma_clear_buffer(struct si_context *sctx, struct radeon_cmdbuf *cs,
1371 void si_cp_dma_copy_buffer(struct si_context *sctx, struct pipe_resource *dst,
1375 void cik_prefetch_TC_L2_async(struct si_context *sctx, struct pipe_resource *buf, uint64_t offset,
1377 void cik_emit_prefetch_L2(struct si_context *sctx, bool vertex_stage_only);
1378 void si_test_gds(struct si_context *sctx);
1379 void si_cp_write_data(struct si_context *sctx, struct si_resource *buf, unsigned offset,
1381 void si_cp_copy_data(struct si_context *sctx, struct radeon_cmdbuf *cs, unsigned dst_sel,
1386 void si_init_cp_reg_shadowing(struct si_context *sctx);
1394 void si_log_hw_flush(struct si_context *sctx);
1395 void si_log_draw_state(struct si_context *sctx, struct u_log_context *log);
1396 void si_log_compute_state(struct si_context *sctx, struct u_log_context *log);
1397 void si_init_debug_functions(struct si_context *sctx);
1398 void si_check_vm_faults(struct si_context *sctx, struct radeon_saved_cs *saved,
1403 void si_dma_emit_timestamp(struct si_context *sctx, struct si_resource *dst, uint64_t offset);
1404 void si_sdma_clear_buffer(struct si_context *sctx, struct pipe_resource *dst, uint64_t offset,
1406 void si_sdma_copy_buffer(struct si_context *sctx, struct pipe_resource *dst,
1437 void si_unref_sdma_uploads(struct si_context *sctx);
1445 void si_emit_initial_compute_regs(struct si_context *sctx, struct radeon_cmdbuf *cs);
1446 void si_init_compute_functions(struct si_context *sctx);
1459 si_prepare_prim_discard_or_split_draw(struct si_context *sctx, const struct pipe_draw_info *info,
1463 void si_compute_signal_gfx(struct si_context *sctx);
1464 void si_dispatch_prim_discard_cs_and_draw(struct si_context *sctx,
1482 void si_init_query_functions(struct si_context *sctx);
1483 void si_suspend_queries(struct si_context *sctx);
1484 void si_resume_queries(struct si_context *sctx);
1487 void *si_get_blitter_vs(struct si_context *sctx, enum blitter_attrib_type type,
1489 void *si_create_fixed_func_tcs(struct si_context *sctx);
1500 void *si_create_query_result_cs(struct si_context *sctx);
1501 void *gfx10_create_sh_query_result_cs(struct si_context *sctx);
1504 void gfx10_init_query(struct si_context *sctx);
1505 void gfx10_destroy_query(struct si_context *sctx);
1521 void si_get_small_prim_cull_info(struct si_context *sctx, struct si_small_prim_cull_info *out);
1526 bool si_prepare_for_dma_blit(struct si_context *sctx, struct si_texture *dst, unsigned dst_level,
1529 void si_eliminate_fast_color_clear(struct si_context *sctx, struct si_texture *tex,
1541 void vi_disable_dcc_if_incompatible_format(struct si_context *sctx, struct pipe_resource *tex,
1548 void vi_separate_dcc_try_enable(struct si_context *sctx, struct si_texture *tex);
1549 void vi_separate_dcc_start_query(struct si_context *sctx, struct si_texture *tex);
1550 void vi_separate_dcc_stop_query(struct si_context *sctx, struct si_texture *tex);
1552 bool si_texture_disable_dcc(struct si_context *sctx, struct si_texture *tex);
1554 void si_init_context_texture_functions(struct si_context *sctx);
1576 si_shader_selector_reference(struct si_context *sctx, /* sctx can optionally be NULL */ in si_shader_selector_reference() argument
1583 util_shader_reference(&sctx->b, &sscreen->live_shader_cache, (void **)dst, src); in si_shader_selector_reference()
1599 static inline unsigned si_get_minimum_num_gfx_cs_dwords(struct si_context *sctx, in si_get_minimum_num_gfx_cs_dwords() argument
1609 return 2048 + sctx->num_cs_dw_queries_suspend + num_draws * 6; in si_get_minimum_num_gfx_cs_dwords()
1612 static inline void si_context_add_resource_size(struct si_context *sctx, struct pipe_resource *r) in si_context_add_resource_size() argument
1616 sctx->vram += si_resource(r)->vram_usage; in si_context_add_resource_size()
1617 sctx->gtt += si_resource(r)->gart_usage; in si_context_add_resource_size()
1621 static inline void si_invalidate_draw_sh_constants(struct si_context *sctx) in si_invalidate_draw_sh_constants() argument
1623 sctx->last_base_vertex = SI_BASE_VERTEX_UNKNOWN; in si_invalidate_draw_sh_constants()
1624 sctx->last_instance_count = SI_INSTANCE_COUNT_UNKNOWN; in si_invalidate_draw_sh_constants()
1627 static inline unsigned si_get_atom_bit(struct si_context *sctx, struct si_atom *atom) in si_get_atom_bit() argument
1629 return 1 << (atom - sctx->atoms.array); in si_get_atom_bit()
1632 static inline void si_set_atom_dirty(struct si_context *sctx, struct si_atom *atom, bool dirty) in si_set_atom_dirty() argument
1634 unsigned bit = si_get_atom_bit(sctx, atom); in si_set_atom_dirty()
1637 sctx->dirty_atoms |= bit; in si_set_atom_dirty()
1639 sctx->dirty_atoms &= ~bit; in si_set_atom_dirty()
1642 static inline bool si_is_atom_dirty(struct si_context *sctx, struct si_atom *atom) in si_is_atom_dirty() argument
1644 return (sctx->dirty_atoms & si_get_atom_bit(sctx, atom)) != 0; in si_is_atom_dirty()
1647 static inline void si_mark_atom_dirty(struct si_context *sctx, struct si_atom *atom) in si_mark_atom_dirty() argument
1649 si_set_atom_dirty(sctx, atom, true); in si_mark_atom_dirty()
1652 static inline struct si_shader_ctx_state *si_get_vs(struct si_context *sctx) in si_get_vs() argument
1654 if (sctx->gs_shader.cso) in si_get_vs()
1655 return &sctx->gs_shader; in si_get_vs()
1656 if (sctx->tes_shader.cso) in si_get_vs()
1657 return &sctx->tes_shader; in si_get_vs()
1659 return &sctx->vs_shader; in si_get_vs()
1662 static inline struct si_shader_info *si_get_vs_info(struct si_context *sctx) in si_get_vs_info() argument
1664 struct si_shader_ctx_state *vs = si_get_vs(sctx); in si_get_vs_info()
1669 static inline struct si_shader *si_get_vs_state(struct si_context *sctx) in si_get_vs_state() argument
1671 if (sctx->gs_shader.cso && sctx->gs_shader.current && !sctx->gs_shader.current->key.as_ngg) in si_get_vs_state()
1672 return sctx->gs_shader.cso->gs_copy_shader; in si_get_vs_state()
1674 struct si_shader_ctx_state *vs = si_get_vs(sctx); in si_get_vs_state()
1683 static inline bool si_get_strmout_en(struct si_context *sctx) in si_get_strmout_en() argument
1685 return sctx->streamout.streamout_enabled || sctx->streamout.prims_gen_query_enabled; in si_get_strmout_en()
1688 static inline unsigned si_optimal_tcc_alignment(struct si_context *sctx, unsigned upload_size) in si_optimal_tcc_alignment() argument
1698 tcc_cache_line_size = sctx->screen->info.tcc_cache_line_size; in si_optimal_tcc_alignment()
1710 static inline void si_make_CB_shader_coherent(struct si_context *sctx, unsigned num_samples, in si_make_CB_shader_coherent() argument
1713 sctx->flags |= SI_CONTEXT_FLUSH_AND_INV_CB | SI_CONTEXT_INV_VCACHE; in si_make_CB_shader_coherent()
1715 if (sctx->chip_class >= GFX10) { in si_make_CB_shader_coherent()
1716 if (sctx->screen->info.tcc_harvested) in si_make_CB_shader_coherent()
1717 sctx->flags |= SI_CONTEXT_INV_L2; in si_make_CB_shader_coherent()
1719 sctx->flags |= SI_CONTEXT_INV_L2_METADATA; in si_make_CB_shader_coherent()
1720 } else if (sctx->chip_class == GFX9) { in si_make_CB_shader_coherent()
1726 sctx->flags |= SI_CONTEXT_INV_L2; in si_make_CB_shader_coherent()
1728 sctx->flags |= SI_CONTEXT_INV_L2_METADATA; in si_make_CB_shader_coherent()
1731 sctx->flags |= SI_CONTEXT_INV_L2; in si_make_CB_shader_coherent()
1735 static inline void si_make_DB_shader_coherent(struct si_context *sctx, unsigned num_samples, in si_make_DB_shader_coherent() argument
1738 sctx->flags |= SI_CONTEXT_FLUSH_AND_INV_DB | SI_CONTEXT_INV_VCACHE; in si_make_DB_shader_coherent()
1740 if (sctx->chip_class >= GFX10) { in si_make_DB_shader_coherent()
1741 if (sctx->screen->info.tcc_harvested) in si_make_DB_shader_coherent()
1742 sctx->flags |= SI_CONTEXT_INV_L2; in si_make_DB_shader_coherent()
1744 sctx->flags |= SI_CONTEXT_INV_L2_METADATA; in si_make_DB_shader_coherent()
1745 } else if (sctx->chip_class == GFX9) { in si_make_DB_shader_coherent()
1751 sctx->flags |= SI_CONTEXT_INV_L2; in si_make_DB_shader_coherent()
1753 sctx->flags |= SI_CONTEXT_INV_L2_METADATA; in si_make_DB_shader_coherent()
1756 sctx->flags |= SI_CONTEXT_INV_L2; in si_make_DB_shader_coherent()
1780 static inline unsigned si_get_ps_iter_samples(struct si_context *sctx) in si_get_ps_iter_samples() argument
1782 if (sctx->ps_uses_fbfetch) in si_get_ps_iter_samples()
1783 return sctx->framebuffer.nr_color_samples; in si_get_ps_iter_samples()
1785 return MIN2(sctx->ps_iter_samples, sctx->framebuffer.nr_color_samples); in si_get_ps_iter_samples()
1788 static inline unsigned si_get_total_colormask(struct si_context *sctx) in si_get_total_colormask() argument
1790 if (sctx->queued.named.rasterizer->rasterizer_discard) in si_get_total_colormask()
1793 struct si_shader_selector *ps = sctx->ps_shader.cso; in si_get_total_colormask()
1798 sctx->framebuffer.colorbuf_enabled_4bit & sctx->queued.named.blend->cb_target_mask; in si_get_total_colormask()
1862 static inline void radeon_add_to_buffer_list(struct si_context *sctx, struct radeon_cmdbuf *cs, in radeon_add_to_buffer_list() argument
1867 sctx->ws->cs_add_buffer(cs, bo->buf, (enum radeon_bo_usage)(usage | RADEON_USAGE_SYNCHRONIZED), in radeon_add_to_buffer_list()
1888 static inline void radeon_add_to_gfx_buffer_list_check_mem(struct si_context *sctx, in radeon_add_to_gfx_buffer_list_check_mem() argument
1895 !radeon_cs_memory_below_limit(sctx->screen, sctx->gfx_cs, sctx->vram + bo->vram_usage, in radeon_add_to_gfx_buffer_list_check_mem()
1896 sctx->gtt + bo->gart_usage)) in radeon_add_to_gfx_buffer_list_check_mem()
1897 si_flush_gfx_cs(sctx, RADEON_FLUSH_ASYNC_START_NEXT_GFX_IB_NOW, NULL); in radeon_add_to_gfx_buffer_list_check_mem()
1899 radeon_add_to_buffer_list(sctx, sctx->gfx_cs, bo, usage, priority); in radeon_add_to_gfx_buffer_list_check_mem()
1902 static inline bool si_compute_prim_discard_enabled(struct si_context *sctx) in si_compute_prim_discard_enabled() argument
1904 return sctx->prim_discard_vertex_count_threshold != UINT_MAX; in si_compute_prim_discard_enabled()
1936 static inline unsigned si_get_num_coverage_samples(struct si_context *sctx) in si_get_num_coverage_samples() argument
1938 if (sctx->framebuffer.nr_samples > 1 && in si_get_num_coverage_samples()
1939 sctx->queued.named.rasterizer->multisample_enable) in si_get_num_coverage_samples()
1940 return sctx->framebuffer.nr_samples; in si_get_num_coverage_samples()
1943 if (sctx->smoothing_enabled) in si_get_num_coverage_samples()