Lines Matching refs:pm4
435 struct si_pm4_state *pm4 = &blend->pm4; in si_create_blend_state_mode() local
459 si_pm4_set_reg(pm4, R_028B70_DB_ALPHA_TO_MASK, in si_create_blend_state_mode()
465 si_pm4_set_reg(pm4, R_028B70_DB_ALPHA_TO_MASK, in si_create_blend_state_mode()
501 si_pm4_set_reg(pm4, R_028780_CB_BLEND0_CONTROL + i * 4, blend_cntl); in si_create_blend_state_mode()
511 si_pm4_set_reg(pm4, R_028780_CB_BLEND0_CONTROL + i * 4, blend_cntl); in si_create_blend_state_mode()
521 si_pm4_set_reg(pm4, R_028780_CB_BLEND0_CONTROL + i * 4, blend_cntl); in si_create_blend_state_mode()
577 si_pm4_set_reg(pm4, R_028780_CB_BLEND0_CONTROL + i * 4, blend_cntl); in si_create_blend_state_mode()
613 si_pm4_set_reg(pm4, R_028760_SX_MRT0_BLEND_OPT + i * 4, sx_mrt_blend_opt[i]); in si_create_blend_state_mode()
620 si_pm4_set_reg(pm4, R_028808_CB_COLOR_CONTROL, color_control); in si_create_blend_state_mode()
825 struct si_pm4_state *pm4 = &rs->pm4; in si_create_rs_state() local
881 pm4, R_0286D4_SPI_INTERP_CONTROL_0, in si_create_rs_state()
891 si_pm4_set_reg(pm4, R_028A00_PA_SU_POINT_SIZE, S_028A00_HEIGHT(tmp) | S_028A00_WIDTH(tmp)); in si_create_rs_state()
904 si_pm4_set_reg(pm4, R_028A04_PA_SU_POINT_MINMAX, in si_create_rs_state()
908 si_pm4_set_reg(pm4, R_028A08_PA_SU_LINE_CNTL, in si_create_rs_state()
911 pm4, R_028A48_PA_SC_MODE_CNTL_0, in si_create_rs_state()
917 si_pm4_set_reg(pm4, R_028B7C_PA_SU_POLY_OFFSET_CLAMP, fui(state->offset_clamp)); in si_create_rs_state()
918 si_pm4_set_reg(pm4, R_028814_PA_SU_SC_MODE_CNTL, in si_create_rs_state()
943 struct si_pm4_state *pm4 = &rs->pm4_poly_offset[i]; in si_create_rs_state() local
966 si_pm4_set_reg(pm4, R_028B80_PA_SU_POLY_OFFSET_FRONT_SCALE, fui(offset_scale)); in si_create_rs_state()
967 si_pm4_set_reg(pm4, R_028B84_PA_SU_POLY_OFFSET_FRONT_OFFSET, fui(offset_units)); in si_create_rs_state()
968 si_pm4_set_reg(pm4, R_028B88_PA_SU_POLY_OFFSET_BACK_SCALE, fui(offset_scale)); in si_create_rs_state()
969 si_pm4_set_reg(pm4, R_028B8C_PA_SU_POLY_OFFSET_BACK_OFFSET, fui(offset_units)); in si_create_rs_state()
970 si_pm4_set_reg(pm4, R_028B78_PA_SU_POLY_OFFSET_DB_FMT_CNTL, pa_su_poly_offset_db_fmt_cntl); in si_create_rs_state()
1135 struct si_pm4_state *pm4 = &dsa->pm4; in si_create_dsa_state() local
1179 si_pm4_set_reg(pm4, R_00B030_SPI_SHADER_USER_DATA_PS_0 + SI_SGPR_ALPHA_REF * 4, in si_create_dsa_state()
1185 si_pm4_set_reg(pm4, R_028800_DB_DEPTH_CONTROL, db_depth_control); in si_create_dsa_state()
1187 si_pm4_set_reg(pm4, R_02842C_DB_STENCIL_CONTROL, db_stencil_control); in si_create_dsa_state()
1189 si_pm4_set_reg(pm4, R_028020_DB_DEPTH_BOUNDS_MIN, fui(state->depth.bounds_min)); in si_create_dsa_state()
1190 si_pm4_set_reg(pm4, R_028024_DB_DEPTH_BOUNDS_MAX, fui(state->depth.bounds_max)); in si_create_dsa_state()
5012 static void si_set_grbm_gfx_index(struct si_context *sctx, struct si_pm4_state *pm4, unsigned value) in si_set_grbm_gfx_index() argument
5015 si_pm4_set_reg(pm4, reg, value); in si_set_grbm_gfx_index()
5018 static void si_set_grbm_gfx_index_se(struct si_context *sctx, struct si_pm4_state *pm4, unsigned se) in si_set_grbm_gfx_index_se() argument
5021 si_set_grbm_gfx_index(sctx, pm4, in si_set_grbm_gfx_index_se()
5027 static void si_write_harvested_raster_configs(struct si_context *sctx, struct si_pm4_state *pm4, in si_write_harvested_raster_configs() argument
5037 si_set_grbm_gfx_index_se(sctx, pm4, se); in si_write_harvested_raster_configs()
5038 si_pm4_set_reg(pm4, R_028350_PA_SC_RASTER_CONFIG, raster_config_se[se]); in si_write_harvested_raster_configs()
5040 si_set_grbm_gfx_index(sctx, pm4, ~0); in si_write_harvested_raster_configs()
5043 si_pm4_set_reg(pm4, R_028354_PA_SC_RASTER_CONFIG_1, raster_config_1); in si_write_harvested_raster_configs()
5047 static void si_set_raster_config(struct si_context *sctx, struct si_pm4_state *pm4) in si_set_raster_config() argument
5059 si_pm4_set_reg(pm4, R_028350_PA_SC_RASTER_CONFIG, raster_config); in si_set_raster_config()
5061 si_pm4_set_reg(pm4, R_028354_PA_SC_RASTER_CONFIG_1, raster_config_1); in si_set_raster_config()
5063 si_write_harvested_raster_configs(sctx, pm4, raster_config, raster_config_1); in si_set_raster_config()
5072 struct si_pm4_state *pm4 = CALLOC_STRUCT(si_pm4_state); in si_init_cs_preamble_state() local
5074 if (!pm4) in si_init_cs_preamble_state()
5078 si_pm4_cmd_add(pm4, PKT3(PKT3_CONTEXT_CONTROL, 1, 0)); in si_init_cs_preamble_state()
5079 si_pm4_cmd_add(pm4, CC0_UPDATE_LOAD_ENABLES(1)); in si_init_cs_preamble_state()
5080 si_pm4_cmd_add(pm4, CC1_UPDATE_SHADOW_ENABLES(1)); in si_init_cs_preamble_state()
5083 si_pm4_cmd_add(pm4, PKT3(PKT3_CLEAR_STATE, 0, 0)); in si_init_cs_preamble_state()
5084 si_pm4_cmd_add(pm4, 0); in si_init_cs_preamble_state()
5089 si_pm4_set_reg(pm4, R_028240_PA_SC_GENERIC_SCISSOR_TL, S_028240_WINDOW_OFFSET_DISABLE(1)); in si_init_cs_preamble_state()
5090 si_pm4_set_reg(pm4, R_028244_PA_SC_GENERIC_SCISSOR_BR, in si_init_cs_preamble_state()
5093 si_pm4_set_reg(pm4, R_028A18_VGT_HOS_MAX_TESS_LEVEL, fui(64)); in si_init_cs_preamble_state()
5095 si_pm4_set_reg(pm4, R_028A1C_VGT_HOS_MIN_TESS_LEVEL, fui(0)); in si_init_cs_preamble_state()
5098 si_pm4_set_reg(pm4, R_028230_PA_SC_EDGERULE, in si_init_cs_preamble_state()
5103 si_pm4_set_reg(pm4, R_028820_PA_CL_NANINF_CNTL, 0); in si_init_cs_preamble_state()
5104 si_pm4_set_reg(pm4, R_028AC0_DB_SRESULTS_COMPARE_STATE0, 0x0); in si_init_cs_preamble_state()
5105 si_pm4_set_reg(pm4, R_028AC4_DB_SRESULTS_COMPARE_STATE1, 0x0); in si_init_cs_preamble_state()
5106 si_pm4_set_reg(pm4, R_028AC8_DB_PRELOAD_CONTROL, 0x0); in si_init_cs_preamble_state()
5107 si_pm4_set_reg(pm4, R_02800C_DB_RENDER_OVERRIDE, 0); in si_init_cs_preamble_state()
5108 si_pm4_set_reg(pm4, R_028A5C_VGT_GS_PER_VS, 0x2); in si_init_cs_preamble_state()
5109 si_pm4_set_reg(pm4, R_028A8C_VGT_PRIMITIVEID_RESET, 0x0); in si_init_cs_preamble_state()
5110 si_pm4_set_reg(pm4, R_028B98_VGT_STRMOUT_BUFFER_CONFIG, 0x0); in si_init_cs_preamble_state()
5111 si_pm4_set_reg(pm4, R_028AB8_VGT_VTX_CNT_EN, 0x0); in si_init_cs_preamble_state()
5114 si_pm4_set_reg(pm4, R_028080_TA_BC_BASE_ADDR, border_color_va >> 8); in si_init_cs_preamble_state()
5116 si_pm4_set_reg(pm4, R_028084_TA_BC_BASE_ADDR_HI, S_028084_ADDRESS(border_color_va >> 40)); in si_init_cs_preamble_state()
5119 si_pm4_set_reg(pm4, R_008A14_PA_CL_ENHANCE, in si_init_cs_preamble_state()
5124 si_pm4_set_reg(pm4, R_028C58_VGT_VERTEX_REUSE_BLOCK_CNTL, 14); in si_init_cs_preamble_state()
5125 si_pm4_set_reg(pm4, R_028C5C_VGT_OUT_DEALLOC_CNTL, 16); in si_init_cs_preamble_state()
5130 si_pm4_set_reg(pm4, R_028B28_VGT_STRMOUT_DRAW_OPAQUE_OFFSET, 0); in si_init_cs_preamble_state()
5131 si_pm4_set_reg(pm4, R_028204_PA_SC_WINDOW_SCISSOR_TL, S_028204_WINDOW_OFFSET_DISABLE(1)); in si_init_cs_preamble_state()
5132 si_pm4_set_reg(pm4, R_028030_PA_SC_SCREEN_SCISSOR_TL, 0); in si_init_cs_preamble_state()
5133 si_pm4_set_reg(pm4, R_028034_PA_SC_SCREEN_SCISSOR_BR, in si_init_cs_preamble_state()
5196 si_pm4_set_reg(pm4, R_00B118_SPI_SHADER_PGM_RSRC3_VS, in si_init_cs_preamble_state()
5198 si_pm4_set_reg(pm4, R_00B11C_SPI_SHADER_LATE_ALLOC_VS, S_00B11C_LIMIT(late_alloc_wave64)); in si_init_cs_preamble_state()
5199 si_pm4_set_reg(pm4, R_00B21C_SPI_SHADER_PGM_RSRC3_GS, in si_init_cs_preamble_state()
5201 si_pm4_set_reg(pm4, R_00B01C_SPI_SHADER_PGM_RSRC3_PS, in si_init_cs_preamble_state()
5206 si_set_raster_config(sctx, pm4); in si_init_cs_preamble_state()
5209 si_pm4_set_reg(pm4, R_028A54_VGT_GS_PER_ES, SI_GS_PER_ES); in si_init_cs_preamble_state()
5210 si_pm4_set_reg(pm4, R_028A58_VGT_ES_PER_GS, 0x40); in si_init_cs_preamble_state()
5216 si_pm4_set_reg(pm4, R_028400_VGT_MAX_VTX_INDX, ~0); in si_init_cs_preamble_state()
5217 si_pm4_set_reg(pm4, R_028404_VGT_MIN_VTX_INDX, 0); in si_init_cs_preamble_state()
5218 si_pm4_set_reg(pm4, R_028408_VGT_INDX_OFFSET, 0); in si_init_cs_preamble_state()
5222 si_pm4_set_reg(pm4, R_00B51C_SPI_SHADER_PGM_RSRC3_LS, in si_init_cs_preamble_state()
5224 si_pm4_set_reg(pm4, R_00B41C_SPI_SHADER_PGM_RSRC3_HS, S_00B41C_WAVE_LIMIT(0x3F)); in si_init_cs_preamble_state()
5225 si_pm4_set_reg(pm4, R_00B31C_SPI_SHADER_PGM_RSRC3_ES, in si_init_cs_preamble_state()
5232 si_pm4_set_reg(pm4, R_028A44_VGT_GS_ONCHIP_CNTL, in si_init_cs_preamble_state()
5248 si_pm4_set_reg(pm4, R_028B50_VGT_TESS_DISTRIBUTION, vgt_tess_distribution); in si_init_cs_preamble_state()
5252 si_pm4_set_reg(pm4, R_028AA0_VGT_INSTANCE_STEP_RATE_0, 1); in si_init_cs_preamble_state()
5256 si_pm4_set_reg(pm4, R_030920_VGT_MAX_VTX_INDX, ~0); in si_init_cs_preamble_state()
5257 si_pm4_set_reg(pm4, R_030924_VGT_MIN_VTX_INDX, 0); in si_init_cs_preamble_state()
5258 si_pm4_set_reg(pm4, R_030928_VGT_INDX_OFFSET, 0); in si_init_cs_preamble_state()
5262 si_pm4_set_reg(pm4, R_00B41C_SPI_SHADER_PGM_RSRC3_HS, in si_init_cs_preamble_state()
5265 si_pm4_set_reg(pm4, R_028B50_VGT_TESS_DISTRIBUTION, in si_init_cs_preamble_state()
5268 si_pm4_set_reg(pm4, R_028C48_PA_SC_BINNER_CNTL_1, in si_init_cs_preamble_state()
5271 si_pm4_set_reg(pm4, R_028C4C_PA_SC_CONSERVATIVE_RASTERIZATION_CNTL, in si_init_cs_preamble_state()
5274 si_pm4_set_reg(pm4, R_030968_VGT_INSTANCE_BASE_ID, 0); in si_init_cs_preamble_state()
5275 si_pm4_set_reg(pm4, R_0301EC_CP_COHER_START_DELAY, in si_init_cs_preamble_state()
5281 si_pm4_set_reg(pm4, R_00B004_SPI_SHADER_PGM_RSRC4_PS, S_00B004_CU_EN(cu_mask_ps >> 16)); in si_init_cs_preamble_state()
5282 si_pm4_set_reg(pm4, R_00B104_SPI_SHADER_PGM_RSRC4_VS, S_00B104_CU_EN(0xffff)); in si_init_cs_preamble_state()
5283 si_pm4_set_reg(pm4, R_00B404_SPI_SHADER_PGM_RSRC4_HS, S_00B404_CU_EN(0xffff)); in si_init_cs_preamble_state()
5285 si_pm4_set_reg(pm4, R_00B0C8_SPI_SHADER_USER_ACCUM_PS_0, 0); in si_init_cs_preamble_state()
5286 si_pm4_set_reg(pm4, R_00B0CC_SPI_SHADER_USER_ACCUM_PS_1, 0); in si_init_cs_preamble_state()
5287 si_pm4_set_reg(pm4, R_00B0D0_SPI_SHADER_USER_ACCUM_PS_2, 0); in si_init_cs_preamble_state()
5288 si_pm4_set_reg(pm4, R_00B0D4_SPI_SHADER_USER_ACCUM_PS_3, 0); in si_init_cs_preamble_state()
5289 si_pm4_set_reg(pm4, R_00B1C8_SPI_SHADER_USER_ACCUM_VS_0, 0); in si_init_cs_preamble_state()
5290 si_pm4_set_reg(pm4, R_00B1CC_SPI_SHADER_USER_ACCUM_VS_1, 0); in si_init_cs_preamble_state()
5291 si_pm4_set_reg(pm4, R_00B1D0_SPI_SHADER_USER_ACCUM_VS_2, 0); in si_init_cs_preamble_state()
5292 si_pm4_set_reg(pm4, R_00B1D4_SPI_SHADER_USER_ACCUM_VS_3, 0); in si_init_cs_preamble_state()
5293 si_pm4_set_reg(pm4, R_00B2C8_SPI_SHADER_USER_ACCUM_ESGS_0, 0); in si_init_cs_preamble_state()
5294 si_pm4_set_reg(pm4, R_00B2CC_SPI_SHADER_USER_ACCUM_ESGS_1, 0); in si_init_cs_preamble_state()
5295 si_pm4_set_reg(pm4, R_00B2D0_SPI_SHADER_USER_ACCUM_ESGS_2, 0); in si_init_cs_preamble_state()
5296 si_pm4_set_reg(pm4, R_00B2D4_SPI_SHADER_USER_ACCUM_ESGS_3, 0); in si_init_cs_preamble_state()
5297 si_pm4_set_reg(pm4, R_00B4C8_SPI_SHADER_USER_ACCUM_LSHS_0, 0); in si_init_cs_preamble_state()
5298 si_pm4_set_reg(pm4, R_00B4CC_SPI_SHADER_USER_ACCUM_LSHS_1, 0); in si_init_cs_preamble_state()
5299 si_pm4_set_reg(pm4, R_00B4D0_SPI_SHADER_USER_ACCUM_LSHS_2, 0); in si_init_cs_preamble_state()
5300 si_pm4_set_reg(pm4, R_00B4D4_SPI_SHADER_USER_ACCUM_LSHS_3, 0); in si_init_cs_preamble_state()
5302 si_pm4_set_reg(pm4, R_00B0C0_SPI_SHADER_REQ_CTRL_PS, in si_init_cs_preamble_state()
5305 si_pm4_set_reg(pm4, R_00B1C0_SPI_SHADER_REQ_CTRL_VS, 0); in si_init_cs_preamble_state()
5317 si_pm4_set_reg(pm4, R_02807C_DB_RMI_L2_CACHE_CONTROL, in si_init_cs_preamble_state()
5325 si_pm4_set_reg(pm4, R_028410_CB_RMI_GL2_CACHE_CONTROL, in si_init_cs_preamble_state()
5334 si_pm4_set_reg(pm4, R_028428_CB_COVERAGE_OUT_CONTROL, 0); in si_init_cs_preamble_state()
5335 si_pm4_set_reg(pm4, R_028A98_VGT_DRAW_PAYLOAD_CNTL, 0); in si_init_cs_preamble_state()
5346 si_pm4_set_reg(pm4, R_028C50_PA_SC_NGG_MODE_CNTL, S_028C50_MAX_DEALLOCS_IN_WAVE(512)); in si_init_cs_preamble_state()
5348 si_pm4_set_reg(pm4, R_028C58_VGT_VERTEX_REUSE_BLOCK_CNTL, 14); in si_init_cs_preamble_state()
5351 si_pm4_set_reg(pm4, R_02835C_PA_SC_TILE_STEERING_OVERRIDE, in si_init_cs_preamble_state()
5356 si_pm4_set_reg(pm4, R_030964_GE_MAX_VTX_INDX, ~0); in si_init_cs_preamble_state()
5357 si_pm4_set_reg(pm4, R_030924_GE_MIN_VTX_INDX, 0); in si_init_cs_preamble_state()
5358 si_pm4_set_reg(pm4, R_030928_GE_INDX_OFFSET, 0); in si_init_cs_preamble_state()
5359 si_pm4_set_reg(pm4, R_03097C_GE_STEREO_CNTL, 0); in si_init_cs_preamble_state()
5360 si_pm4_set_reg(pm4, R_030988_GE_USER_VGPR_EN, 0); in si_init_cs_preamble_state()
5364 si_pm4_set_reg(pm4, R_028750_SX_PS_DOWNCONVERT_CONTROL, 0xff); in si_init_cs_preamble_state()
5366 si_pm4_set_reg(pm4, R_028848_PA_CL_VRS_CNTL, in si_init_cs_preamble_state()
5370 sctx->cs_preamble_state = pm4; in si_init_cs_preamble_state()