195          anv_batch_emit(&batch, GENX(MI_BATCH_BUFFER_END), bbe);  in genX()
589    anv_batch_emit(&cmd_buffer->batch, GENX(PIPE_CONTROL), pc) {  in emit_ps_depth_count()
616    anv_batch_emit(&cmd_buffer->batch, GENX(PIPE_CONTROL), pc) {  in emit_query_pc_availability()
778    GENX(IA_VERTICES_COUNT_num),
779    GENX(IA_PRIMITIVES_COUNT_num),
780    GENX(VS_INVOCATION_COUNT_num),
781    GENX(GS_INVOCATION_COUNT_num),
782    GENX(GS_PRIMITIVES_COUNT_num),
783    GENX(CL_INVOCATION_COUNT_num),
784    GENX(CL_PRIMITIVES_COUNT_num),
785    GENX(PS_INVOCATION_COUNT_num),
786    GENX(HS_INVOCATION_COUNT_num),
787    GENX(DS_INVOCATION_COUNT_num),
788    GENX(CS_INVOCATION_COUNT_num),
810                 gen_mi_reg64(GENX(SO_NUM_PRIMS_WRITTEN0_num) + stream * 8));  in emit_xfb_query()
812                 gen_mi_reg64(GENX(SO_PRIM_STORAGE_NEEDED0_num) + stream * 8));  in emit_xfb_query()
845       anv_batch_emit(&cmd_buffer->batch, GENX(PIPE_CONTROL), pc) {  in genX()
861       anv_batch_emit(&cmd_buffer->batch, GENX(PIPE_CONTROL), pc) {  in genX()
870       anv_batch_emit(&cmd_buffer->batch, GENX(PIPE_CONTROL), pc) {  in genX()
893                          GENX(MI_REPORT_PERF_COUNT_length),  in genX()
894                          GENX(MI_REPORT_PERF_COUNT),  in genX()
898                                     GENX(MI_REPORT_PERF_COUNT_MemoryAddress_start) / 8);  in genX()
904       anv_batch_emit(&cmd_buffer->batch, GENX(PIPE_CONTROL), pc) {  in genX()
908       anv_batch_emit(&cmd_buffer->batch, GENX(MI_REPORT_PERF_COUNT), rpc) {  in genX()
916                    gen_mi_reg32(GENX(RPSTAT1_num)));  in genX()
921                    gen_mi_reg32(GENX(RPSTAT0_num)));  in genX()
926                    gen_mi_reg64(GENX(PERFCNT1_num)));  in genX()
929                    gen_mi_reg64(GENX(PERFCNT2_num)));  in genX()
968       anv_batch_emit(&cmd_buffer->batch, GENX(PIPE_CONTROL), pc) {  in genX()
986       anv_batch_emit(&cmd_buffer->batch, GENX(PIPE_CONTROL), pc) {  in genX()
997       anv_batch_emit(&cmd_buffer->batch, GENX(PIPE_CONTROL), pc) {  in genX()
1030                          GENX(MI_REPORT_PERF_COUNT_length),  in genX()
1031                          GENX(MI_REPORT_PERF_COUNT),  in genX()
1035                                     GENX(MI_REPORT_PERF_COUNT_MemoryAddress_start) / 8);  in genX()
1039                          GENX(MI_STORE_DATA_IMM_length),  in genX()
1040                          GENX(MI_STORE_DATA_IMM),  in genX()
1044                                     GENX(MI_STORE_DATA_IMM_Address_start) / 8);  in genX()
1050       anv_batch_emit(&cmd_buffer->batch, GENX(PIPE_CONTROL), pc) {  in genX()
1059                    gen_mi_reg64(GENX(PERFCNT1_num)));  in genX()
1061                    gen_mi_reg64(GENX(PERFCNT2_num)));  in genX()
1067                    gen_mi_reg32(GENX(RPSTAT1_num)));  in genX()
1072                    gen_mi_reg32(GENX(RPSTAT0_num)));  in genX()
1077       anv_batch_emit(&cmd_buffer->batch, GENX(MI_REPORT_PERF_COUNT), rpc) {  in genX()
1134       anv_batch_emit(&cmd_buffer->batch, GENX(PIPE_CONTROL), pc) {  in genX()
1187    anv_batch_emit(&cmd_buffer->batch, GENX(MI_PREDICATE), mip) {  in gpu_write_query_result_cond()