583 emit_ps_depth_count(struct anv_cmd_buffer *cmd_buffer,  in emit_ps_depth_count()  argument
586    cmd_buffer->state.pending_pipe_bits |= ANV_PIPE_POST_SYNC_BIT;  in emit_ps_depth_count()
587    genX(cmd_buffer_apply_pipe_flushes)(cmd_buffer);  in emit_ps_depth_count()
589    anv_batch_emit(&cmd_buffer->batch, GENX(PIPE_CONTROL), pc) {  in emit_ps_depth_count()
595       if (GEN_GEN == 9 && cmd_buffer->device->info.gt == 4)  in emit_ps_depth_count()
609 emit_query_pc_availability(struct anv_cmd_buffer *cmd_buffer,  in emit_query_pc_availability()  argument
613    cmd_buffer->state.pending_pipe_bits |= ANV_PIPE_POST_SYNC_BIT;  in emit_query_pc_availability()
614    genX(cmd_buffer_apply_pipe_flushes)(cmd_buffer);  in emit_query_pc_availability()
616    anv_batch_emit(&cmd_buffer->batch, GENX(PIPE_CONTROL), pc) {  in emit_query_pc_availability()
629 emit_zero_queries(struct anv_cmd_buffer *cmd_buffer,  in emit_zero_queries()  argument
646             emit_query_pc_availability(cmd_buffer,  in emit_zero_queries()
650          emit_query_pc_availability(cmd_buffer, slot_addr, true);  in emit_zero_queries()
701    ANV_FROM_HANDLE(anv_cmd_buffer, cmd_buffer, commandBuffer);  in genX()
708          emit_query_pc_availability(cmd_buffer,  in genX()
717       gen_mi_builder_init(&b, &cmd_buffer->batch);  in genX()
727       gen_mi_builder_init(&b, &cmd_buffer->batch);  in genX()
743       gen_mi_builder_init(&b, &cmd_buffer->batch);  in genX()
831    ANV_FROM_HANDLE(anv_cmd_buffer, cmd_buffer, commandBuffer);  in genX()
836    gen_mi_builder_init(&b, &cmd_buffer->batch);  in genX()
840       emit_ps_depth_count(cmd_buffer, anv_address_add(query_addr, 8));  in genX()
845       anv_batch_emit(&cmd_buffer->batch, GENX(PIPE_CONTROL), pc) {  in genX()
861       anv_batch_emit(&cmd_buffer->batch, GENX(PIPE_CONTROL), pc) {  in genX()
870       anv_batch_emit(&cmd_buffer->batch, GENX(PIPE_CONTROL), pc) {  in genX()
874       cmd_buffer->perf_query_pool = pool;  in genX()
892          anv_batch_emitn(&cmd_buffer->batch,  in genX()
904       anv_batch_emit(&cmd_buffer->batch, GENX(PIPE_CONTROL), pc) {  in genX()
908       anv_batch_emit(&cmd_buffer->batch, GENX(MI_REPORT_PERF_COUNT), rpc) {  in genX()
953    ANV_FROM_HANDLE(anv_cmd_buffer, cmd_buffer, commandBuffer);  in genX()
958    gen_mi_builder_init(&b, &cmd_buffer->batch);  in genX()
962       emit_ps_depth_count(cmd_buffer, anv_address_add(query_addr, 16));  in genX()
963       emit_query_pc_availability(cmd_buffer, query_addr, true);  in genX()
968       anv_batch_emit(&cmd_buffer->batch, GENX(PIPE_CONTROL), pc) {  in genX()
986       anv_batch_emit(&cmd_buffer->batch, GENX(PIPE_CONTROL), pc) {  in genX()
997       anv_batch_emit(&cmd_buffer->batch, GENX(PIPE_CONTROL), pc) {  in genX()
1029          anv_batch_emitn(&cmd_buffer->batch,  in genX()
1038          anv_batch_emitn(&cmd_buffer->batch,  in genX()
1050       anv_batch_emit(&cmd_buffer->batch, GENX(PIPE_CONTROL), pc) {  in genX()
1056                    gen_mi_imm(cmd_buffer->intel_perf_marker));  in genX()
1077       anv_batch_emit(&cmd_buffer->batch, GENX(MI_REPORT_PERF_COUNT), rpc) {  in genX()
1098    if (cmd_buffer->state.subpass && cmd_buffer->state.subpass->view_mask) {  in genX()
1100          util_bitcount(cmd_buffer->state.subpass->view_mask);  in genX()
1102          emit_zero_queries(cmd_buffer, &b, pool, query + 1, num_queries - 1);  in genX()
1114    ANV_FROM_HANDLE(anv_cmd_buffer, cmd_buffer, commandBuffer);  in genX()
1121    gen_mi_builder_init(&b, &cmd_buffer->batch);  in genX()
1131       cmd_buffer->state.pending_pipe_bits |= ANV_PIPE_POST_SYNC_BIT;  in genX()
1132       genX(cmd_buffer_apply_pipe_flushes)(cmd_buffer);  in genX()
1134       anv_batch_emit(&cmd_buffer->batch, GENX(PIPE_CONTROL), pc) {  in genX()
1139          if (GEN_GEN == 9 && cmd_buffer->device->info.gt == 4)  in genX()
1145    emit_query_pc_availability(cmd_buffer, query_addr, true);  in genX()
1155    if (cmd_buffer->state.subpass && cmd_buffer->state.subpass->view_mask) {  in genX()
1157          util_bitcount(cmd_buffer->state.subpass->view_mask);  in genX()
1159          emit_zero_queries(cmd_buffer, &b, pool, query + 1, num_queries - 1);  in genX()
1176 gpu_write_query_result_cond(struct anv_cmd_buffer *cmd_buffer,  in gpu_write_query_result_cond()  argument
1187    anv_batch_emit(&cmd_buffer->batch, GENX(MI_PREDICATE), mip) {  in gpu_write_query_result_cond()
1237    ANV_FROM_HANDLE(anv_cmd_buffer, cmd_buffer, commandBuffer);  in genX()
1242    gen_mi_builder_init(&b, &cmd_buffer->batch);  in genX()
1249    if (cmd_buffer->state.pending_pipe_bits & ANV_PIPE_RENDER_TARGET_BUFFER_WRITES) {  in genX()
1250       cmd_buffer->state.pending_pipe_bits |=  in genX()
1255        (cmd_buffer->state.pending_pipe_bits & ANV_PIPE_FLUSH_BITS) ||  in genX()
1269       cmd_buffer->state.pending_pipe_bits |= ANV_PIPE_CS_STALL_BIT;  in genX()
1270       genX(cmd_buffer_apply_pipe_flushes)(cmd_buffer);  in genX()
1286          gpu_write_query_result_cond(cmd_buffer, &b, query_addr, dest_addr,  in genX()
1289             gpu_write_query_result_cond(cmd_buffer, &b, query_addr, dest_addr,  in genX()
1307             if ((cmd_buffer->device->info.gen == 8 ||  in genX()
1308                  cmd_buffer->device->info.is_haswell) &&  in genX()