51    unsigned size = GENX(SLICE_HASH_TABLE_length) * 4;  in genX()
55    struct GENX(SLICE_HASH_TABLE) table0 = {  in genX()
76    struct GENX(SLICE_HASH_TABLE) table1 = {  in genX()
97    const struct GENX(SLICE_HASH_TABLE) *table =  in genX()
99    GENX(SLICE_HASH_TABLE_pack)(NULL, device->slice_hash.map, table);  in genX()
101    anv_batch_emit(batch, GENX(3DSTATE_SLICE_TABLE_STATE_POINTERS), ptr) {  in genX()
106    anv_batch_emit(batch, GENX(3DSTATE_3D_MODE), mode) {  in genX()
121    anv_batch_emit(&batch, GENX(PIPELINE_SELECT), ps) {  in genX()
131    anv_pack_struct(&cache_mode_1, GENX(CACHE_MODE_1),  in genX()
139    anv_batch_emit(&batch, GENX(MI_LOAD_REGISTER_IMM), lri) {  in genX()
140       lri.RegisterOffset = GENX(CACHE_MODE_1_num);  in genX()
145    anv_batch_emit(&batch, GENX(3DSTATE_AA_LINE_PARAMETERS), aa);  in genX()
147    anv_batch_emit(&batch, GENX(3DSTATE_DRAWING_RECTANGLE), rect) {  in genX()
157    anv_batch_emit(&batch, GENX(3DSTATE_WM_CHROMAKEY), ck);  in genX()
162    anv_batch_emit(&batch, GENX(3DSTATE_SAMPLE_PATTERN), sp) {  in genX()
180    anv_batch_emit(&batch, GENX(3DSTATE_WM_HZ_OP), hzp);  in genX()
190    anv_pack_struct(&sampler_mode, GENX(SAMPLER_MODE),  in genX()
194     anv_batch_emit(&batch, GENX(MI_LOAD_REGISTER_IMM), lri) {  in genX()
195       lri.RegisterOffset = GENX(SAMPLER_MODE_num);  in genX()
203    anv_pack_struct(&half_slice_chicken7, GENX(HALF_SLICE_CHICKEN7),  in genX()
207     anv_batch_emit(&batch, GENX(MI_LOAD_REGISTER_IMM), lri) {  in genX()
208       lri.RegisterOffset = GENX(HALF_SLICE_CHICKEN7_num);  in genX()
213    anv_pack_struct(&tccntlreg, GENX(TCCNTLREG),  in genX()
219    anv_batch_emit(&batch, GENX(MI_LOAD_REGISTER_IMM), lri) {  in genX()
220       lri.RegisterOffset = GENX(TCCNTLREG_num);  in genX()
234                       GENX(CACHE_MODE_0),  in genX()
238       anv_batch_emit(&batch, GENX(MI_LOAD_REGISTER_IMM), lri) {  in genX()
239          lri.RegisterOffset = GENX(CACHE_MODE_0_num);  in genX()
251                    GENX(CS_CHICKEN1),  in genX()
255    anv_batch_emit(&batch, GENX(MI_LOAD_REGISTER_IMM), lri) {  in genX()
256       lri.RegisterOffset = GENX(CS_CHICKEN1_num);  in genX()
265       anv_batch_emit(&batch, GENX(MI_LOAD_REGISTER_IMM), lri) {  in genX()
266          lri.RegisterOffset = GENX(GFX_AUX_TABLE_BASE_ADDR_num);  in genX()
269       anv_batch_emit(&batch, GENX(MI_LOAD_REGISTER_IMM), lri) {  in genX()
270          lri.RegisterOffset = GENX(GFX_AUX_TABLE_BASE_ADDR_num) + 4;  in genX()
284       anv_pack_struct(&tmp_reg, GENX(CS_DEBUG_MODE2),  in genX()
287       anv_batch_emit(&batch, GENX(MI_LOAD_REGISTER_IMM), lri) {  in genX()
288          lri.RegisterOffset = GENX(CS_DEBUG_MODE2_num);  in genX()
292       anv_pack_struct(&tmp_reg, GENX(INSTPM),  in genX()
295       anv_batch_emit(&batch, GENX(MI_LOAD_REGISTER_IMM), lri) {  in genX()
296          lri.RegisterOffset = GENX(INSTPM_num);  in genX()
307       anv_pack_struct(&l3cr, GENX(L3ALLOC),  in genX()
309       anv_batch_emit(&batch, GENX(MI_LOAD_REGISTER_IMM), lri) {  in genX()
310          lri.RegisterOffset = GENX(L3ALLOC_num);  in genX()
316    anv_batch_emit(&batch, GENX(MI_BATCH_BUFFER_END), bbe);  in genX()
512       struct GENX(SAMPLER_STATE) sampler_state = {  in genX()
566       GENX(SAMPLER_STATE_pack)(NULL, sampler->state[p], &sampler_state);  in genX()
570                 sampler->state[p], GENX(SAMPLER_STATE_length) * 4);  in genX()