Lines Matching refs:OPC3
130 #define OPC3(opcode) ((opcode) << 19) macro
131 #define SET_FLAGS OPC3(0x10)
133 #define ADD (OPC1(0x2) | OPC3(0x00))
134 #define ADDC (OPC1(0x2) | OPC3(0x08))
135 #define AND (OPC1(0x2) | OPC3(0x01))
136 #define ANDN (OPC1(0x2) | OPC3(0x05))
138 #define FABSS (OPC1(0x2) | OPC3(0x34) | DOP(0x09))
139 #define FADDD (OPC1(0x2) | OPC3(0x34) | DOP(0x42))
140 #define FADDS (OPC1(0x2) | OPC3(0x34) | DOP(0x41))
141 #define FCMPD (OPC1(0x2) | OPC3(0x35) | DOP(0x52))
142 #define FCMPS (OPC1(0x2) | OPC3(0x35) | DOP(0x51))
143 #define FDIVD (OPC1(0x2) | OPC3(0x34) | DOP(0x4e))
144 #define FDIVS (OPC1(0x2) | OPC3(0x34) | DOP(0x4d))
145 #define FDTOI (OPC1(0x2) | OPC3(0x34) | DOP(0xd2))
146 #define FDTOS (OPC1(0x2) | OPC3(0x34) | DOP(0xc6))
147 #define FITOD (OPC1(0x2) | OPC3(0x34) | DOP(0xc8))
148 #define FITOS (OPC1(0x2) | OPC3(0x34) | DOP(0xc4))
149 #define FMOVS (OPC1(0x2) | OPC3(0x34) | DOP(0x01))
150 #define FMULD (OPC1(0x2) | OPC3(0x34) | DOP(0x4a))
151 #define FMULS (OPC1(0x2) | OPC3(0x34) | DOP(0x49))
152 #define FNEGS (OPC1(0x2) | OPC3(0x34) | DOP(0x05))
153 #define FSTOD (OPC1(0x2) | OPC3(0x34) | DOP(0xc9))
154 #define FSTOI (OPC1(0x2) | OPC3(0x34) | DOP(0xd1))
155 #define FSUBD (OPC1(0x2) | OPC3(0x34) | DOP(0x46))
156 #define FSUBS (OPC1(0x2) | OPC3(0x34) | DOP(0x45))
157 #define JMPL (OPC1(0x2) | OPC3(0x38))
158 #define LDD (OPC1(0x3) | OPC3(0x03))
159 #define LDUW (OPC1(0x3) | OPC3(0x00))
161 #define OR (OPC1(0x2) | OPC3(0x02))
162 #define ORN (OPC1(0x2) | OPC3(0x06))
163 #define RDY (OPC1(0x2) | OPC3(0x28) | S1A(0))
164 #define RESTORE (OPC1(0x2) | OPC3(0x3d))
165 #define SAVE (OPC1(0x2) | OPC3(0x3c))
167 #define SLL (OPC1(0x2) | OPC3(0x25))
168 #define SLLX (OPC1(0x2) | OPC3(0x25) | (1 << 12))
169 #define SRA (OPC1(0x2) | OPC3(0x27))
170 #define SRAX (OPC1(0x2) | OPC3(0x27) | (1 << 12))
171 #define SRL (OPC1(0x2) | OPC3(0x26))
172 #define SRLX (OPC1(0x2) | OPC3(0x26) | (1 << 12))
173 #define STDF (OPC1(0x3) | OPC3(0x27))
174 #define STF (OPC1(0x3) | OPC3(0x24))
175 #define STW (OPC1(0x3) | OPC3(0x04))
176 #define SUB (OPC1(0x2) | OPC3(0x04))
177 #define SUBC (OPC1(0x2) | OPC3(0x0c))
178 #define TA (OPC1(0x2) | OPC3(0x3a) | (8 << 25))
179 #define WRY (OPC1(0x2) | OPC3(0x30) | DA(0))
180 #define XOR (OPC1(0x2) | OPC3(0x03))
181 #define XNOR (OPC1(0x2) | OPC3(0x07))
191 #define SDIV (OPC1(0x2) | OPC3(0x0f))
192 #define SMUL (OPC1(0x2) | OPC3(0x0b))
193 #define UDIV (OPC1(0x2) | OPC3(0x0e))
194 #define UMUL (OPC1(0x2) | OPC3(0x0a))
567 /* u w s */ ARCH_32_64(OPC1(3) | OPC3(0x04) /* stw */, OPC1(3) | OPC3(0x0e) /* stx */),
568 /* u w l */ ARCH_32_64(OPC1(3) | OPC3(0x00) /* lduw */, OPC1(3) | OPC3(0x0b) /* ldx */),
569 /* u b s */ OPC1(3) | OPC3(0x05) /* stb */,
570 /* u b l */ OPC1(3) | OPC3(0x01) /* ldub */,
571 /* u h s */ OPC1(3) | OPC3(0x06) /* sth */,
572 /* u h l */ OPC1(3) | OPC3(0x02) /* lduh */,
573 /* u i s */ OPC1(3) | OPC3(0x04) /* stw */,
574 /* u i l */ OPC1(3) | OPC3(0x00) /* lduw */,
576 /* s w s */ ARCH_32_64(OPC1(3) | OPC3(0x04) /* stw */, OPC1(3) | OPC3(0x0e) /* stx */),
577 /* s w l */ ARCH_32_64(OPC1(3) | OPC3(0x00) /* lduw */, OPC1(3) | OPC3(0x0b) /* ldx */),
578 /* s b s */ OPC1(3) | OPC3(0x05) /* stb */,
579 /* s b l */ OPC1(3) | OPC3(0x09) /* ldsb */,
580 /* s h s */ OPC1(3) | OPC3(0x06) /* sth */,
581 /* s h l */ OPC1(3) | OPC3(0x0a) /* ldsh */,
582 /* s i s */ OPC1(3) | OPC3(0x04) /* stw */,
583 /* s i l */ ARCH_32_64(OPC1(3) | OPC3(0x00) /* lduw */, OPC1(3) | OPC3(0x08) /* ldsw */),
585 /* d s */ OPC1(3) | OPC3(0x27),
586 /* d l */ OPC1(3) | OPC3(0x23),
587 /* s s */ OPC1(3) | OPC3(0x24),
588 /* s l */ OPC1(3) | OPC3(0x20),