Lines Matching refs:Cond
143 IValueT encodeCondition(CondARM32::Cond Cond) { in encodeCondition() argument
144 return static_cast<IValueT>(Cond); in encodeCondition()
797 void AssemblerARM32::emitType01(CondARM32::Cond Cond, IValueT InstType, in emitType01() argument
809 assert(CondARM32::isDefined(Cond)); in emitType01()
810 const IValueT Encoding = (encodeCondition(Cond) << kConditionShift) | in emitType01()
817 void AssemblerARM32::emitType01(CondARM32::Cond Cond, IValueT Opcode, in emitType01() argument
823 emitType01(Cond, Opcode, Rd, Rn, OpSrc1, SetFlags, RuleChecks, InstName); in emitType01()
826 void AssemblerARM32::emitType01(CondARM32::Cond Cond, IValueT Opcode, in emitType01() argument
845 emitType01(Cond, kInstTypeDataRegister, Opcode, SetFlags, Rn, Rd, Src1Value, in emitType01()
851 emitType01(Cond, kInstTypeDataRegister, Opcode, SetFlags, Rn, Rd, Src1Value, in emitType01()
871 emitType01(Cond, kInstTypeDataImmediate, Opcode, SetFlags, Rn, Rd, in emitType01()
882 emitType01(Cond, kInstTypeDataRegShift, Opcode, SetFlags, Rn, Rd, Src1Value, in emitType01()
889 void AssemblerARM32::emitType05(CondARM32::Cond Cond, IOffsetT Offset, in emitType05() argument
894 assert(CondARM32::isDefined(Cond)); in emitType05()
895 IValueT Encoding = static_cast<int32_t>(Cond) << kConditionShift | in emitType05()
901 void AssemblerARM32::emitBranch(Label *L, CondARM32::Cond Cond, bool Link) { in emitBranch() argument
905 emitType05(Cond, Dest, Link); in emitBranch()
910 emitType05(Cond, L->getEncodedPosition(), Link); in emitBranch()
914 void AssemblerARM32::emitCompareOp(CondARM32::Cond Cond, IValueT Opcode, in emitCompareOp() argument
933 emitType01(Cond, Opcode, Rd, Rn, OpSrc1, SetFlags, NoChecks, InstName); in emitCompareOp()
936 void AssemblerARM32::emitMemOp(CondARM32::Cond Cond, IValueT InstType, in emitMemOp() argument
940 assert(CondARM32::isDefined(Cond)); in emitMemOp()
941 const IValueT Encoding = (encodeCondition(Cond) << kConditionShift) | in emitMemOp()
947 void AssemblerARM32::emitMemOp(CondARM32::Cond Cond, bool IsLoad, bool IsByte, in emitMemOp() argument
975 emitMemOp(Cond, kInstTypeMemImmediate, IsLoad, IsByte, Rt, Address); in emitMemOp()
998 emitMemOp(Cond, kInstTypeRegisterShift, IsLoad, IsByte, Rt, Address); in emitMemOp()
1004 void AssemblerARM32::emitMemOpEnc3(CondARM32::Cond Cond, IValueT Opcode, in emitMemOpEnc3() argument
1023 assert(CondARM32::isDefined(Cond)); in emitMemOpEnc3()
1028 const IValueT Encoding = (encodeCondition(Cond) << kConditionShift) | in emitMemOpEnc3()
1042 assert(CondARM32::isDefined(Cond)); in emitMemOpEnc3()
1055 const IValueT Encoding = (encodeCondition(Cond) << kConditionShift) | in emitMemOpEnc3()
1063 void AssemblerARM32::emitDivOp(CondARM32::Cond Cond, IValueT Opcode, IValueT Rd, in emitDivOp() argument
1068 assert(CondARM32::isDefined(Cond)); in emitDivOp()
1069 const IValueT Encoding = Opcode | (encodeCondition(Cond) << kConditionShift) | in emitDivOp()
1076 void AssemblerARM32::emitInsertExtractInt(CondARM32::Cond Cond, in emitInsertExtractInt() argument
1084 assert(CondARM32::isDefined(Cond)); in emitInsertExtractInt()
1112 (encodeCondition(Cond) << kConditionShift) | in emitInsertExtractInt()
1120 void AssemblerARM32::emitMoveSS(CondARM32::Cond Cond, IValueT Sd, IValueT Sm) { in emitMoveSS() argument
1127 emitVFPsss(Cond, VmovssOpcode, Sd, S0, Sm); in emitMoveSS()
1130 void AssemblerARM32::emitMulOp(CondARM32::Cond Cond, IValueT Opcode, IValueT Rd, in emitMulOp() argument
1137 assert(CondARM32::isDefined(Cond)); in emitMulOp()
1138 IValueT Encoding = Opcode | (encodeCondition(Cond) << kConditionShift) | in emitMulOp()
1145 void AssemblerARM32::emitMultiMemOp(CondARM32::Cond Cond, in emitMultiMemOp() argument
1148 assert(CondARM32::isDefined(Cond)); in emitMultiMemOp()
1151 IValueT Encoding = (encodeCondition(Cond) << kConditionShift) | B27 | in emitMultiMemOp()
1157 void AssemblerARM32::emitSignExtend(CondARM32::Cond Cond, IValueT Opcode, in emitSignExtend() argument
1192 assert(CondARM32::isDefined(Cond)); in emitSignExtend()
1197 IValueT Encoding = (encodeCondition(Cond) << kConditionShift) | Opcode | in emitSignExtend()
1271 void AssemblerARM32::emitVFPddd(CondARM32::Cond Cond, IValueT Opcode, in emitVFPddd() argument
1276 assert(CondARM32::isDefined(Cond)); in emitVFPddd()
1279 Opcode | VFPOpcode | (encodeCondition(Cond) << kConditionShift) | in emitVFPddd()
1286 void AssemblerARM32::emitVFPddd(CondARM32::Cond Cond, IValueT Opcode, in emitVFPddd() argument
1292 emitVFPddd(Cond, Opcode, Dd, Dn, Dm); in emitVFPddd()
1295 void AssemblerARM32::emitVFPsss(CondARM32::Cond Cond, IValueT Opcode, in emitVFPsss() argument
1300 assert(CondARM32::isDefined(Cond)); in emitVFPsss()
1303 Opcode | VFPOpcode | (encodeCondition(Cond) << kConditionShift) | in emitVFPsss()
1310 void AssemblerARM32::emitVFPsss(CondARM32::Cond Cond, IValueT Opcode, in emitVFPsss() argument
1316 emitVFPsss(Cond, Opcode, Sd, Sn, Sm); in emitVFPsss()
1321 CondARM32::Cond Cond) { in adc() argument
1335 emitType01(Cond, AdcOpcode, OpRd, OpRn, OpSrc1, SetFlags, RdIsPcAndSetFlags, in adc()
1341 CondARM32::Cond Cond) { in add() argument
1359 emitType01(Cond, Add, OpRd, OpRn, OpSrc1, SetFlags, RdIsPcAndSetFlags, in add()
1365 CondARM32::Cond Cond) { in and_() argument
1379 emitType01(Cond, And, OpRd, OpRn, OpSrc1, SetFlags, RdIsPcAndSetFlags, in and_()
1383 void AssemblerARM32::b(Label *L, CondARM32::Cond Cond) { in b() argument
1384 emitBranch(L, Cond, false); in b()
1399 CondARM32::Cond Cond) { in bic() argument
1413 emitType01(Cond, BicOpcode, OpRd, OpRn, OpSrc1, SetFlags, RdIsPcAndSetFlags, in bic()
1424 constexpr CondARM32::Cond Cond = CondARM32::AL; in bl() local
1427 emitType05(Cond, Immed, Link); in bl()
1439 constexpr CondARM32::Cond Cond = CondARM32::AL; in blx() local
1440 int32_t Encoding = (encodeCondition(Cond) << kConditionShift) | B24 | B21 | in blx()
1445 void AssemblerARM32::bx(RegARM32::GPRRegister Rm, CondARM32::Cond Cond) { in bx() argument
1450 assert(CondARM32::isDefined(Cond)); in bx()
1451 const IValueT Encoding = (encodeCondition(Cond) << kConditionShift) | B24 | in bx()
1458 CondARM32::Cond Cond) { in clz() argument
1472 assert(CondARM32::isDefined(Cond)); in clz()
1475 const IValueT Encoding = PredefinedBits | (Cond << kConditionShift) | in clz()
1481 CondARM32::Cond Cond) { in cmn() argument
1495 emitCompareOp(Cond, CmnOpcode, OpRn, OpSrc1, CmnName); in cmn()
1499 CondARM32::Cond Cond) { in cmp() argument
1513 emitCompareOp(Cond, CmpOpcode, OpRn, OpSrc1, CmpName); in cmp()
1531 CondARM32::Cond Cond) { in eor() argument
1545 emitType01(Cond, EorOpcode, OpRd, OpRn, OpSrc1, SetFlags, RdIsPcAndSetFlags, in eor()
1550 CondARM32::Cond Cond, const TargetInfo &TInfo) { in ldr() argument
1583 emitMemOp(Cond, IsLoad, IsByte, Rt, OpAddress, TInfo, LdrName); in ldr()
1596 emitMemOpEnc3(Cond, L | B7 | B5 | B4, Rt, OpAddress, TInfo, Ldrh); in ldr()
1615 emitMemOp(Cond, IsLoad, IsByte, Rt, OpAddress, TInfo, LdrName); in ldr()
1621 void AssemblerARM32::emitMemExOp(CondARM32::Cond Cond, Type Ty, bool IsLoad, in emitMemExOp() argument
1652 assert(CondARM32::isDefined(Cond)); in emitMemExOp()
1653 IValueT Encoding = (Cond << kConditionShift) | B24 | B23 | B11 | B10 | B9 | in emitMemExOp()
1661 CondARM32::Cond Cond, const TargetInfo &TInfo) { in ldrex() argument
1685 emitMemExOp(Cond, Ty, IsLoad, OpRt, Rm, OpAddress, TInfo, LdrexName); in ldrex()
1688 void AssemblerARM32::emitShift(const CondARM32::Cond Cond, in emitShift() argument
1709 emitType01(Cond, kInstTypeDataRegShift, ShiftOpcode, SetFlags, Rn, Rd, in emitShift()
1724 emitType01(Cond, kInstTypeDataRegShift, ShiftOpcode, SetFlags, Rn, Rd, in emitShift()
1733 CondARM32::Cond Cond) { in asr() argument
1735 emitShift(Cond, OperandARM32::ASR, OpRd, OpRm, OpSrc1, SetFlags, AsrName); in asr()
1740 CondARM32::Cond Cond) { in lsl() argument
1742 emitShift(Cond, OperandARM32::LSL, OpRd, OpRm, OpSrc1, SetFlags, LslName); in lsl()
1747 CondARM32::Cond Cond) { in lsr() argument
1749 emitShift(Cond, OperandARM32::LSR, OpRd, OpRm, OpSrc1, SetFlags, LsrName); in lsr()
1753 CondARM32::Cond Cond) { in mov() argument
1771 emitType01(Cond, MovOpcode, Rd, Rn, OpSrc, SetFlags, RdIsPcAndSetFlags, in mov()
1775 void AssemblerARM32::emitMovwt(CondARM32::Cond Cond, bool IsMovW, in emitMovwt() argument
1789 assert(CondARM32::isDefined(Cond)); in emitMovwt()
1792 const IValueT Encoding = encodeCondition(Cond) << kConditionShift | Opcode | in emitMovwt()
1799 CondARM32::Cond Cond) { in movw() argument
1807 emitMovwt(Cond, IsMovW, OpRd, OpSrc, MovwName); in movw()
1811 CondARM32::Cond Cond) { in movt() argument
1819 emitMovwt(Cond, IsMovW, OpRd, OpSrc, MovtName); in movt()
1823 CondARM32::Cond Cond) { in mvn() argument
1840 emitType01(Cond, MvnOpcode, Rd, Rn, OpSrc, SetFlags, RdIsPcAndSetFlags, in mvn()
1849 constexpr CondARM32::Cond Cond = CondARM32::AL; in nop() local
1850 const IValueT Encoding = (encodeCondition(Cond) << kConditionShift) | B25 | in nop()
1857 CondARM32::Cond Cond) { in sbc() argument
1871 emitType01(Cond, SbcOpcode, OpRd, OpRn, OpSrc1, SetFlags, RdIsPcAndSetFlags, in sbc()
1876 const Operand *OpSrc1, CondARM32::Cond Cond) { in sdiv() argument
1891 emitDivOp(Cond, SdivOpcode, Rd, Rn, Rm); in sdiv()
1895 CondARM32::Cond Cond, const TargetInfo &TInfo) { in str() argument
1920 emitMemOp(Cond, IsLoad, IsByte, Rt, OpAddress, TInfo, StrName); in str()
1933 emitMemOpEnc3(Cond, B7 | B5 | B4, Rt, OpAddress, TInfo, Strh); in str()
1948 emitMemOp(Cond, IsLoad, IsByte, Rt, OpAddress, TInfo, StrName); in str()
1955 const Operand *OpAddress, CondARM32::Cond Cond, in strex() argument
1985 emitMemExOp(Cond, Ty, !IsLoad, OpRd, Rt, OpAddress, TInfo, StrexName); in strex()
1990 CondARM32::Cond Cond) { in orr() argument
2004 emitType01(Cond, OrrOpcode, OpRd, OpRn, OpSrc1, SetFlags, RdIsPcAndSetFlags, in orr()
2008 void AssemblerARM32::pop(const Variable *OpRt, CondARM32::Cond Cond) { in pop() argument
2024 emitMemOp(Cond, kInstTypeMemImmediate, IsLoad, IsByte, Rt, Address); in pop()
2027 void AssemblerARM32::popList(const IValueT Registers, CondARM32::Cond Cond) { in popList() argument
2034 emitMultiMemOp(Cond, IA_W, IsLoad, RegARM32::Encoded_Reg_sp, Registers); in popList()
2037 void AssemblerARM32::push(const Operand *OpRt, CondARM32::Cond Cond) { in push() argument
2053 emitMemOp(Cond, kInstTypeMemImmediate, isLoad, isByte, Rt, Address); in push()
2056 void AssemblerARM32::pushList(const IValueT Registers, CondARM32::Cond Cond) { in pushList() argument
2063 emitMultiMemOp(Cond, DB_W, IsLoad, RegARM32::Encoded_Reg_sp, Registers); in pushList()
2068 CondARM32::Cond Cond) { in mla() argument
2086 emitMulOp(Cond, MlaOpcode, Ra, Rd, Rn, Rm, !SetFlags); in mla()
2091 CondARM32::Cond Cond) { in mls() argument
2104 emitMulOp(Cond, MlsOpcode, Ra, Rd, Rn, Rm, !SetFlags); in mls()
2109 CondARM32::Cond Cond) { in mul() argument
2124 emitMulOp(Cond, MulOpcode, RegARM32::Encoded_Reg_r0, Rd, Rn, Rm, SetFlags); in mul()
2127 void AssemblerARM32::emitRdRm(CondARM32::Cond Cond, IValueT Opcode, in emitRdRm() argument
2133 (Cond << kConditionShift) | Opcode | (Rd << kRdShift) | (Rm << kRmShift); in emitRdRm()
2138 CondARM32::Cond Cond) { in rbit() argument
2146 emitRdRm(Cond, RbitOpcode, OpRd, OpRm, RbitName); in rbit()
2150 CondARM32::Cond Cond) { in rev() argument
2158 emitRdRm(Cond, RevOpcode, OpRd, OpRm, RevName); in rev()
2163 CondARM32::Cond Cond) { in rsb() argument
2177 emitType01(Cond, RsbOpcode, OpRd, OpRn, OpSrc1, SetFlags, RdIsPcAndSetFlags, in rsb()
2183 CondARM32::Cond Cond) { in rsc() argument
2203 emitType01(Cond, RscOpcode, OpRd, OpRn, OpSrc1, SetFlags, RdIsPcAndSetFlags, in rsc()
2208 CondARM32::Cond Cond) { in sxt() argument
2211 emitSignExtend(Cond, SxtOpcode, OpRd, OpSrc0, SxtName); in sxt()
2216 CondARM32::Cond Cond) { in sub() argument
2234 emitType01(Cond, SubOpcode, OpRd, OpRn, OpSrc1, SetFlags, RdIsPcAndSetFlags, in sub()
2260 CondARM32::Cond Cond) { in tst() argument
2274 emitCompareOp(Cond, TstOpcode, OpRn, OpSrc1, TstName); in tst()
2278 const Operand *OpSrc1, CondARM32::Cond Cond) { in udiv() argument
2293 emitDivOp(Cond, UdivOpcode, Rd, Rn, Rm); in udiv()
2298 CondARM32::Cond Cond) { in umull() argument
2316 emitMulOp(Cond, UmullOpcode, RdLo, RdHi, Rn, Rm, SetFlags); in umull()
2320 CondARM32::Cond Cond) { in uxt() argument
2323 emitSignExtend(Cond, UxtOpcode, OpRd, OpSrc0, UxtName); in uxt()
2327 CondARM32::Cond Cond) { in vabss() argument
2337 emitVFPsss(Cond, VabssOpcode, Sd, S0, Sm); in vabss()
2341 CondARM32::Cond Cond) { in vabsd() argument
2351 emitVFPddd(Cond, VabsdOpcode, Dd, D0, Dm); in vabsd()
2373 const Operand *OpSm, CondARM32::Cond Cond) { in vadds() argument
2381 emitVFPsss(Cond, VaddsOpcode, OpSd, OpSn, OpSm, Vadds); in vadds()
2412 const Operand *OpDm, CondARM32::Cond Cond) { in vaddd() argument
2420 emitVFPddd(Cond, VadddOpcode, OpDd, OpDn, OpDm, Vaddd); in vaddd()
2544 CondARM32::Cond Cond) { in vcmpd() argument
2550 emitVFPddd(Cond, VcmpdOpcode, Dd, Dn, Dm); in vcmpd()
2553 void AssemblerARM32::vcmpdz(const Operand *OpDd, CondARM32::Cond Cond) { in vcmpdz() argument
2559 emitVFPddd(Cond, VcmpdzOpcode, Dd, Dn, Dm); in vcmpdz()
2563 CondARM32::Cond Cond) { in vcmps() argument
2569 emitVFPsss(Cond, VcmpsOpcode, Sd, Sn, Sm); in vcmps()
2572 void AssemblerARM32::vcmpsz(const Operand *OpSd, CondARM32::Cond Cond) { in vcmpsz() argument
2578 emitVFPsss(Cond, VcmpszOpcode, Sd, Sn, Sm); in vcmpsz()
2581 void AssemblerARM32::emitVFPsd(CondARM32::Cond Cond, IValueT Opcode, IValueT Sd, in emitVFPsd() argument
2585 assert(CondARM32::isDefined(Cond)); in emitVFPsd()
2588 Opcode | VFPOpcode | (encodeCondition(Cond) << kConditionShift) | in emitVFPsd()
2595 CondARM32::Cond Cond) { in vcvtdi() argument
2605 emitVFPds(Cond, VcvtdiOpcode, Dd, Sm); in vcvtdi()
2609 CondARM32::Cond Cond) { in vcvtdu() argument
2619 emitVFPds(Cond, VcvtduOpcode, Dd, Sm); in vcvtdu()
2623 CondARM32::Cond Cond) { in vcvtsd() argument
2629 emitVFPsd(Cond, VcvtsdOpcode, Sd, Dm); in vcvtsd()
2633 CondARM32::Cond Cond) { in vcvtis() argument
2644 emitVFPsss(Cond, VcvtisOpcode, Sd, S0, Sm); in vcvtis()
2648 CondARM32::Cond Cond) { in vcvtid() argument
2659 emitVFPsd(Cond, VcvtidOpcode, Sd, Dm); in vcvtid()
2663 CondARM32::Cond Cond) { in vcvtsi() argument
2674 emitVFPsss(Cond, VcvtsiOpcode, Sd, S0, Sm); in vcvtsi()
2678 CondARM32::Cond Cond) { in vcvtsu() argument
2689 emitVFPsss(Cond, VcvtsuOpcode, Sd, S0, Sm); in vcvtsu()
2693 CondARM32::Cond Cond) { in vcvtud() argument
2703 emitVFPsd(Cond, VcvtudOpcode, Sd, Dm); in vcvtud()
2707 CondARM32::Cond Cond) { in vcvtus() argument
2718 emitVFPsss(Cond, VcvtsiOpcode, Sd, S0, Sm); in vcvtus()
2765 void AssemblerARM32::emitVFPds(CondARM32::Cond Cond, IValueT Opcode, IValueT Dd, in emitVFPds() argument
2769 assert(CondARM32::isDefined(Cond)); in emitVFPds()
2772 Opcode | VFPOpcode | (encodeCondition(Cond) << kConditionShift) | in emitVFPds()
2779 CondARM32::Cond Cond) { in vcvtds() argument
2784 emitVFPds(Cond, VcvtdsOpcode, Dd, Sm); in vcvtds()
2788 const Operand *OpSm, CondARM32::Cond Cond) { in vdivs() argument
2796 emitVFPsss(Cond, VdivsOpcode, OpSd, OpSn, OpSm, Vdivs); in vdivs()
2800 const Operand *OpDm, CondARM32::Cond Cond) { in vdivd() argument
2808 emitVFPddd(Cond, VdivdOpcode, OpDd, OpDn, OpDm, Vdivd); in vdivd()
2823 (encodeCondition(CondARM32::Cond::kNone) << kConditionShift) | in veord()
2842 CondARM32::Cond Cond, const TargetInfo &TInfo) { in vldrd() argument
2850 assert(CondARM32::isDefined(Cond)); in vldrd()
2857 (encodeCondition(Cond) << kConditionShift) | in vldrd()
2864 CondARM32::Cond Cond, const TargetInfo &TInfo) { in vldrq() argument
2875 assert(CondARM32::isDefined(Cond)); in vldrq()
2882 (encodeCondition(Cond) << kConditionShift) | in vldrq()
2889 CondARM32::Cond Cond, const TargetInfo &TInfo) { in vldrs() argument
2897 assert(CondARM32::isDefined(Cond)); in vldrs()
2904 (encodeCondition(Cond) << kConditionShift) | in vldrs()
3059 CondARM32::Cond Cond) { in vmovd() argument
3071 emitVFPddd(Cond, OpcodePlusImm8, Dd, D0, D0); in vmovd()
3075 CondARM32::Cond Cond) { in vmovdd() argument
3085 emitVFPddd(Cond, VmovddOpcode, Dd, D0, Dm); in vmovdd()
3089 const Operand *OpRt2, CondARM32::Cond Cond) { in vmovdrr() argument
3105 assert(CondARM32::isDefined(Cond)); in vmovdrr()
3107 (encodeCondition(Cond) << kConditionShift) | (Rt2 << 16) | in vmovdrr()
3114 const Operand *OpRt, CondARM32::Cond Cond) { in vmovqir() argument
3119 emitInsertExtractInt(Cond, OpQn, Index, OpRt, !IsExtract, Vmovdr); in vmovqir()
3123 const Operand *OpSm, CondARM32::Cond Cond) { in vmovqis() argument
3128 emitMoveSS(Cond, Sd, Sm); in vmovqis()
3132 uint32_t Index, CondARM32::Cond Cond) { in vmovrqi() argument
3137 emitInsertExtractInt(Cond, OpQn, Index, OpRt, IsExtract, Vmovrd); in vmovrqi()
3141 const Operand *OpDm, CondARM32::Cond Cond) { in vmovrrd() argument
3157 assert(CondARM32::isDefined(Cond)); in vmovrrd()
3159 (encodeCondition(Cond) << kConditionShift) | (Rt2 << 16) | in vmovrrd()
3166 CondARM32::Cond Cond) { in vmovrs() argument
3176 assert(CondARM32::isDefined(Cond)); in vmovrs()
3177 IValueT Encoding = (encodeCondition(Cond) << kConditionShift) | B27 | B26 | in vmovrs()
3185 CondARM32::Cond Cond) { in vmovs() argument
3197 emitVFPsss(Cond, OpcodePlusImm8, Sd, S0, S0); in vmovs()
3201 CondARM32::Cond Cond) { in vmovss() argument
3205 emitMoveSS(Cond, Sd, Sm); in vmovss()
3209 uint32_t Index, CondARM32::Cond Cond) { in vmovsqi() argument
3215 emitMoveSS(Cond, Sd, Sm); in vmovsqi()
3219 CondARM32::Cond Cond) { in vmovsr() argument
3231 assert(CondARM32::isDefined(Cond)); in vmovsr()
3232 IValueT Encoding = (encodeCondition(Cond) << kConditionShift) | B27 | B26 | in vmovsr()
3239 const Operand *OpDm, CondARM32::Cond Cond) { in vmlad() argument
3247 emitVFPddd(Cond, VmladOpcode, OpDd, OpDn, OpDm, Vmlad); in vmlad()
3251 const Operand *OpSm, CondARM32::Cond Cond) { in vmlas() argument
3259 emitVFPsss(Cond, VmlasOpcode, OpSd, OpSn, OpSm, Vmlas); in vmlas()
3263 const Operand *OpDm, CondARM32::Cond Cond) { in vmlsd() argument
3271 emitVFPddd(Cond, VmladOpcode, OpDd, OpDn, OpDm, Vmlad); in vmlsd()
3275 const Operand *OpSm, CondARM32::Cond Cond) { in vmlss() argument
3283 emitVFPsss(Cond, VmlasOpcode, OpSd, OpSn, OpSm, Vmlas); in vmlss()
3286 void AssemblerARM32::vmrsAPSR_nzcv(CondARM32::Cond Cond) { in vmrsAPSR_nzcv() argument
3292 assert(CondARM32::isDefined(Cond)); in vmrsAPSR_nzcv()
3295 (encodeCondition(Cond) << kConditionShift); in vmrsAPSR_nzcv()
3300 const Operand *OpSm, CondARM32::Cond Cond) { in vmuls() argument
3308 emitVFPsss(Cond, VmulsOpcode, OpSd, OpSn, OpSm, Vmuls); in vmuls()
3312 const Operand *OpDm, CondARM32::Cond Cond) { in vmuld() argument
3320 emitVFPddd(Cond, VmuldOpcode, OpDd, OpDn, OpDm, Vmuld); in vmuld()
3686 CondARM32::Cond Cond, const TargetInfo &TInfo) { in vstrd() argument
3694 assert(CondARM32::isDefined(Cond)); in vstrd()
3701 (encodeCondition(Cond) << kConditionShift) | in vstrd()
3708 CondARM32::Cond Cond, const TargetInfo &TInfo) { in vstrq() argument
3719 assert(CondARM32::isDefined(Cond)); in vstrq()
3726 (encodeCondition(Cond) << kConditionShift) | in vstrq()
3733 CondARM32::Cond Cond, const TargetInfo &TInfo) { in vstrs() argument
3741 assert(CondARM32::isDefined(Cond)); in vstrs()
3748 B27 | B26 | B24 | B11 | B9 | (encodeCondition(Cond) << kConditionShift) | in vstrs()
3807 const Operand *OpSm, CondARM32::Cond Cond) { in vsubs() argument
3815 emitVFPsss(Cond, VsubsOpcode, OpSd, OpSn, OpSm, Vsubs); in vsubs()
3819 const Operand *OpDm, CondARM32::Cond Cond) { in vsubd() argument
3827 emitVFPddd(Cond, VsubdOpcode, OpDd, OpDn, OpDm, Vsubd); in vsubd()
3965 void AssemblerARM32::emitVStackOp(CondARM32::Cond Cond, IValueT Opcode, in emitVStackOp() argument
3975 assert(CondARM32::isDefined(Cond)); in emitVStackOp()
3976 const IValueT Encoding = Opcode | (Cond << kConditionShift) | DLastBit | in emitVStackOp()
3982 CondARM32::Cond Cond) { in vpop() argument
3993 emitVStackOp(Cond, VpopOpcode, OpBaseReg, NumConsecRegs); in vpop()
3997 CondARM32::Cond Cond) { in vpush() argument
4008 emitVStackOp(Cond, VpushOpcode, OpBaseReg, NumConsecRegs); in vpush()
4073 CondARM32::Cond Cond) { in vsqrtd() argument
4083 emitVFPddd(Cond, VsqrtdOpcode, Dd, D0, Dm); in vsqrtd()
4087 CondARM32::Cond Cond) { in vsqrts() argument
4097 emitVFPsss(Cond, VsqrtsOpcode, Sd, S0, Sm); in vsqrts()