Lines Matching refs:Dd
1203 void AssemblerARM32::emitSIMDBase(IValueT Opcode, IValueT Dd, IValueT Dn, in emitSIMDBase() argument
1207 (getYInRegYXXXX(Dd) << 22) | (getXXXXInRegYXXXX(Dn) << 16) | in emitSIMDBase()
1208 (getXXXXInRegYXXXX(Dd) << 12) | (IsFloatTy ? B10 : 0) | in emitSIMDBase()
1214 void AssemblerARM32::emitSIMD(IValueT Opcode, Type ElmtTy, IValueT Dd, in emitSIMD() argument
1219 emitSIMDBase(Opcode | (ElmtSize << ElmtShift), Dd, Dn, Dm, UseQRegs, in emitSIMD()
1272 IValueT Dd, IValueT Dn, IValueT Dm) { in emitVFPddd() argument
1273 assert(Dd < RegARM32::getNumDRegs()); in emitVFPddd()
1280 (getYInRegYXXXX(Dd) << 22) | (getXXXXInRegYXXXX(Dn) << 16) | in emitVFPddd()
1281 (getXXXXInRegYXXXX(Dd) << 12) | (getYInRegYXXXX(Dn) << 7) | in emitVFPddd()
1289 IValueT Dd = encodeDRegister(OpDd, "Dd", InstName); in emitVFPddd() local
1292 emitVFPddd(Cond, Opcode, Dd, Dn, Dm); in emitVFPddd()
2347 const IValueT Dd = encodeDRegister(OpDd, "Dd", Vabsd); in vabsd() local
2351 emitVFPddd(Cond, VabsdOpcode, Dd, D0, Dm); in vabsd()
2363 const IValueT Dd = mapQRegToDReg(encodeQRegister(OpQd, "Qd", Vabsq)); in vabsq() local
2369 emitSIMDBase(VabsqOpcode, Dd, Dn, Dm, UseQRegs, isFloatingType(ElmtTy)); in vabsq()
2546 IValueT Dd = encodeDRegister(OpDd, "Dd", Vcmpd); in vcmpd() local
2550 emitVFPddd(Cond, VcmpdOpcode, Dd, Dn, Dm); in vcmpd()
2555 IValueT Dd = encodeDRegister(OpDd, "Dd", Vcmpdz); in vcmpdz() local
2559 emitVFPddd(Cond, VcmpdzOpcode, Dd, Dn, Dm); in vcmpdz()
2602 IValueT Dd = encodeDRegister(OpDd, "Dd", Vcvtdi); in vcvtdi() local
2605 emitVFPds(Cond, VcvtdiOpcode, Dd, Sm); in vcvtdi()
2616 IValueT Dd = encodeDRegister(OpDd, "Dd", Vcvtdu); in vcvtdu() local
2619 emitVFPds(Cond, VcvtduOpcode, Dd, Sm); in vcvtdu()
2765 void AssemblerARM32::emitVFPds(CondARM32::Cond Cond, IValueT Opcode, IValueT Dd, in emitVFPds() argument
2767 assert(Dd < RegARM32::getNumDRegs()); in emitVFPds()
2773 (getYInRegYXXXX(Dd) << 22) | (getXXXXInRegYXXXX(Dd) << 12) | in emitVFPds()
2781 IValueT Dd = encodeDRegister(OpDd, "Dd", Vcvtds); in vcvtds() local
2784 emitVFPds(Cond, VcvtdsOpcode, Dd, Sm); in vcvtds()
2818 IValueT Dd = encodeDRegister(OpDd, "Dd", Veord); in veord() local
2824 (getYInRegYXXXX(Dd) << 22) | (getXXXXInRegYXXXX(Dn) << 16) | in veord()
2825 (getXXXXInRegYXXXX(Dd) << 12) | (getYInRegYXXXX(Dn) << 7) | in veord()
2849 IValueT Dd = encodeDRegister(OpDd, "Dd", Vldrd); in vldrd() local
2858 (getYInRegYXXXX(Dd) << 22) | in vldrd()
2859 (getXXXXInRegYXXXX(Dd) << 12) | Address; in vldrd()
2874 IValueT Dd = mapQRegToDReg(encodeQRegister(OpQd, "Qd", Vldrd)); in vldrq() local
2883 (getYInRegYXXXX(Dd) << 22) | in vldrq()
2884 (getXXXXInRegYXXXX(Dd) << 12) | Address; in vldrq()
2910 void AssemblerARM32::emitVMem1Op(IValueT Opcode, IValueT Dd, IValueT Rn, in emitVMem1Op() argument
2937 (getYInRegYXXXX(Dd) << 22) | (Rn << kRnShift) | in emitVMem1Op()
2938 (getXXXXInRegYXXXX(Dd) << kRdShift) | (NumDRegs << 8) | in emitVMem1Op()
2943 void AssemblerARM32::emitVMem1Op(IValueT Opcode, IValueT Dd, IValueT Rn, in emitVMem1Op() argument
2969 (getYInRegYXXXX(Dd) << 22) | (Rn << kRnShift) | in emitVMem1Op()
2970 (getXXXXInRegYXXXX(Dd) << kRdShift) | (EncodedElmtSize << 10) | in emitVMem1Op()
2985 const IValueT Dd = mapQRegToDReg(Qd); in vld1qr() local
2994 emitVMem1Op(Opcode, Dd, Rn, Rm, DRegListSize2, ElmtSize, Align, Vld1qr); in vld1qr()
3015 const IValueT Dd = mapQRegToDReg(Qd); in vld1() local
3024 emitVMem1Op(Opcode, Dd, Rn, Rm, ElmtSize, Align, Vld1qr); in vld1()
3033 const IValueT Dd = mapQRegToDReg(encodeQRegister(OpQd, "Qd", Vmovc)); in vmovqc() local
3050 (mask(Imm8, 7, 1) << 24) | (getYInRegYXXXX(Dd) << 22) | in vmovqc()
3051 (mask(Imm8, 4, 3) << 16) | (getXXXXInRegYXXXX(Dd) << 12) | (Cmode << 8) | in vmovqc()
3065 IValueT Dd = encodeSRegister(OpDd, "Dd", Vmovd); in vmovd() local
3071 emitVFPddd(Cond, OpcodePlusImm8, Dd, D0, D0); in vmovd()
3081 IValueT Dd = encodeSRegister(OpDd, "Dd", Vmovdd); in vmovdd() local
3085 emitVFPddd(Cond, VmovddOpcode, Dd, D0, Dm); in vmovdd()
3364 const IValueT Dd = mapQRegToDReg(Qd); in vmulh() local
3370 emitSIMDBase(VmullOpcode | (ElmtSize << ElmtShift), Dd, Dn, Dm, UseQRegs, in vmulh()
3378 emitSIMDBase(VshrnOpcode | (Imm6 << ImmShift), Dd, 0, Dd, UseQRegs, in vmulh()
3404 const IValueT Dd = mapQRegToDReg(encodeQRegister(OpQd, "Qd", Vmull)); in vmlap() local
3410 emitSIMDBase(VmullOpcode | (ElmtSize << ElmtShift), Dd, Dn, Dm, UseQRegs, in vmlap()
3421 emitSIMDBase(VpaddOpcode, Dd, Dd, Dd + 1, UseQRegs, IsFloatTy); in vmlap()
3435 const IValueT Dd = mapQRegToDReg(encodeQRegister(OpQd, "Qd", Vdup)); in vdup() local
3465 emitSIMDBase(VdupOpcode, Dd, Imm4, Dn + (Lower ? 0 : 1), UseQRegs, IsFloatTy); in vdup()
3481 const IValueT Dd = mapQRegToDReg(encodeQRegister(OpQd, "Qd", Vzip)); in vzip() local
3493 emitSIMDBase(VmovOpcode, Dd + 1, Dm, Dm, UseQRegs, IsFloatTy); in vzip()
3496 if (Dd != Dn) in vzip()
3497 emitSIMDBase(VmovOpcode, Dd, Dn, Dn, UseQRegs, IsFloatTy); in vzip()
3506 emitSIMDBase(VzipOpcode | (ElmtSize << ElmtShift), Dd, 0, Dd + 1, UseQRegs, in vzip()
3510 emitSIMDBase(VtrnOpcode | (ElmtSize << ElmtShift), Dd, 0, Dd + 1, UseQRegs, in vzip()
3556 const IValueT Dd = mapQRegToDReg(encodeQRegister(OpQd, "Qd", Vmov)); in vmovlq() local
3565 if (Dd != Dm) in vmovlq()
3566 emitSIMDBase(VmovOpcode, Dd, Dm, Dm, UseQRegs, IsFloat); in vmovlq()
3567 if (Dd + 1 != Dn + 1) in vmovlq()
3568 emitSIMDBase(VmovOpcode, Dd + 1, Dn + 1, Dn + 1, UseQRegs, IsFloat); in vmovlq()
3582 const IValueT Dd = mapQRegToDReg(encodeQRegister(OpQd, "Qd", Vmov)); in vmovhq() local
3591 if (Dd != Dn) in vmovhq()
3592 emitSIMDBase(VmovOpcode, Dd, Dn, Dn, UseQRegs, IsFloat); in vmovhq()
3593 if (Dd + 1 != Dm + 1) in vmovhq()
3594 emitSIMDBase(VmovOpcode, Dd + 1, Dm + 1, Dm + 1, UseQRegs, IsFloat); in vmovhq()
3608 const IValueT Dd = mapQRegToDReg(encodeQRegister(OpQd, "Qd", Vmov)); in vmovhlq() local
3617 if (Dd != Dm + 1) in vmovhlq()
3618 emitSIMDBase(VmovOpcode, Dd, Dm + 1, Dm + 1, UseQRegs, IsFloat); in vmovhlq()
3619 if (Dd + 1 != Dn + 1) in vmovhlq()
3620 emitSIMDBase(VmovOpcode, Dd + 1, Dn + 1, Dn + 1, UseQRegs, IsFloat); in vmovhlq()
3634 const IValueT Dd = mapQRegToDReg(encodeQRegister(OpQd, "Qd", Vmov)); in vmovlhq() local
3643 if (Dd + 1 != Dm) in vmovlhq()
3644 emitSIMDBase(VmovOpcode, Dd + 1, Dm, Dm, UseQRegs, IsFloat); in vmovlhq()
3645 if (Dd != Dn) in vmovlhq()
3646 emitSIMDBase(VmovOpcode, Dd, Dn, Dn, UseQRegs, IsFloat); in vmovlhq()
3693 IValueT Dd = encodeDRegister(OpDd, "Dd", Vstrd); in vstrd() local
3702 (getYInRegYXXXX(Dd) << 22) | in vstrd()
3703 (getXXXXInRegYXXXX(Dd) << 12) | Address; in vstrd()
3718 IValueT Dd = mapQRegToDReg(encodeQRegister(OpQd, "Dd", Vstrd)); in vstrq() local
3727 (getYInRegYXXXX(Dd) << 22) | in vstrq()
3728 (getXXXXInRegYXXXX(Dd) << 12) | Address; in vstrq()
3763 const IValueT Dd = mapQRegToDReg(Qd); in vst1qr() local
3772 emitVMem1Op(Opcode, Dd, Rn, Rm, DRegListSize2, ElmtSize, Align, Vst1qr); in vst1qr()
3794 const IValueT Dd = mapQRegToDReg(Qd); in vst1() local
3803 emitVMem1Op(Opcode, Dd, Rn, Rm, ElmtSize, Align, Vst1qr); in vst1()
3921 const IValueT Dd = mapQRegToDReg(Qd); in vqmovn2() local
3933 emitSIMDBase(VqmovnOpcode, Dd + 1, 0, Dn, UseQRegs, IsFloatTy); in vqmovn2()
3935 emitSIMDBase(VqmovnOpcode, Dd + 0, 0, Dm, UseQRegs, IsFloatTy); in vqmovn2()
3938 emitSIMDBase(VqmovnOpcode, Dd + 0, 0, Dm, UseQRegs, IsFloatTy); in vqmovn2()
3940 emitSIMDBase(VqmovnOpcode, Dd + 1, 0, Dn, UseQRegs, IsFloatTy); in vqmovn2()
3943 emitSIMDBase(VqmovnOpcode, Dd, 0, Dm, UseQRegs, IsFloatTy); in vqmovn2()
3949 emitSIMDBase(VmovOpcode, Dd + 1, Dd, Dd, UseQRegs, IsFloatTy); in vqmovn2()
4079 IValueT Dd = encodeDRegister(OpDd, "Dd", Vsqrtd); in vsqrtd() local
4083 emitVFPddd(Cond, VsqrtdOpcode, Dd, D0, Dm); in vsqrtd()