684 void AssemblerMIPS32::ldc1(const Operand *OpRt, const Operand *OpBase,  in ldc1()  argument
688   const IValueT Base = encodeGPRegister(OpBase, "Base", "ldc1");  in ldc1()
705 void AssemblerMIPS32::ll(const Operand *OpRt, const Operand *OpBase,  in ll()  argument
708   emitRtRsImm16(Opcode, OpRt, OpBase, Offset, "ll");  in ll()
711 void AssemblerMIPS32::lw(const Operand *OpRt, const Operand *OpBase,  in lw()  argument
717     emitRtRsImm16(Opcode, OpRt, OpBase, Offset, "lb");  in lw()
722     emitRtRsImm16(Opcode, OpRt, OpBase, Offset, "lh");  in lw()
727     emitRtRsImm16(Opcode, OpRt, OpBase, Offset, "lw");  in lw()
732     emitFtRsImm16(Opcode, OpRt, OpBase, Offset, "lwc1");  in lw()
737     emitFtRsImm16(Opcode, OpRt, OpBase, Offset, "ldc1");  in lw()
746 void AssemblerMIPS32::lwc1(const Operand *OpRt, const Operand *OpBase,  in lwc1()  argument
750   const IValueT Base = encodeGPRegister(OpBase, "Base", "lwc1");  in lwc1()
978 void AssemblerMIPS32::sc(const Operand *OpRt, const Operand *OpBase,  in sc()  argument
981   emitRtRsImm16(Opcode, OpRt, OpBase, Offset, "sc");  in sc()
1072 void AssemblerMIPS32::sdc1(const Operand *OpRt, const Operand *OpBase,  in sdc1()  argument
1076   const IValueT Base = encodeGPRegister(OpBase, "Base", "sdc1");  in sdc1()
1093 void AssemblerMIPS32::sw(const Operand *OpRt, const Operand *OpBase,  in sw()  argument
1099     emitRtRsImm16(Opcode, OpRt, OpBase, Offset, "sb");  in sw()
1104     emitRtRsImm16(Opcode, OpRt, OpBase, Offset, "sh");  in sw()
1109     emitRtRsImm16(Opcode, OpRt, OpBase, Offset, "sw");  in sw()
1114     emitFtRsImm16(Opcode, OpRt, OpBase, Offset, "swc1");  in sw()
1119     emitFtRsImm16(Opcode, OpRt, OpBase, Offset, "sdc1");  in sw()
1128 void AssemblerMIPS32::swc1(const Operand *OpRt, const Operand *OpBase,  in swc1()  argument
1132   const IValueT Base = encodeGPRegister(OpBase, "Base", "swc1");  in swc1()