Lines Matching refs:rm_
57 : imm_(immediate), rm_(NoReg), shift_(LSL), amount_(0), rs_(NoReg) {} in Operand()
59 : imm_(immediate), rm_(NoReg), shift_(LSL), amount_(0), rs_(NoReg) {} in Operand()
66 : imm_(0), rm_(rm), shift_(LSL), amount_(0), rs_(NoReg) { in Operand()
67 VIXL_ASSERT(rm_.IsValid()); in Operand()
74 : imm_(0), rm_(rm), shift_(shift), amount_(0), rs_(NoReg) { in Operand()
75 VIXL_ASSERT(rm_.IsValid()); in Operand()
84 : imm_(0), rm_(rm), shift_(shift), amount_(amount), rs_(NoReg) { in Operand()
85 VIXL_ASSERT(rm_.IsValid()); in Operand()
112 : imm_(0), rm_(rm), shift_(shift), amount_(0), rs_(rs) { in Operand()
113 VIXL_ASSERT(rm_.IsValid() && rs_.IsValid()); in Operand()
142 bool IsImmediate() const { return !rm_.IsValid(); } in IsImmediate()
145 return rm_.IsValid() && !shift_.IsRRX() && !rs_.IsValid() && (amount_ == 0); in IsPlainRegister()
149 return rm_.IsValid() && !rs_.IsValid(); in IsImmediateShiftedRegister()
153 return rm_.IsValid() && rs_.IsValid(); in IsRegisterShiftedRegister()
170 return rm_; in GetBaseRegister()
216 Register rm_; variable
359 : imm_(immediate), rm_(NoDReg) {} in NeonOperand()
361 : imm_(immediate), rm_(NoDReg) {} in NeonOperand()
363 : imm_(immediate), rm_(NoDReg) {} in NeonOperand()
365 : imm_(immediate), rm_(NoDReg) {} in NeonOperand()
367 : imm_(immediate), rm_(NoDReg) {} in NeonOperand()
369 : imm_(immediate), rm_(NoDReg) {} in NeonOperand()
371 : imm_(imm), rm_(NoDReg) {} in NeonOperand()
373 : imm_(0), rm_(rm) { in NeonOperand()
374 VIXL_ASSERT(rm_.IsValid()); in NeonOperand()
377 bool IsImmediate() const { return !rm_.IsValid(); } in IsImmediate()
378 bool IsRegister() const { return rm_.IsValid(); } in IsRegister()
388 return rm_; in GetRegister()
393 VRegister rm_; variable
426 VIXL_ASSERT(IsRegister() && (rm_.GetType() == CPURegister::kSRegister)); in GetRegister()
427 return SRegister(rm_.GetCode()); in GetRegister()
468 VIXL_ASSERT(IsRegister() && (rm_.GetType() == CPURegister::kDRegister)); in GetRegister()
469 return DRegister(rm_.GetCode()); in GetRegister()
503 VIXL_ASSERT(rm_.IsValid()); in QOperand()
507 VIXL_ASSERT(IsRegister() && (rm_.GetType() == CPURegister::kQRegister)); in GetRegister()
508 return QRegister(rm_.GetCode()); in GetRegister()
641 rm_(NoReg), in rn_()
658 rm_(NoReg), in rn_()
668 rm_(NoReg), in rn_()
685 rm_(rm), in rn_()
689 VIXL_ASSERT(rn_.IsValid() && rm_.IsValid()); in rn_()
699 rm_(rm), in rn_()
703 VIXL_ASSERT(rn_.IsValid() && rm_.IsValid()); in rn_()
719 rm_(rm), in rn_()
723 VIXL_ASSERT(rn_.IsValid() && rm_.IsValid()); in rn_()
735 rm_(rm), in rn_()
739 VIXL_ASSERT(rn_.IsValid() && rm_.IsValid()); in rn_()
758 rm_(rm), in rn_()
762 VIXL_ASSERT(rn_.IsValid() && rm_.IsValid()); in rn_()
779 rm_(rm), in rn_()
783 VIXL_ASSERT(rn_.IsValid() && rm_.IsValid()); in rn_()
796 Register GetOffsetRegister() const { return rm_; } in GetOffsetRegister()
806 bool IsImmediate() const { return !rm_.IsValid(); } in IsImmediate()
807 bool IsImmediateZero() const { return !rm_.IsValid() && (offset_ == 0); } in IsImmediateZero()
809 return rm_.IsValid() && shift_.IsLSL() && (shift_amount_ == 0); in IsPlainRegister()
811 bool IsShiftedRegister() const { return rm_.IsValid(); } in IsShiftedRegister()
813 return (GetAddrMode() == Offset) && !rm_.IsValid(); in IsImmediateOffset()
816 return (GetAddrMode() == Offset) && !rm_.IsValid() && (offset_ == 0); in IsImmediateZeroOffset()
819 return (GetAddrMode() == Offset) && rm_.IsValid() && shift_.IsLSL() && in IsRegisterOffset()
823 return (GetAddrMode() == Offset) && rm_.IsValid(); in IsShiftedRegisterOffset()
867 Register rm_; variable