Lines Matching refs:vn
315 const VRegister& vn, in NEONTable() argument
320 VIXL_ASSERT(vn.Is16B()); in NEONTable()
322 Emit(op | (vd.IsQ() ? NEON_Q : 0) | Rm(vm) | Rn(vn) | Rd(vd)); in NEONTable()
327 const VRegister& vn, in tbl() argument
330 NEONTable(vd, vn, vm, NEON_TBL_1v); in tbl()
335 const VRegister& vn, in tbl() argument
340 VIXL_ASSERT(AreSameFormat(vn, vn2)); in tbl()
341 VIXL_ASSERT(AreConsecutive(vn, vn2)); in tbl()
342 NEONTable(vd, vn, vm, NEON_TBL_2v); in tbl()
347 const VRegister& vn, in tbl() argument
353 VIXL_ASSERT(AreSameFormat(vn, vn2, vn3)); in tbl()
354 VIXL_ASSERT(AreConsecutive(vn, vn2, vn3)); in tbl()
355 NEONTable(vd, vn, vm, NEON_TBL_3v); in tbl()
360 const VRegister& vn, in tbl() argument
367 VIXL_ASSERT(AreSameFormat(vn, vn2, vn3, vn4)); in tbl()
368 VIXL_ASSERT(AreConsecutive(vn, vn2, vn3, vn4)); in tbl()
369 NEONTable(vd, vn, vm, NEON_TBL_4v); in tbl()
374 const VRegister& vn, in tbx() argument
377 NEONTable(vd, vn, vm, NEON_TBX_1v); in tbx()
382 const VRegister& vn, in tbx() argument
387 VIXL_ASSERT(AreSameFormat(vn, vn2)); in tbx()
388 VIXL_ASSERT(AreConsecutive(vn, vn2)); in tbx()
389 NEONTable(vd, vn, vm, NEON_TBX_2v); in tbx()
394 const VRegister& vn, in tbx() argument
400 VIXL_ASSERT(AreSameFormat(vn, vn2, vn3)); in tbx()
401 VIXL_ASSERT(AreConsecutive(vn, vn2, vn3)); in tbx()
402 NEONTable(vd, vn, vm, NEON_TBX_3v); in tbx()
407 const VRegister& vn, in tbx() argument
414 VIXL_ASSERT(AreSameFormat(vn, vn2, vn3, vn4)); in tbx()
415 VIXL_ASSERT(AreConsecutive(vn, vn2, vn3, vn4)); in tbx()
416 NEONTable(vd, vn, vm, NEON_TBX_4v); in tbx()
2381 const VRegister& vn, in NEON3DifferentL() argument
2384 VIXL_ASSERT(AreSameFormat(vn, vm)); in NEON3DifferentL()
2385 VIXL_ASSERT((vn.Is1H() && vd.Is1S()) || (vn.Is1S() && vd.Is1D()) || in NEON3DifferentL()
2386 (vn.Is8B() && vd.Is8H()) || (vn.Is4H() && vd.Is4S()) || in NEON3DifferentL()
2387 (vn.Is2S() && vd.Is2D()) || (vn.Is16B() && vd.Is8H()) || in NEON3DifferentL()
2388 (vn.Is8H() && vd.Is4S()) || (vn.Is4S() && vd.Is2D())); in NEON3DifferentL()
2392 format = SFormat(vn); in NEON3DifferentL()
2394 format = VFormat(vn); in NEON3DifferentL()
2396 Emit(format | op | Rm(vm) | Rn(vn) | Rd(vd)); in NEON3DifferentL()
2401 const VRegister& vn, in NEON3DifferentW() argument
2404 VIXL_ASSERT(AreSameFormat(vd, vn)); in NEON3DifferentW()
2408 Emit(VFormat(vm) | vop | Rm(vm) | Rn(vn) | Rd(vd)); in NEON3DifferentW()
2413 const VRegister& vn, in NEON3DifferentHN() argument
2416 VIXL_ASSERT(AreSameFormat(vm, vn)); in NEON3DifferentHN()
2417 VIXL_ASSERT((vd.Is8B() && vn.Is8H()) || (vd.Is4H() && vn.Is4S()) || in NEON3DifferentHN()
2418 (vd.Is2S() && vn.Is2D()) || (vd.Is16B() && vn.Is8H()) || in NEON3DifferentHN()
2419 (vd.Is8H() && vn.Is4S()) || (vd.Is4S() && vn.Is2D())); in NEON3DifferentHN()
2420 Emit(VFormat(vd) | vop | Rm(vm) | Rn(vn) | Rd(vd)); in NEON3DifferentHN()
2426 V(pmull, NEON_PMULL, vn.IsVector() && vn.Is8B()) \
2427 V(pmull2, NEON_PMULL2, vn.IsVector() && vn.Is16B()) \
2428 V(saddl, NEON_SADDL, vn.IsVector() && vn.IsD()) \
2429 V(saddl2, NEON_SADDL2, vn.IsVector() && vn.IsQ()) \
2430 V(sabal, NEON_SABAL, vn.IsVector() && vn.IsD()) \
2431 V(sabal2, NEON_SABAL2, vn.IsVector() && vn.IsQ()) \
2432 V(uabal, NEON_UABAL, vn.IsVector() && vn.IsD()) \
2433 V(uabal2, NEON_UABAL2, vn.IsVector() && vn.IsQ()) \
2434 V(sabdl, NEON_SABDL, vn.IsVector() && vn.IsD()) \
2435 V(sabdl2, NEON_SABDL2, vn.IsVector() && vn.IsQ()) \
2436 V(uabdl, NEON_UABDL, vn.IsVector() && vn.IsD()) \
2437 V(uabdl2, NEON_UABDL2, vn.IsVector() && vn.IsQ()) \
2438 V(smlal, NEON_SMLAL, vn.IsVector() && vn.IsD()) \
2439 V(smlal2, NEON_SMLAL2, vn.IsVector() && vn.IsQ()) \
2440 V(umlal, NEON_UMLAL, vn.IsVector() && vn.IsD()) \
2441 V(umlal2, NEON_UMLAL2, vn.IsVector() && vn.IsQ()) \
2442 V(smlsl, NEON_SMLSL, vn.IsVector() && vn.IsD()) \
2443 V(smlsl2, NEON_SMLSL2, vn.IsVector() && vn.IsQ()) \
2444 V(umlsl, NEON_UMLSL, vn.IsVector() && vn.IsD()) \
2445 V(umlsl2, NEON_UMLSL2, vn.IsVector() && vn.IsQ()) \
2446 V(smull, NEON_SMULL, vn.IsVector() && vn.IsD()) \
2447 V(smull2, NEON_SMULL2, vn.IsVector() && vn.IsQ()) \
2448 V(umull, NEON_UMULL, vn.IsVector() && vn.IsD()) \
2449 V(umull2, NEON_UMULL2, vn.IsVector() && vn.IsQ()) \
2450 V(ssubl, NEON_SSUBL, vn.IsVector() && vn.IsD()) \
2451 V(ssubl2, NEON_SSUBL2, vn.IsVector() && vn.IsQ()) \
2452 V(uaddl, NEON_UADDL, vn.IsVector() && vn.IsD()) \
2453 V(uaddl2, NEON_UADDL2, vn.IsVector() && vn.IsQ()) \
2454 V(usubl, NEON_USUBL, vn.IsVector() && vn.IsD()) \
2455 V(usubl2, NEON_USUBL2, vn.IsVector() && vn.IsQ()) \
2456 V(sqdmlal, NEON_SQDMLAL, vn.Is1H() || vn.Is1S() || vn.Is4H() || vn.Is2S()) \
2457 V(sqdmlal2, NEON_SQDMLAL2, vn.Is1H() || vn.Is1S() || vn.Is8H() || vn.Is4S()) \
2458 V(sqdmlsl, NEON_SQDMLSL, vn.Is1H() || vn.Is1S() || vn.Is4H() || vn.Is2S()) \
2459 V(sqdmlsl2, NEON_SQDMLSL2, vn.Is1H() || vn.Is1S() || vn.Is8H() || vn.Is4S()) \
2460 V(sqdmull, NEON_SQDMULL, vn.Is1H() || vn.Is1S() || vn.Is4H() || vn.Is2S()) \
2461 V(sqdmull2, NEON_SQDMULL2, vn.Is1H() || vn.Is1S() || vn.Is8H() || vn.Is4S()) \
2467 const VRegister& vn, \
2471 NEON3DifferentL(vd, vn, vm, OP); \
2490 const VRegister& vn, \
2494 NEON3DifferentHN(vd, vn, vm, OP); \
2500 const VRegister& vn, in NEON_3DIFF_HN_LIST()
2504 NEON3DifferentW(vd, vn, vm, NEON_UADDW); in NEON_3DIFF_HN_LIST()
2509 const VRegister& vn, in uaddw2() argument
2513 NEON3DifferentW(vd, vn, vm, NEON_UADDW2); in uaddw2()
2518 const VRegister& vn, in saddw() argument
2522 NEON3DifferentW(vd, vn, vm, NEON_SADDW); in saddw()
2527 const VRegister& vn, in saddw2() argument
2531 NEON3DifferentW(vd, vn, vm, NEON_SADDW2); in saddw2()
2536 const VRegister& vn, in usubw() argument
2540 NEON3DifferentW(vd, vn, vm, NEON_USUBW); in usubw()
2545 const VRegister& vn, in usubw2() argument
2549 NEON3DifferentW(vd, vn, vm, NEON_USUBW2); in usubw2()
2554 const VRegister& vn, in ssubw() argument
2558 NEON3DifferentW(vd, vn, vm, NEON_SSUBW); in ssubw()
2563 const VRegister& vn, in ssubw2() argument
2567 NEON3DifferentW(vd, vn, vm, NEON_SSUBW2); in ssubw2()
2764 void Assembler::fmov(const Register& rd, const VRegister& vn) { in fmov() argument
2766 VIXL_ASSERT(vn.Is1H() || vn.Is1S() || vn.Is1D()); in fmov()
2767 VIXL_ASSERT((rd.GetSizeInBits() == vn.GetSizeInBits()) || vn.Is1H()); in fmov()
2769 switch (vn.GetSizeInBits()) { in fmov()
2780 Emit(op | Rd(rd) | Rn(vn)); in fmov()
2804 void Assembler::fmov(const VRegister& vd, const VRegister& vn) { in fmov() argument
2810 VIXL_ASSERT(vd.IsSameFormat(vn)); in fmov()
2811 Emit(FPType(vd) | FMOV | Rd(vd) | Rn(vn)); in fmov()
2823 void Assembler::fmov(const Register& rd, const VRegister& vn, int index) { in fmov() argument
2825 VIXL_ASSERT((index == 1) && vn.Is1D() && rd.IsX()); in fmov()
2827 Emit(FMOV_x_d1 | Rd(rd) | Rn(vn)); in fmov()
2832 const VRegister& vn, in fmadd() argument
2846 FPDataProcessing3Source(vd, vn, vm, va, op); in fmadd()
2851 const VRegister& vn, in fmsub() argument
2865 FPDataProcessing3Source(vd, vn, vm, va, op); in fmsub()
2870 const VRegister& vn, in fnmadd() argument
2884 FPDataProcessing3Source(vd, vn, vm, va, op); in fnmadd()
2889 const VRegister& vn, in fnmsub() argument
2903 FPDataProcessing3Source(vd, vn, vm, va, op); in fnmsub()
2908 const VRegister& vn, in fnmul() argument
2911 VIXL_ASSERT(AreSameSizeAndType(vd, vn, vm)); in fnmul()
2922 Emit(FPType(vd) | op | Rm(vm) | Rn(vn) | Rd(vd)); in fnmul()
2926 void Assembler::FPCompareMacro(const VRegister& vn, in FPCompareMacro() argument
2934 VIXL_ASSERT(vn.Is1H() || vn.Is1S() || vn.Is1D()); in FPCompareMacro()
2936 Emit(FPType(vn) | op | Rn(vn)); in FPCompareMacro()
2940 void Assembler::FPCompareMacro(const VRegister& vn, in FPCompareMacro() argument
2943 VIXL_ASSERT(vn.Is1H() || vn.Is1S() || vn.Is1D()); in FPCompareMacro()
2944 VIXL_ASSERT(vn.IsSameSizeAndType(vm)); in FPCompareMacro()
2946 Emit(FPType(vn) | op | Rm(vm) | Rn(vn)); in FPCompareMacro()
2950 void Assembler::fcmp(const VRegister& vn, const VRegister& vm) { in fcmp() argument
2952 if (vn.Is1H()) VIXL_ASSERT(CPUHas(CPUFeatures::kFPHalf)); in fcmp()
2953 FPCompareMacro(vn, vm, DisableTrap); in fcmp()
2957 void Assembler::fcmpe(const VRegister& vn, const VRegister& vm) { in fcmpe() argument
2959 if (vn.Is1H()) VIXL_ASSERT(CPUHas(CPUFeatures::kFPHalf)); in fcmpe()
2960 FPCompareMacro(vn, vm, EnableTrap); in fcmpe()
2964 void Assembler::fcmp(const VRegister& vn, double value) { in fcmp() argument
2966 if (vn.Is1H()) VIXL_ASSERT(CPUHas(CPUFeatures::kFPHalf)); in fcmp()
2967 FPCompareMacro(vn, value, DisableTrap); in fcmp()
2971 void Assembler::fcmpe(const VRegister& vn, double value) { in fcmpe() argument
2973 if (vn.Is1H()) VIXL_ASSERT(CPUHas(CPUFeatures::kFPHalf)); in fcmpe()
2974 FPCompareMacro(vn, value, EnableTrap); in fcmpe()
2978 void Assembler::FPCCompareMacro(const VRegister& vn, in FPCCompareMacro() argument
2983 VIXL_ASSERT(vn.Is1H() || vn.Is1S() || vn.Is1D()); in FPCCompareMacro()
2984 VIXL_ASSERT(vn.IsSameSizeAndType(vm)); in FPCCompareMacro()
2986 Emit(FPType(vn) | op | Rm(vm) | Cond(cond) | Rn(vn) | Nzcv(nzcv)); in FPCCompareMacro()
2989 void Assembler::fccmp(const VRegister& vn, in fccmp() argument
2994 if (vn.Is1H()) VIXL_ASSERT(CPUHas(CPUFeatures::kFPHalf)); in fccmp()
2995 FPCCompareMacro(vn, vm, nzcv, cond, DisableTrap); in fccmp()
2999 void Assembler::fccmpe(const VRegister& vn, in fccmpe() argument
3004 if (vn.Is1H()) VIXL_ASSERT(CPUHas(CPUFeatures::kFPHalf)); in fccmpe()
3005 FPCCompareMacro(vn, vm, nzcv, cond, EnableTrap); in fccmpe()
3010 const VRegister& vn, in fcsel() argument
3016 VIXL_ASSERT(AreSameFormat(vd, vn, vm)); in fcsel()
3017 Emit(FPType(vd) | FCSEL | Rm(vm) | Cond(cond) | Rn(vn) | Rd(vd)); in fcsel()
3021 void Assembler::fcvt(const VRegister& vd, const VRegister& vn) { in fcvt() argument
3026 VIXL_ASSERT(vn.Is1S() || vn.Is1H()); in fcvt()
3027 op = vn.Is1S() ? FCVT_ds : FCVT_dh; in fcvt()
3029 VIXL_ASSERT(vn.Is1D() || vn.Is1H()); in fcvt()
3030 op = vn.Is1D() ? FCVT_sd : FCVT_sh; in fcvt()
3033 VIXL_ASSERT(vn.Is1D() || vn.Is1S()); in fcvt()
3034 op = vn.Is1D() ? FCVT_hd : FCVT_hs; in fcvt()
3036 FPDataProcessing1Source(vd, vn, op); in fcvt()
3040 void Assembler::fcvtl(const VRegister& vd, const VRegister& vn) { in fcvtl() argument
3042 VIXL_ASSERT((vd.Is4S() && vn.Is4H()) || (vd.Is2D() && vn.Is2S())); in fcvtl()
3045 Emit(format | NEON_FCVTL | Rn(vn) | Rd(vd)); in fcvtl()
3049 void Assembler::fcvtl2(const VRegister& vd, const VRegister& vn) { in fcvtl2() argument
3051 VIXL_ASSERT((vd.Is4S() && vn.Is8H()) || (vd.Is2D() && vn.Is4S())); in fcvtl2()
3054 Emit(NEON_Q | format | NEON_FCVTL | Rn(vn) | Rd(vd)); in fcvtl2()
3058 void Assembler::fcvtn(const VRegister& vd, const VRegister& vn) { in fcvtn() argument
3060 VIXL_ASSERT((vn.Is4S() && vd.Is4H()) || (vn.Is2D() && vd.Is2S())); in fcvtn()
3062 Instr format = vn.Is2D() ? (1 << NEONSize_offset) : 0; in fcvtn()
3063 Emit(format | NEON_FCVTN | Rn(vn) | Rd(vd)); in fcvtn()
3067 void Assembler::fcvtn2(const VRegister& vd, const VRegister& vn) { in fcvtn2() argument
3069 VIXL_ASSERT((vn.Is4S() && vd.Is8H()) || (vn.Is2D() && vd.Is4S())); in fcvtn2()
3071 Instr format = vn.Is2D() ? (1 << NEONSize_offset) : 0; in fcvtn2()
3072 Emit(NEON_Q | format | NEON_FCVTN | Rn(vn) | Rd(vd)); in fcvtn2()
3076 void Assembler::fcvtxn(const VRegister& vd, const VRegister& vn) { in fcvtxn() argument
3080 VIXL_ASSERT(vd.Is1S() && vn.Is1D()); in fcvtxn()
3081 Emit(format | NEON_FCVTXN_scalar | Rn(vn) | Rd(vd)); in fcvtxn()
3083 VIXL_ASSERT(vd.Is2S() && vn.Is2D()); in fcvtxn()
3084 Emit(format | NEON_FCVTXN | Rn(vn) | Rd(vd)); in fcvtxn()
3089 void Assembler::fcvtxn2(const VRegister& vd, const VRegister& vn) { in fcvtxn2() argument
3091 VIXL_ASSERT(vd.Is4S() && vn.Is2D()); in fcvtxn2()
3093 Emit(NEON_Q | format | NEON_FCVTXN | Rn(vn) | Rd(vd)); in fcvtxn2()
3096 void Assembler::fjcvtzs(const Register& rd, const VRegister& vn) { in fjcvtzs() argument
3098 VIXL_ASSERT(rd.IsW() && vn.Is1D()); in fjcvtzs()
3099 Emit(FJCVTZS | Rn(vn) | Rd(rd)); in fjcvtzs()
3104 const VRegister& vn, in NEONFPConvertToInt() argument
3106 Emit(SF(rd) | FPType(vn) | op | Rn(vn) | Rd(rd)); in NEONFPConvertToInt()
3111 const VRegister& vn, in NEONFPConvertToInt() argument
3113 if (vn.IsScalar()) { in NEONFPConvertToInt()
3114 VIXL_ASSERT((vd.Is1S() && vn.Is1S()) || (vd.Is1D() && vn.Is1D())); in NEONFPConvertToInt()
3117 Emit(FPFormat(vn) | op | Rn(vn) | Rd(vd)); in NEONFPConvertToInt()
3122 const VRegister& vn, in NEONFP16ConvertToInt() argument
3124 VIXL_ASSERT(AreSameFormat(vd, vn)); in NEONFP16ConvertToInt()
3125 VIXL_ASSERT(vn.IsLaneSizeH()); in NEONFP16ConvertToInt()
3126 if (vn.IsScalar()) { in NEONFP16ConvertToInt()
3128 } else if (vn.Is8H()) { in NEONFP16ConvertToInt()
3131 Emit(op | Rn(vn) | Rd(vd)); in NEONFP16ConvertToInt()
3146 void Assembler::FN(const Register& rd, const VRegister& vn) { \
3148 if (vn.IsH()) VIXL_ASSERT(CPUHas(CPUFeatures::kFPHalf)); \
3149 NEONFPConvertToInt(rd, vn, SCA_OP); \
3151 void Assembler::FN(const VRegister& vd, const VRegister& vn) { \
3155 NEONFP16ConvertToInt(vd, vn, VEC_OP##_H); \
3157 NEONFPConvertToInt(vd, vn, VEC_OP); \
3164 void Assembler::fcvtzs(const Register& rd, const VRegister& vn, int fbits) { in NEON_FP2REGMISC_FCVT_LIST()
3166 if (vn.Is1H()) VIXL_ASSERT(CPUHas(CPUFeatures::kFPHalf)); in NEON_FP2REGMISC_FCVT_LIST()
3167 VIXL_ASSERT(vn.Is1H() || vn.Is1S() || vn.Is1D()); in NEON_FP2REGMISC_FCVT_LIST()
3170 Emit(SF(rd) | FPType(vn) | FCVTZS | Rn(vn) | Rd(rd)); in NEON_FP2REGMISC_FCVT_LIST()
3172 Emit(SF(rd) | FPType(vn) | FCVTZS_fixed | FPScale(64 - fbits) | Rn(vn) | in NEON_FP2REGMISC_FCVT_LIST()
3178 void Assembler::fcvtzs(const VRegister& vd, const VRegister& vn, int fbits) { in fcvtzs() argument
3181 if (vn.IsLaneSizeH()) VIXL_ASSERT(CPUHas(CPUFeatures::kNEONHalf)); in fcvtzs()
3185 NEONFP2RegMiscFP16(vd, vn, NEON_FCVTZS_H); in fcvtzs()
3187 NEONFP2RegMisc(vd, vn, NEON_FCVTZS); in fcvtzs()
3192 NEONShiftRightImmediate(vd, vn, fbits, NEON_FCVTZS_imm); in fcvtzs()
3197 void Assembler::fcvtzu(const Register& rd, const VRegister& vn, int fbits) { in fcvtzu() argument
3199 if (vn.Is1H()) VIXL_ASSERT(CPUHas(CPUFeatures::kFPHalf)); in fcvtzu()
3200 VIXL_ASSERT(vn.Is1H() || vn.Is1S() || vn.Is1D()); in fcvtzu()
3203 Emit(SF(rd) | FPType(vn) | FCVTZU | Rn(vn) | Rd(rd)); in fcvtzu()
3205 Emit(SF(rd) | FPType(vn) | FCVTZU_fixed | FPScale(64 - fbits) | Rn(vn) | in fcvtzu()
3211 void Assembler::fcvtzu(const VRegister& vd, const VRegister& vn, int fbits) { in fcvtzu() argument
3214 if (vn.IsLaneSizeH()) VIXL_ASSERT(CPUHas(CPUFeatures::kNEONHalf)); in fcvtzu()
3218 NEONFP2RegMiscFP16(vd, vn, NEON_FCVTZU_H); in fcvtzu()
3220 NEONFP2RegMisc(vd, vn, NEON_FCVTZU); in fcvtzu()
3225 NEONShiftRightImmediate(vd, vn, fbits, NEON_FCVTZU_imm); in fcvtzu()
3229 void Assembler::ucvtf(const VRegister& vd, const VRegister& vn, int fbits) { in ucvtf() argument
3232 if (vn.IsLaneSizeH()) VIXL_ASSERT(CPUHas(CPUFeatures::kNEONHalf)); in ucvtf()
3236 NEONFP2RegMiscFP16(vd, vn, NEON_UCVTF_H); in ucvtf()
3238 NEONFP2RegMisc(vd, vn, NEON_UCVTF); in ucvtf()
3243 NEONShiftRightImmediate(vd, vn, fbits, NEON_UCVTF_imm); in ucvtf()
3247 void Assembler::scvtf(const VRegister& vd, const VRegister& vn, int fbits) { in scvtf() argument
3250 if (vn.IsLaneSizeH()) VIXL_ASSERT(CPUHas(CPUFeatures::kNEONHalf)); in scvtf()
3254 NEONFP2RegMiscFP16(vd, vn, NEON_SCVTF_H); in scvtf()
3256 NEONFP2RegMisc(vd, vn, NEON_SCVTF); in scvtf()
3261 NEONShiftRightImmediate(vd, vn, fbits, NEON_SCVTF_imm); in scvtf()
3295 const VRegister& vn, in NEON3Same() argument
3298 VIXL_ASSERT(AreSameFormat(vd, vn, vm)); in NEON3Same()
3309 Emit(format | op | Rm(vm) | Rn(vn) | Rd(vd)); in NEON3Same()
3314 const VRegister& vn, in NEONFP3Same() argument
3317 VIXL_ASSERT(AreSameFormat(vd, vn, vm)); in NEONFP3Same()
3318 Emit(FPFormat(vd) | op | Rm(vm) | Rn(vn) | Rd(vd)); in NEONFP3Same()
3323 const VRegister& vn, in NEON3SameFP16() argument
3326 VIXL_ASSERT(AreSameFormat(vd, vn, vm)); in NEON3SameFP16()
3329 Emit(op | Rm(vm) | Rn(vn) | Rd(vd)); in NEON3SameFP16()
3350 void Assembler::FN(const VRegister& vd, const VRegister& vn) { \
3384 NEONFP2RegMiscFP16(vd, vn, op); \
3386 NEONFP2RegMisc(vd, vn, op); \
3401 void Assembler::FN(const VRegister& vd, const VRegister& vn) { \
3412 NEONFP2RegMisc(vd, vn, op); \
3418 const VRegister& vn, in NEON_FP2REGMISC_V85_LIST()
3420 VIXL_ASSERT(AreSameFormat(vd, vn)); in NEON_FP2REGMISC_V85_LIST()
3421 Emit(op | Rn(vn) | Rd(vd)); in NEON_FP2REGMISC_V85_LIST()
3426 const VRegister& vn, in NEONFP2RegMisc() argument
3428 VIXL_ASSERT(AreSameFormat(vd, vn)); in NEONFP2RegMisc()
3429 Emit(FPFormat(vd) | op | Rn(vn) | Rd(vd)); in NEONFP2RegMisc()
3434 const VRegister& vn, in NEON2RegMisc() argument
3437 VIXL_ASSERT(AreSameFormat(vd, vn)); in NEON2RegMisc()
3449 Emit(format | op | Rn(vn) | Rd(vd)); in NEON2RegMisc()
3453 void Assembler::cmeq(const VRegister& vd, const VRegister& vn, int value) { in cmeq() argument
3456 NEON2RegMisc(vd, vn, NEON_CMEQ_zero, value); in cmeq()
3460 void Assembler::cmge(const VRegister& vd, const VRegister& vn, int value) { in cmge() argument
3463 NEON2RegMisc(vd, vn, NEON_CMGE_zero, value); in cmge()
3467 void Assembler::cmgt(const VRegister& vd, const VRegister& vn, int value) { in cmgt() argument
3470 NEON2RegMisc(vd, vn, NEON_CMGT_zero, value); in cmgt()
3474 void Assembler::cmle(const VRegister& vd, const VRegister& vn, int value) { in cmle() argument
3477 NEON2RegMisc(vd, vn, NEON_CMLE_zero, value); in cmle()
3481 void Assembler::cmlt(const VRegister& vd, const VRegister& vn, int value) { in cmlt() argument
3484 NEON2RegMisc(vd, vn, NEON_CMLT_zero, value); in cmlt()
3488 void Assembler::shll(const VRegister& vd, const VRegister& vn, int shift) { in shll() argument
3491 VIXL_ASSERT((vd.Is8H() && vn.Is8B() && shift == 8) || in shll()
3492 (vd.Is4S() && vn.Is4H() && shift == 16) || in shll()
3493 (vd.Is2D() && vn.Is2S() && shift == 32)); in shll()
3494 Emit(VFormat(vn) | NEON_SHLL | Rn(vn) | Rd(vd)); in shll()
3498 void Assembler::shll2(const VRegister& vd, const VRegister& vn, int shift) { in shll2() argument
3501 VIXL_ASSERT((vd.Is8H() && vn.Is16B() && shift == 8) || in shll2()
3502 (vd.Is4S() && vn.Is8H() && shift == 16) || in shll2()
3503 (vd.Is2D() && vn.Is4S() && shift == 32)); in shll2()
3504 Emit(VFormat(vn) | NEON_SHLL | Rn(vn) | Rd(vd)); in shll2()
3509 const VRegister& vn, in NEONFP2RegMisc() argument
3512 VIXL_ASSERT(AreSameFormat(vd, vn)); in NEONFP2RegMisc()
3524 Emit(FPFormat(vd) | op | Rn(vn) | Rd(vd)); in NEONFP2RegMisc()
3529 const VRegister& vn, in NEONFP2RegMiscFP16() argument
3532 VIXL_ASSERT(AreSameFormat(vd, vn)); in NEONFP2RegMiscFP16()
3547 Emit(op | Rn(vn) | Rd(vd)); in NEONFP2RegMiscFP16()
3551 void Assembler::fcmeq(const VRegister& vd, const VRegister& vn, double value) { in fcmeq() argument
3555 NEONFP2RegMiscFP16(vd, vn, NEON_FCMEQ_H_zero, value); in fcmeq()
3557 NEONFP2RegMisc(vd, vn, NEON_FCMEQ_zero, value); in fcmeq()
3562 void Assembler::fcmge(const VRegister& vd, const VRegister& vn, double value) { in fcmge() argument
3566 NEONFP2RegMiscFP16(vd, vn, NEON_FCMGE_H_zero, value); in fcmge()
3568 NEONFP2RegMisc(vd, vn, NEON_FCMGE_zero, value); in fcmge()
3573 void Assembler::fcmgt(const VRegister& vd, const VRegister& vn, double value) { in fcmgt() argument
3577 NEONFP2RegMiscFP16(vd, vn, NEON_FCMGT_H_zero, value); in fcmgt()
3579 NEONFP2RegMisc(vd, vn, NEON_FCMGT_zero, value); in fcmgt()
3584 void Assembler::fcmle(const VRegister& vd, const VRegister& vn, double value) { in fcmle() argument
3588 NEONFP2RegMiscFP16(vd, vn, NEON_FCMLE_H_zero, value); in fcmle()
3590 NEONFP2RegMisc(vd, vn, NEON_FCMLE_zero, value); in fcmle()
3595 void Assembler::fcmlt(const VRegister& vd, const VRegister& vn, double value) { in fcmlt() argument
3599 NEONFP2RegMiscFP16(vd, vn, NEON_FCMLT_H_zero, value); in fcmlt()
3601 NEONFP2RegMisc(vd, vn, NEON_FCMLT_zero, value); in fcmlt()
3606 void Assembler::frecpx(const VRegister& vd, const VRegister& vn) { in frecpx() argument
3609 VIXL_ASSERT(AreSameFormat(vd, vn)); in frecpx()
3618 Emit(FPFormat(vd) | op | Rn(vn) | Rd(vd)); in frecpx()
3681 const VRegister& vn, \
3685 NEON3Same(vd, vn, vm, OP); \
3723 const VRegister& vn, \
3756 NEON3SameFP16(vd, vn, vm, op); \
3758 NEONFP3Same(vd, vn, vm, op); \
3775 const VRegister& vn, \ in NEON_FP3SAME_OP_LIST()
3781 VIXL_ASSERT((vd.Is2S() && vn.Is2H() && vm.Is2H()) || \ in NEON_FP3SAME_OP_LIST()
3782 (vd.Is4S() && vn.Is4H() && vm.Is4H())); \ in NEON_FP3SAME_OP_LIST()
3783 Emit(FPFormat(vd) | VEC_OP | Rm(vm) | Rn(vn) | Rd(vd)); \ in NEON_FP3SAME_OP_LIST()
3789 void Assembler::addp(const VRegister& vd, const VRegister& vn) {
3791 VIXL_ASSERT((vd.Is1D() && vn.Is2D()));
3792 Emit(SFormat(vd) | NEON_ADDP_scalar | Rn(vn) | Rd(vd));
3797 const VRegister& vn, in sqrdmlah() argument
3800 VIXL_ASSERT(AreSameFormat(vd, vn, vm)); in sqrdmlah()
3811 Emit(format | op | Rm(vm) | Rn(vn) | Rd(vd)); in sqrdmlah()
3816 const VRegister& vn, in sqrdmlsh() argument
3819 VIXL_ASSERT(AreSameFormat(vd, vn, vm)); in sqrdmlsh()
3830 Emit(format | op | Rm(vm) | Rn(vn) | Rd(vd)); in sqrdmlsh()
3835 const VRegister& vn, in sdot() argument
3838 VIXL_ASSERT(AreSameFormat(vn, vm)); in sdot()
3839 VIXL_ASSERT((vd.Is2S() && vn.Is8B()) || (vd.Is4S() && vn.Is16B())); in sdot()
3841 Emit(VFormat(vd) | NEON_SDOT | Rm(vm) | Rn(vn) | Rd(vd)); in sdot()
3846 const VRegister& vn, in udot() argument
3849 VIXL_ASSERT(AreSameFormat(vn, vm)); in udot()
3850 VIXL_ASSERT((vd.Is2S() && vn.Is8B()) || (vd.Is4S() && vn.Is16B())); in udot()
3852 Emit(VFormat(vd) | NEON_UDOT | Rm(vm) | Rn(vn) | Rd(vd)); in udot()
3856 void Assembler::faddp(const VRegister& vd, const VRegister& vn) { in faddp() argument
3858 VIXL_ASSERT((vd.Is1S() && vn.Is2S()) || (vd.Is1D() && vn.Is2D()) || in faddp()
3859 (vd.Is1H() && vn.Is2H())); in faddp()
3862 Emit(NEON_FADDP_h_scalar | Rn(vn) | Rd(vd)); in faddp()
3864 Emit(FPFormat(vd) | NEON_FADDP_scalar | Rn(vn) | Rd(vd)); in faddp()
3869 void Assembler::fmaxp(const VRegister& vd, const VRegister& vn) { in fmaxp() argument
3871 VIXL_ASSERT((vd.Is1S() && vn.Is2S()) || (vd.Is1D() && vn.Is2D()) || in fmaxp()
3872 (vd.Is1H() && vn.Is2H())); in fmaxp()
3875 Emit(NEON_FMAXP_h_scalar | Rn(vn) | Rd(vd)); in fmaxp()
3877 Emit(FPFormat(vd) | NEON_FMAXP_scalar | Rn(vn) | Rd(vd)); in fmaxp()
3882 void Assembler::fminp(const VRegister& vd, const VRegister& vn) { in fminp() argument
3884 VIXL_ASSERT((vd.Is1S() && vn.Is2S()) || (vd.Is1D() && vn.Is2D()) || in fminp()
3885 (vd.Is1H() && vn.Is2H())); in fminp()
3888 Emit(NEON_FMINP_h_scalar | Rn(vn) | Rd(vd)); in fminp()
3890 Emit(FPFormat(vd) | NEON_FMINP_scalar | Rn(vn) | Rd(vd)); in fminp()
3895 void Assembler::fmaxnmp(const VRegister& vd, const VRegister& vn) { in fmaxnmp() argument
3897 VIXL_ASSERT((vd.Is1S() && vn.Is2S()) || (vd.Is1D() && vn.Is2D()) || in fmaxnmp()
3898 (vd.Is1H() && vn.Is2H())); in fmaxnmp()
3901 Emit(NEON_FMAXNMP_h_scalar | Rn(vn) | Rd(vd)); in fmaxnmp()
3903 Emit(FPFormat(vd) | NEON_FMAXNMP_scalar | Rn(vn) | Rd(vd)); in fmaxnmp()
3908 void Assembler::fminnmp(const VRegister& vd, const VRegister& vn) { in fminnmp() argument
3910 VIXL_ASSERT((vd.Is1S() && vn.Is2S()) || (vd.Is1D() && vn.Is2D()) || in fminnmp()
3911 (vd.Is1H() && vn.Is2H())); in fminnmp()
3914 Emit(NEON_FMINNMP_h_scalar | Rn(vn) | Rd(vd)); in fminnmp()
3916 Emit(FPFormat(vd) | NEON_FMINNMP_scalar | Rn(vn) | Rd(vd)); in fminnmp()
3923 const VRegister& vn, in fcmla() argument
3928 VIXL_ASSERT(vd.IsVector() && AreSameFormat(vd, vn)); in fcmla()
3934 ImmNEONHLM(vm_index, index_num_bits) | ImmRotFcmlaSca(rot) | Rn(vn) | in fcmla()
3940 const VRegister& vn, in fcmla() argument
3944 VIXL_ASSERT(AreSameFormat(vd, vn, vm)); in fcmla()
3947 Emit(VFormat(vd) | Rm(vm) | NEON_FCMLA | ImmRotFcmlaVec(rot) | Rn(vn) | in fcmla()
3954 const VRegister& vn, in fcadd() argument
3958 VIXL_ASSERT(AreSameFormat(vd, vn, vm)); in fcadd()
3961 Emit(VFormat(vd) | Rm(vm) | NEON_FCADD | ImmRotFcadd(rot) | Rn(vn) | Rd(vd)); in fcadd()
3971 void Assembler::mov(const VRegister& vd, const VRegister& vn) { in mov() argument
3973 VIXL_ASSERT(AreSameFormat(vd, vn)); in mov()
3975 orr(vd.V8B(), vn.V8B(), vn.V8B()); in mov()
3978 orr(vd.V16B(), vn.V16B(), vn.V16B()); in mov()
4024 void Assembler::mvn(const VRegister& vd, const VRegister& vn) { in mvn() argument
4026 VIXL_ASSERT(AreSameFormat(vd, vn)); in mvn()
4028 not_(vd.V8B(), vn.V8B()); in mvn()
4031 not_(vd.V16B(), vn.V16B()); in mvn()
4051 const VRegister& vn, in NEONFPByElement() argument
4056 VIXL_ASSERT(AreSameFormat(vd, vn)); in NEONFPByElement()
4085 Emit(op | ImmNEONHLM(vm_index, index_num_bits) | Rm(vm) | Rn(vn) | Rd(vd)); in NEONFPByElement()
4090 const VRegister& vn, in NEONByElement() argument
4094 VIXL_ASSERT(AreSameFormat(vd, vn)); in NEONByElement()
4105 format = SFormat(vn); in NEONByElement()
4107 format = VFormat(vn); in NEONByElement()
4109 Emit(format | op | ImmNEONHLM(vm_index, index_num_bits) | Rm(vm) | Rn(vn) | in NEONByElement()
4115 const VRegister& vn, in NEONByElementL() argument
4119 VIXL_ASSERT((vd.Is4S() && vn.Is4H() && vm.Is1H()) || in NEONByElementL()
4120 (vd.Is4S() && vn.Is8H() && vm.Is1H()) || in NEONByElementL()
4121 (vd.Is1S() && vn.Is1H() && vm.Is1H()) || in NEONByElementL()
4122 (vd.Is2D() && vn.Is2S() && vm.Is1S()) || in NEONByElementL()
4123 (vd.Is2D() && vn.Is4S() && vm.Is1S()) || in NEONByElementL()
4124 (vd.Is1D() && vn.Is1S() && vm.Is1S())); in NEONByElementL()
4133 format = SFormat(vn); in NEONByElementL()
4135 format = VFormat(vn); in NEONByElementL()
4137 Emit(format | op | ImmNEONHLM(vm_index, index_num_bits) | Rm(vm) | Rn(vn) | in NEONByElementL()
4143 const VRegister& vn, in sdot() argument
4147 VIXL_ASSERT((vd.Is2S() && vn.Is8B() && vm.Is1S4B()) || in sdot()
4148 (vd.Is4S() && vn.Is16B() && vm.Is1S4B())); in sdot()
4152 ImmNEONHLM(vm_index, index_num_bits) | Rm(vm) | Rn(vn) | Rd(vd)); in sdot()
4157 const VRegister& vn, in udot() argument
4161 VIXL_ASSERT((vd.Is2S() && vn.Is8B() && vm.Is1S4B()) || in udot()
4162 (vd.Is4S() && vn.Is16B() && vm.Is1S4B())); in udot()
4166 ImmNEONHLM(vm_index, index_num_bits) | Rm(vm) | Rn(vn) | Rd(vd)); in udot()
4172 V(mul, NEON_MUL_byelement, vn.IsVector()) \
4173 V(mla, NEON_MLA_byelement, vn.IsVector()) \
4174 V(mls, NEON_MLS_byelement, vn.IsVector()) \
4181 const VRegister& vn, \
4186 NEONByElement(vd, vn, vm, vm_index, OP); \
4200 const VRegister& vn, \
4204 NEONByElement(vd, vn, vm, vm_index, OP); \
4220 const VRegister& vn, \ in NEON_BYELEMENT_RDM_LIST()
4225 NEONFPByElement(vd, vn, vm, vm_index, OP, OP_H); \ in NEON_BYELEMENT_RDM_LIST()
4233 V(sqdmull, NEON_SQDMULL_byelement, vn.IsScalar() || vn.IsD()) \
4234 V(sqdmull2, NEON_SQDMULL_byelement, vn.IsVector() && vn.IsQ()) \
4235 V(sqdmlal, NEON_SQDMLAL_byelement, vn.IsScalar() || vn.IsD()) \
4236 V(sqdmlal2, NEON_SQDMLAL_byelement, vn.IsVector() && vn.IsQ()) \
4237 V(sqdmlsl, NEON_SQDMLSL_byelement, vn.IsScalar() || vn.IsD()) \
4238 V(sqdmlsl2, NEON_SQDMLSL_byelement, vn.IsVector() && vn.IsQ()) \
4239 V(smull, NEON_SMULL_byelement, vn.IsVector() && vn.IsD()) \
4240 V(smull2, NEON_SMULL_byelement, vn.IsVector() && vn.IsQ()) \
4241 V(umull, NEON_UMULL_byelement, vn.IsVector() && vn.IsD()) \
4242 V(umull2, NEON_UMULL_byelement, vn.IsVector() && vn.IsQ()) \
4243 V(smlal, NEON_SMLAL_byelement, vn.IsVector() && vn.IsD()) \
4244 V(smlal2, NEON_SMLAL_byelement, vn.IsVector() && vn.IsQ()) \
4245 V(umlal, NEON_UMLAL_byelement, vn.IsVector() && vn.IsD()) \
4246 V(umlal2, NEON_UMLAL_byelement, vn.IsVector() && vn.IsQ()) \
4247 V(smlsl, NEON_SMLSL_byelement, vn.IsVector() && vn.IsD()) \
4248 V(smlsl2, NEON_SMLSL_byelement, vn.IsVector() && vn.IsQ()) \
4249 V(umlsl, NEON_UMLSL_byelement, vn.IsVector() && vn.IsD()) \
4250 V(umlsl2, NEON_UMLSL_byelement, vn.IsVector() && vn.IsQ())
4256 const VRegister& vn, \
4261 NEONByElementL(vd, vn, vm, vm_index, OP); \
4278 const VRegister& vn, \
4285 VIXL_ASSERT((vd.Is2S() && vn.Is2H()) || (vd.Is4S() && vn.Is4H())); \
4290 Emit(FPFormat(vd) | OP | Rd(vd) | Rn(vn) | Rm(vm) | \
4296 void Assembler::suqadd(const VRegister& vd, const VRegister& vn) {
4298 NEON2RegMisc(vd, vn, NEON_SUQADD);
4302 void Assembler::usqadd(const VRegister& vd, const VRegister& vn) { in usqadd() argument
4304 NEON2RegMisc(vd, vn, NEON_USQADD); in usqadd()
4308 void Assembler::abs(const VRegister& vd, const VRegister& vn) { in abs() argument
4311 NEON2RegMisc(vd, vn, NEON_ABS); in abs()
4315 void Assembler::sqabs(const VRegister& vd, const VRegister& vn) { in sqabs() argument
4317 NEON2RegMisc(vd, vn, NEON_SQABS); in sqabs()
4321 void Assembler::neg(const VRegister& vd, const VRegister& vn) { in neg() argument
4324 NEON2RegMisc(vd, vn, NEON_NEG); in neg()
4328 void Assembler::sqneg(const VRegister& vd, const VRegister& vn) { in sqneg() argument
4330 NEON2RegMisc(vd, vn, NEON_SQNEG); in sqneg()
4335 const VRegister& vn, in NEONXtn() argument
4340 VIXL_ASSERT((vd.Is1B() && vn.Is1H()) || (vd.Is1H() && vn.Is1S()) || in NEONXtn()
4341 (vd.Is1S() && vn.Is1D())); in NEONXtn()
4345 VIXL_ASSERT((vd.Is8B() && vn.Is8H()) || (vd.Is4H() && vn.Is4S()) || in NEONXtn()
4346 (vd.Is2S() && vn.Is2D()) || (vd.Is16B() && vn.Is8H()) || in NEONXtn()
4347 (vd.Is8H() && vn.Is4S()) || (vd.Is4S() && vn.Is2D())); in NEONXtn()
4350 Emit(format | op | Rn(vn) | Rd(vd)); in NEONXtn()
4354 void Assembler::xtn(const VRegister& vd, const VRegister& vn) { in xtn() argument
4357 NEONXtn(vd, vn, NEON_XTN); in xtn()
4361 void Assembler::xtn2(const VRegister& vd, const VRegister& vn) { in xtn2() argument
4364 NEONXtn(vd, vn, NEON_XTN); in xtn2()
4368 void Assembler::sqxtn(const VRegister& vd, const VRegister& vn) { in sqxtn() argument
4371 NEONXtn(vd, vn, NEON_SQXTN); in sqxtn()
4375 void Assembler::sqxtn2(const VRegister& vd, const VRegister& vn) { in sqxtn2() argument
4378 NEONXtn(vd, vn, NEON_SQXTN); in sqxtn2()
4382 void Assembler::sqxtun(const VRegister& vd, const VRegister& vn) { in sqxtun() argument
4385 NEONXtn(vd, vn, NEON_SQXTUN); in sqxtun()
4389 void Assembler::sqxtun2(const VRegister& vd, const VRegister& vn) { in sqxtun2() argument
4392 NEONXtn(vd, vn, NEON_SQXTUN); in sqxtun2()
4396 void Assembler::uqxtn(const VRegister& vd, const VRegister& vn) { in uqxtn() argument
4399 NEONXtn(vd, vn, NEON_UQXTN); in uqxtn()
4403 void Assembler::uqxtn2(const VRegister& vd, const VRegister& vn) { in uqxtn2() argument
4406 NEONXtn(vd, vn, NEON_UQXTN); in uqxtn2()
4411 void Assembler::not_(const VRegister& vd, const VRegister& vn) { in not_() argument
4413 VIXL_ASSERT(AreSameFormat(vd, vn)); in not_()
4415 Emit(VFormat(vd) | NEON_RBIT_NOT | Rn(vn) | Rd(vd)); in not_()
4419 void Assembler::rbit(const VRegister& vd, const VRegister& vn) { in rbit() argument
4421 VIXL_ASSERT(AreSameFormat(vd, vn)); in rbit()
4423 Emit(VFormat(vn) | (1 << NEONSize_offset) | NEON_RBIT_NOT | Rn(vn) | Rd(vd)); in rbit()
4428 const VRegister& vn, in ext() argument
4432 VIXL_ASSERT(AreSameFormat(vd, vn, vm)); in ext()
4435 Emit(VFormat(vd) | NEON_EXT | Rm(vm) | ImmNEONExt(index) | Rn(vn) | Rd(vd)); in ext()
4439 void Assembler::dup(const VRegister& vd, const VRegister& vn, int vn_index) { in dup() argument
4445 int lane_size = vn.GetLaneSizeInBytes(); in dup()
4471 Emit(q | scalar | NEON_DUP_ELEMENT | ImmNEON5(format, vn_index) | Rn(vn) | in dup()
4476 void Assembler::mov(const VRegister& vd, const VRegister& vn, int vn_index) { in mov() argument
4479 dup(vd, vn, vn_index); in mov()
4494 const VRegister& vn, in ins() argument
4497 VIXL_ASSERT(AreSameFormat(vd, vn)); in ins()
4525 ImmNEON4(format, vn_index) | Rn(vn) | Rd(vd)); in ins()
4531 const VRegister& vn, in mov() argument
4534 ins(vd, vd_index, vn, vn_index); in mov()
4577 void Assembler::umov(const Register& rd, const VRegister& vn, int vn_index) { in umov() argument
4581 int lane_size = vn.GetLaneSizeInBytes(); in umov()
4608 Emit(q | NEON_UMOV | ImmNEON5(format, vn_index) | Rn(vn) | Rd(rd)); in umov()
4612 void Assembler::mov(const Register& rd, const VRegister& vn, int vn_index) { in mov() argument
4614 VIXL_ASSERT(vn.GetSizeInBytes() >= 4); in mov()
4615 umov(rd, vn, vn_index); in mov()
4619 void Assembler::smov(const Register& rd, const VRegister& vn, int vn_index) { in smov() argument
4623 int lane_size = vn.GetLaneSizeInBytes(); in smov()
4644 Emit(q | NEON_SMOV | ImmNEON5(format, vn_index) | Rn(vn) | Rd(rd)); in smov()
4648 void Assembler::cls(const VRegister& vd, const VRegister& vn) { in cls() argument
4650 VIXL_ASSERT(AreSameFormat(vd, vn)); in cls()
4652 Emit(VFormat(vn) | NEON_CLS | Rn(vn) | Rd(vd)); in cls()
4656 void Assembler::clz(const VRegister& vd, const VRegister& vn) { in clz() argument
4658 VIXL_ASSERT(AreSameFormat(vd, vn)); in clz()
4660 Emit(VFormat(vn) | NEON_CLZ | Rn(vn) | Rd(vd)); in clz()
4664 void Assembler::cnt(const VRegister& vd, const VRegister& vn) { in cnt() argument
4666 VIXL_ASSERT(AreSameFormat(vd, vn)); in cnt()
4668 Emit(VFormat(vn) | NEON_CNT | Rn(vn) | Rd(vd)); in cnt()
4672 void Assembler::rev16(const VRegister& vd, const VRegister& vn) { in rev16() argument
4674 VIXL_ASSERT(AreSameFormat(vd, vn)); in rev16()
4676 Emit(VFormat(vn) | NEON_REV16 | Rn(vn) | Rd(vd)); in rev16()
4680 void Assembler::rev32(const VRegister& vd, const VRegister& vn) { in rev32() argument
4682 VIXL_ASSERT(AreSameFormat(vd, vn)); in rev32()
4684 Emit(VFormat(vn) | NEON_REV32 | Rn(vn) | Rd(vd)); in rev32()
4688 void Assembler::rev64(const VRegister& vd, const VRegister& vn) { in rev64() argument
4690 VIXL_ASSERT(AreSameFormat(vd, vn)); in rev64()
4692 Emit(VFormat(vn) | NEON_REV64 | Rn(vn) | Rd(vd)); in rev64()
4696 void Assembler::ursqrte(const VRegister& vd, const VRegister& vn) { in ursqrte() argument
4698 VIXL_ASSERT(AreSameFormat(vd, vn)); in ursqrte()
4700 Emit(VFormat(vn) | NEON_URSQRTE | Rn(vn) | Rd(vd)); in ursqrte()
4704 void Assembler::urecpe(const VRegister& vd, const VRegister& vn) { in urecpe() argument
4706 VIXL_ASSERT(AreSameFormat(vd, vn)); in urecpe()
4708 Emit(VFormat(vn) | NEON_URECPE | Rn(vn) | Rd(vd)); in urecpe()
4713 const VRegister& vn, in NEONAddlp() argument
4719 VIXL_ASSERT((vn.Is8B() && vd.Is4H()) || (vn.Is4H() && vd.Is2S()) || in NEONAddlp()
4720 (vn.Is2S() && vd.Is1D()) || (vn.Is16B() && vd.Is8H()) || in NEONAddlp()
4721 (vn.Is8H() && vd.Is4S()) || (vn.Is4S() && vd.Is2D())); in NEONAddlp()
4722 Emit(VFormat(vn) | op | Rn(vn) | Rd(vd)); in NEONAddlp()
4726 void Assembler::saddlp(const VRegister& vd, const VRegister& vn) { in saddlp() argument
4728 NEONAddlp(vd, vn, NEON_SADDLP); in saddlp()
4732 void Assembler::uaddlp(const VRegister& vd, const VRegister& vn) { in uaddlp() argument
4734 NEONAddlp(vd, vn, NEON_UADDLP); in uaddlp()
4738 void Assembler::sadalp(const VRegister& vd, const VRegister& vn) { in sadalp() argument
4740 NEONAddlp(vd, vn, NEON_SADALP); in sadalp()
4744 void Assembler::uadalp(const VRegister& vd, const VRegister& vn) { in uadalp() argument
4746 NEONAddlp(vd, vn, NEON_UADALP); in uadalp()
4751 const VRegister& vn, in NEONAcrossLanesL() argument
4753 VIXL_ASSERT((vn.Is8B() && vd.Is1H()) || (vn.Is16B() && vd.Is1H()) || in NEONAcrossLanesL()
4754 (vn.Is4H() && vd.Is1S()) || (vn.Is8H() && vd.Is1S()) || in NEONAcrossLanesL()
4755 (vn.Is4S() && vd.Is1D())); in NEONAcrossLanesL()
4756 Emit(VFormat(vn) | op | Rn(vn) | Rd(vd)); in NEONAcrossLanesL()
4760 void Assembler::saddlv(const VRegister& vd, const VRegister& vn) { in saddlv() argument
4762 NEONAcrossLanesL(vd, vn, NEON_SADDLV); in saddlv()
4766 void Assembler::uaddlv(const VRegister& vd, const VRegister& vn) { in uaddlv() argument
4768 NEONAcrossLanesL(vd, vn, NEON_UADDLV); in uaddlv()
4773 const VRegister& vn, in NEONAcrossLanes() argument
4776 VIXL_ASSERT((vn.Is8B() && vd.Is1B()) || (vn.Is16B() && vd.Is1B()) || in NEONAcrossLanes()
4777 (vn.Is4H() && vd.Is1H()) || (vn.Is8H() && vd.Is1H()) || in NEONAcrossLanes()
4778 (vn.Is4S() && vd.Is1S())); in NEONAcrossLanes()
4783 if (vn.Is8H()) { in NEONAcrossLanes()
4786 Emit(vop | Rn(vn) | Rd(vd)); in NEONAcrossLanes()
4788 Emit(FPFormat(vn) | op | Rn(vn) | Rd(vd)); in NEONAcrossLanes()
4791 Emit(VFormat(vn) | op | Rn(vn) | Rd(vd)); in NEONAcrossLanes()
4805 void Assembler::FN(const VRegister& vd, const VRegister& vn) { \
4807 NEONAcrossLanes(vd, vn, OP, 0); \
4822 void Assembler::FN(const VRegister& vd, const VRegister& vn) { \
4826 NEONAcrossLanes(vd, vn, OP, OP_H); \
4833 const VRegister& vn, in NEON_ACROSSLANES_FP_LIST()
4836 VIXL_ASSERT(AreSameFormat(vd, vn, vm)); in NEON_ACROSSLANES_FP_LIST()
4838 Emit(VFormat(vd) | op | Rm(vm) | Rn(vn) | Rd(vd)); in NEON_ACROSSLANES_FP_LIST()
4843 const VRegister& vn, in trn1() argument
4846 NEONPerm(vd, vn, vm, NEON_TRN1); in trn1()
4851 const VRegister& vn, in trn2() argument
4854 NEONPerm(vd, vn, vm, NEON_TRN2); in trn2()
4859 const VRegister& vn, in uzp1() argument
4862 NEONPerm(vd, vn, vm, NEON_UZP1); in uzp1()
4867 const VRegister& vn, in uzp2() argument
4870 NEONPerm(vd, vn, vm, NEON_UZP2); in uzp2()
4875 const VRegister& vn, in zip1() argument
4878 NEONPerm(vd, vn, vm, NEON_ZIP1); in zip1()
4883 const VRegister& vn, in zip2() argument
4886 NEONPerm(vd, vn, vm, NEON_ZIP2); in zip2()
4891 const VRegister& vn, in NEONShiftImmediate() argument
4894 VIXL_ASSERT(AreSameFormat(vd, vn)); in NEONShiftImmediate()
4896 if (vn.IsScalar()) { in NEONShiftImmediate()
4903 Emit(q | op | scalar | immh_immb | Rn(vn) | Rd(vd)); in NEONShiftImmediate()
4908 const VRegister& vn, in NEONShiftLeftImmediate() argument
4911 int lane_size_in_bits = vn.GetLaneSizeInBits(); in NEONShiftLeftImmediate()
4913 NEONShiftImmediate(vd, vn, op, (lane_size_in_bits + shift) << 16); in NEONShiftLeftImmediate()
4918 const VRegister& vn, in NEONShiftRightImmediate() argument
4921 int lane_size_in_bits = vn.GetLaneSizeInBits(); in NEONShiftRightImmediate()
4923 NEONShiftImmediate(vd, vn, op, ((2 * lane_size_in_bits) - shift) << 16); in NEONShiftRightImmediate()
4928 const VRegister& vn, in NEONShiftImmediateL() argument
4931 int lane_size_in_bits = vn.GetLaneSizeInBits(); in NEONShiftImmediateL()
4935 VIXL_ASSERT((vn.Is8B() && vd.Is8H()) || (vn.Is4H() && vd.Is4S()) || in NEONShiftImmediateL()
4936 (vn.Is2S() && vd.Is2D()) || (vn.Is16B() && vd.Is8H()) || in NEONShiftImmediateL()
4937 (vn.Is8H() && vd.Is4S()) || (vn.Is4S() && vd.Is2D())); in NEONShiftImmediateL()
4939 q = vn.IsD() ? 0 : NEON_Q; in NEONShiftImmediateL()
4940 Emit(q | op | immh_immb | Rn(vn) | Rd(vd)); in NEONShiftImmediateL()
4945 const VRegister& vn, in NEONShiftImmediateN() argument
4953 if (vn.IsScalar()) { in NEONShiftImmediateN()
4954 VIXL_ASSERT((vd.Is1B() && vn.Is1H()) || (vd.Is1H() && vn.Is1S()) || in NEONShiftImmediateN()
4955 (vd.Is1S() && vn.Is1D())); in NEONShiftImmediateN()
4959 VIXL_ASSERT((vd.Is8B() && vn.Is8H()) || (vd.Is4H() && vn.Is4S()) || in NEONShiftImmediateN()
4960 (vd.Is2S() && vn.Is2D()) || (vd.Is16B() && vn.Is8H()) || in NEONShiftImmediateN()
4961 (vd.Is8H() && vn.Is4S()) || (vd.Is4S() && vn.Is2D())); in NEONShiftImmediateN()
4965 Emit(q | op | scalar | immh_immb | Rn(vn) | Rd(vd)); in NEONShiftImmediateN()
4969 void Assembler::shl(const VRegister& vd, const VRegister& vn, int shift) { in shl() argument
4972 NEONShiftLeftImmediate(vd, vn, shift, NEON_SHL); in shl()
4976 void Assembler::sli(const VRegister& vd, const VRegister& vn, int shift) { in sli() argument
4979 NEONShiftLeftImmediate(vd, vn, shift, NEON_SLI); in sli()
4983 void Assembler::sqshl(const VRegister& vd, const VRegister& vn, int shift) { in sqshl() argument
4985 NEONShiftLeftImmediate(vd, vn, shift, NEON_SQSHL_imm); in sqshl()
4989 void Assembler::sqshlu(const VRegister& vd, const VRegister& vn, int shift) { in sqshlu() argument
4991 NEONShiftLeftImmediate(vd, vn, shift, NEON_SQSHLU); in sqshlu()
4995 void Assembler::uqshl(const VRegister& vd, const VRegister& vn, int shift) { in uqshl() argument
4997 NEONShiftLeftImmediate(vd, vn, shift, NEON_UQSHL_imm); in uqshl()
5001 void Assembler::sshll(const VRegister& vd, const VRegister& vn, int shift) { in sshll() argument
5003 VIXL_ASSERT(vn.IsD()); in sshll()
5004 NEONShiftImmediateL(vd, vn, shift, NEON_SSHLL); in sshll()
5008 void Assembler::sshll2(const VRegister& vd, const VRegister& vn, int shift) { in sshll2() argument
5010 VIXL_ASSERT(vn.IsQ()); in sshll2()
5011 NEONShiftImmediateL(vd, vn, shift, NEON_SSHLL); in sshll2()
5015 void Assembler::sxtl(const VRegister& vd, const VRegister& vn) { in sxtl() argument
5017 sshll(vd, vn, 0); in sxtl()
5021 void Assembler::sxtl2(const VRegister& vd, const VRegister& vn) { in sxtl2() argument
5023 sshll2(vd, vn, 0); in sxtl2()
5027 void Assembler::ushll(const VRegister& vd, const VRegister& vn, int shift) { in ushll() argument
5029 VIXL_ASSERT(vn.IsD()); in ushll()
5030 NEONShiftImmediateL(vd, vn, shift, NEON_USHLL); in ushll()
5034 void Assembler::ushll2(const VRegister& vd, const VRegister& vn, int shift) { in ushll2() argument
5036 VIXL_ASSERT(vn.IsQ()); in ushll2()
5037 NEONShiftImmediateL(vd, vn, shift, NEON_USHLL); in ushll2()
5041 void Assembler::uxtl(const VRegister& vd, const VRegister& vn) { in uxtl() argument
5043 ushll(vd, vn, 0); in uxtl()
5047 void Assembler::uxtl2(const VRegister& vd, const VRegister& vn) { in uxtl2() argument
5049 ushll2(vd, vn, 0); in uxtl2()
5053 void Assembler::sri(const VRegister& vd, const VRegister& vn, int shift) { in sri() argument
5056 NEONShiftRightImmediate(vd, vn, shift, NEON_SRI); in sri()
5060 void Assembler::sshr(const VRegister& vd, const VRegister& vn, int shift) { in sshr() argument
5063 NEONShiftRightImmediate(vd, vn, shift, NEON_SSHR); in sshr()
5067 void Assembler::ushr(const VRegister& vd, const VRegister& vn, int shift) { in ushr() argument
5070 NEONShiftRightImmediate(vd, vn, shift, NEON_USHR); in ushr()
5074 void Assembler::srshr(const VRegister& vd, const VRegister& vn, int shift) { in srshr() argument
5077 NEONShiftRightImmediate(vd, vn, shift, NEON_SRSHR); in srshr()
5081 void Assembler::urshr(const VRegister& vd, const VRegister& vn, int shift) { in urshr() argument
5084 NEONShiftRightImmediate(vd, vn, shift, NEON_URSHR); in urshr()
5088 void Assembler::ssra(const VRegister& vd, const VRegister& vn, int shift) { in ssra() argument
5091 NEONShiftRightImmediate(vd, vn, shift, NEON_SSRA); in ssra()
5095 void Assembler::usra(const VRegister& vd, const VRegister& vn, int shift) { in usra() argument
5098 NEONShiftRightImmediate(vd, vn, shift, NEON_USRA); in usra()
5102 void Assembler::srsra(const VRegister& vd, const VRegister& vn, int shift) { in srsra() argument
5105 NEONShiftRightImmediate(vd, vn, shift, NEON_SRSRA); in srsra()
5109 void Assembler::ursra(const VRegister& vd, const VRegister& vn, int shift) { in ursra() argument
5112 NEONShiftRightImmediate(vd, vn, shift, NEON_URSRA); in ursra()
5116 void Assembler::shrn(const VRegister& vd, const VRegister& vn, int shift) { in shrn() argument
5118 VIXL_ASSERT(vn.IsVector() && vd.IsD()); in shrn()
5119 NEONShiftImmediateN(vd, vn, shift, NEON_SHRN); in shrn()
5123 void Assembler::shrn2(const VRegister& vd, const VRegister& vn, int shift) { in shrn2() argument
5125 VIXL_ASSERT(vn.IsVector() && vd.IsQ()); in shrn2()
5126 NEONShiftImmediateN(vd, vn, shift, NEON_SHRN); in shrn2()
5130 void Assembler::rshrn(const VRegister& vd, const VRegister& vn, int shift) { in rshrn() argument
5132 VIXL_ASSERT(vn.IsVector() && vd.IsD()); in rshrn()
5133 NEONShiftImmediateN(vd, vn, shift, NEON_RSHRN); in rshrn()
5137 void Assembler::rshrn2(const VRegister& vd, const VRegister& vn, int shift) { in rshrn2() argument
5139 VIXL_ASSERT(vn.IsVector() && vd.IsQ()); in rshrn2()
5140 NEONShiftImmediateN(vd, vn, shift, NEON_RSHRN); in rshrn2()
5144 void Assembler::sqshrn(const VRegister& vd, const VRegister& vn, int shift) { in sqshrn() argument
5146 VIXL_ASSERT(vd.IsD() || (vn.IsScalar() && vd.IsScalar())); in sqshrn()
5147 NEONShiftImmediateN(vd, vn, shift, NEON_SQSHRN); in sqshrn()
5151 void Assembler::sqshrn2(const VRegister& vd, const VRegister& vn, int shift) { in sqshrn2() argument
5153 VIXL_ASSERT(vn.IsVector() && vd.IsQ()); in sqshrn2()
5154 NEONShiftImmediateN(vd, vn, shift, NEON_SQSHRN); in sqshrn2()
5158 void Assembler::sqrshrn(const VRegister& vd, const VRegister& vn, int shift) { in sqrshrn() argument
5160 VIXL_ASSERT(vd.IsD() || (vn.IsScalar() && vd.IsScalar())); in sqrshrn()
5161 NEONShiftImmediateN(vd, vn, shift, NEON_SQRSHRN); in sqrshrn()
5165 void Assembler::sqrshrn2(const VRegister& vd, const VRegister& vn, int shift) { in sqrshrn2() argument
5167 VIXL_ASSERT(vn.IsVector() && vd.IsQ()); in sqrshrn2()
5168 NEONShiftImmediateN(vd, vn, shift, NEON_SQRSHRN); in sqrshrn2()
5172 void Assembler::sqshrun(const VRegister& vd, const VRegister& vn, int shift) { in sqshrun() argument
5174 VIXL_ASSERT(vd.IsD() || (vn.IsScalar() && vd.IsScalar())); in sqshrun()
5175 NEONShiftImmediateN(vd, vn, shift, NEON_SQSHRUN); in sqshrun()
5179 void Assembler::sqshrun2(const VRegister& vd, const VRegister& vn, int shift) { in sqshrun2() argument
5181 VIXL_ASSERT(vn.IsVector() && vd.IsQ()); in sqshrun2()
5182 NEONShiftImmediateN(vd, vn, shift, NEON_SQSHRUN); in sqshrun2()
5186 void Assembler::sqrshrun(const VRegister& vd, const VRegister& vn, int shift) { in sqrshrun() argument
5188 VIXL_ASSERT(vd.IsD() || (vn.IsScalar() && vd.IsScalar())); in sqrshrun()
5189 NEONShiftImmediateN(vd, vn, shift, NEON_SQRSHRUN); in sqrshrun()
5193 void Assembler::sqrshrun2(const VRegister& vd, const VRegister& vn, int shift) { in sqrshrun2() argument
5195 VIXL_ASSERT(vn.IsVector() && vd.IsQ()); in sqrshrun2()
5196 NEONShiftImmediateN(vd, vn, shift, NEON_SQRSHRUN); in sqrshrun2()
5200 void Assembler::uqshrn(const VRegister& vd, const VRegister& vn, int shift) { in uqshrn() argument
5202 VIXL_ASSERT(vd.IsD() || (vn.IsScalar() && vd.IsScalar())); in uqshrn()
5203 NEONShiftImmediateN(vd, vn, shift, NEON_UQSHRN); in uqshrn()
5207 void Assembler::uqshrn2(const VRegister& vd, const VRegister& vn, int shift) { in uqshrn2() argument
5209 VIXL_ASSERT(vn.IsVector() && vd.IsQ()); in uqshrn2()
5210 NEONShiftImmediateN(vd, vn, shift, NEON_UQSHRN); in uqshrn2()
5214 void Assembler::uqrshrn(const VRegister& vd, const VRegister& vn, int shift) { in uqrshrn() argument
5216 VIXL_ASSERT(vd.IsD() || (vn.IsScalar() && vd.IsScalar())); in uqrshrn()
5217 NEONShiftImmediateN(vd, vn, shift, NEON_UQRSHRN); in uqrshrn()
5221 void Assembler::uqrshrn2(const VRegister& vd, const VRegister& vn, int shift) { in uqrshrn2() argument
5223 VIXL_ASSERT(vn.IsVector() && vd.IsQ()); in uqrshrn2()
5224 NEONShiftImmediateN(vd, vn, shift, NEON_UQRSHRN); in uqrshrn2()
5486 const VRegister& vn, in FPDataProcessing1Source() argument
5489 Emit(FPType(vn) | op | Rn(vn) | Rd(vd)); in FPDataProcessing1Source()
5494 const VRegister& vn, in FPDataProcessing3Source() argument
5499 VIXL_ASSERT(AreSameSizeAndType(vd, vn, vm, va)); in FPDataProcessing3Source()
5500 Emit(FPType(vd) | op | Rm(vm) | Rn(vn) | Rd(vd) | Ra(va)); in FPDataProcessing3Source()