1716   LogicVRegister extendedreg = sxtl2(vform, temp2, src);  in sshll2()
3118 LogicVRegister Simulator::sxtl2(VectorFormat vform,  in sxtl2()  function in vixl::aarch64::Simulator
3521   sxtl2(vform, temp1, src1);  in saddl2()
3522   sxtl2(vform, temp2, src2);  in saddl2()
3544   sxtl2(vform, temp, src2);  in saddw2()
3613   sxtl2(vform, temp1, src1);  in ssubl2()
3614   sxtl2(vform, temp2, src2);  in ssubl2()
3636   sxtl2(vform, temp, src2);  in ssubw2()
3683   sxtl2(vform, temp1, src1);  in sabal2()
3684   sxtl2(vform, temp2, src2);  in sabal2()
3731   sxtl2(vform, temp1, src1);  in sabdl2()
3732   sxtl2(vform, temp2, src2);  in sabdl2()
3779   sxtl2(vform, temp1, src1);  in smull2()
3780   sxtl2(vform, temp2, src2);  in smull2()
3827   sxtl2(vform, temp1, src1);  in smlsl2()
3828   sxtl2(vform, temp2, src2);  in smlsl2()
3875   sxtl2(vform, temp1, src1);  in smlal2()
3876   sxtl2(vform, temp2, src2);  in smlal2()