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Lines Matching refs:zd

757   bool FitsInLane(const CPURegister& zd) const {  in FitsInLane()  argument
758 return FitsInBits(zd.GetLaneSizeInBits()); in FitsInLane()
760 bool FitsInSignedLane(const CPURegister& zd) const { in FitsInSignedLane() argument
761 return IsIntN(zd.GetLaneSizeInBits()); in FitsInSignedLane()
763 bool FitsInUnsignedLane(const CPURegister& zd) const { in FitsInUnsignedLane() argument
764 return IsUintN(zd.GetLaneSizeInBits()); in FitsInUnsignedLane()
799 bool TryEncodeAsShiftedIntNForLane(const CPURegister& zd, T* imm) const { in TryEncodeAsShiftedIntNForLane() argument
801 VIXL_ASSERT(FitsInLane(zd)); in TryEncodeAsShiftedIntNForLane()
821 if (unshifted.IsUintN(zd.GetLaneSizeInBits() - kShift)) { in TryEncodeAsShiftedIntNForLane()
822 int64_t encoded = unshifted.AsIntN(zd.GetLaneSizeInBits() - kShift); in TryEncodeAsShiftedIntNForLane()
839 bool TryEncodeAsShiftedIntNForLane(const CPURegister& zd, in TryEncodeAsShiftedIntNForLane() argument
842 if (TryEncodeAsShiftedIntNForLane<N, kShift>(zd, imm)) { in TryEncodeAsShiftedIntNForLane()
851 bool TryEncodeAsIntNForLane(const CPURegister& zd, T* imm) const { in TryEncodeAsIntNForLane() argument
852 return TryEncodeAsShiftedIntNForLane<N, 0>(zd, imm); in TryEncodeAsIntNForLane()
858 bool TryEncodeAsShiftedUintNForLane(const CPURegister& zd, T* imm) const { in TryEncodeAsShiftedUintNForLane() argument
860 VIXL_ASSERT(FitsInLane(zd)); in TryEncodeAsShiftedUintNForLane()
864 USE(zd); in TryEncodeAsShiftedUintNForLane()
876 bool TryEncodeAsShiftedUintNForLane(const CPURegister& zd, in TryEncodeAsShiftedUintNForLane() argument
879 if (TryEncodeAsShiftedUintNForLane<N, kShift>(zd, imm)) { in TryEncodeAsShiftedUintNForLane()