176                 const CPURegister& reg4,  in AreAliased()  argument
189   const CPURegister regs[] = {reg1, reg2, reg3, reg4, reg5, reg6, reg7, reg8};  in AreAliased()
227                         const CPURegister& reg4,  in AreSameSizeAndType()  argument
236   match &= !reg4.IsValid() || reg4.IsSameSizeAndType(reg1);  in AreSameSizeAndType()
247              const CPURegister& reg4,  in AreEven()  argument
256   even &= !reg4.IsValid() || ((reg4.GetCode() % 2) == 0);  in AreEven()
267                     const CPURegister& reg4) {  in AreConsecutive()  argument
284   if (!reg4.IsValid()) {  in AreConsecutive()
286   } else if (reg4.GetCode() !=  in AreConsecutive()
297                    const CPURegister& reg4) {  in AreSameFormat()  argument
302   match &= !reg4.IsValid() || reg4.IsSameFormat(reg1);  in AreSameFormat()
309                      const CPURegister& reg4) {  in AreSameLaneSize()  argument
317       !reg4.IsValid() || (reg4.GetLaneSizeInBits() == reg1.GetLaneSizeInBits());  in AreSameLaneSize()