Lines Matching refs:vform
412 void SetActive(VectorFormat vform, int lane_index, bool value) { in SetActive() argument
413 int psize = LaneSizeInBytesFromFormat(vform); in SetActive()
421 bool IsActive(VectorFormat vform, int lane_index) const { in IsActive() argument
422 int psize = LaneSizeInBytesFromFormat(vform); in IsActive()
512 int64_t Int(VectorFormat vform, int index) const { in Int() argument
513 if (IsSVEFormat(vform)) register_.NotifyAccessAsZ(); in Int()
515 switch (LaneSizeInBitsFromFormat(vform)) { in Int()
535 uint64_t Uint(VectorFormat vform, int index) const { in Uint() argument
536 if (IsSVEFormat(vform)) register_.NotifyAccessAsZ(); in Uint()
538 switch (LaneSizeInBitsFromFormat(vform)) { in Uint()
558 uint64_t UintLeftJustified(VectorFormat vform, int index) const { in UintLeftJustified() argument
559 return Uint(vform, index) << (64 - LaneSizeInBitsFromFormat(vform)); in UintLeftJustified()
562 int64_t IntLeftJustified(VectorFormat vform, int index) const { in IntLeftJustified() argument
563 uint64_t value = UintLeftJustified(vform, index); in IntLeftJustified()
569 void SetInt(VectorFormat vform, int index, int64_t value) const { in SetInt() argument
570 if (IsSVEFormat(vform)) register_.NotifyAccessAsZ(); in SetInt()
571 switch (LaneSizeInBitsFromFormat(vform)) { in SetInt()
590 void SetIntArray(VectorFormat vform, const int64_t* src) const { in SetIntArray() argument
591 ClearForWrite(vform); in SetIntArray()
592 for (int i = 0; i < LaneCountFromFormat(vform); i++) { in SetIntArray()
593 SetInt(vform, i, src[i]); in SetIntArray()
597 void SetUint(VectorFormat vform, int index, uint64_t value) const { in SetUint() argument
598 if (IsSVEFormat(vform)) register_.NotifyAccessAsZ(); in SetUint()
599 switch (LaneSizeInBitsFromFormat(vform)) { in SetUint()
618 void SetUintArray(VectorFormat vform, const uint64_t* src) const { in SetUintArray() argument
619 ClearForWrite(vform); in SetUintArray()
620 for (int i = 0; i < LaneCountFromFormat(vform); i++) { in SetUintArray()
621 SetUint(vform, i, src[i]); in SetUintArray()
636 void SetFloat(VectorFormat vform, int index, T value) const { in SetFloat() argument
637 if (IsSVEFormat(vform)) register_.NotifyAccessAsZ(); in SetFloat()
643 void ClearForWrite(VectorFormat vform) const { in ClearForWrite() argument
645 if (IsSVEFormat(vform)) return; in ClearForWrite()
647 unsigned size = RegisterSizeInBytesFromFormat(vform); in ClearForWrite()
693 LogicVRegister& SignedSaturate(VectorFormat vform) { in SignedSaturate() argument
694 for (int i = 0; i < LaneCountFromFormat(vform); i++) { in SignedSaturate()
697 SetInt(vform, i, MaxIntFromFormat(vform)); in SignedSaturate()
699 SetInt(vform, i, MinIntFromFormat(vform)); in SignedSaturate()
705 LogicVRegister& UnsignedSaturate(VectorFormat vform) { in UnsignedSaturate() argument
706 for (int i = 0; i < LaneCountFromFormat(vform); i++) { in UnsignedSaturate()
709 SetUint(vform, i, MaxUintFromFormat(vform)); in UnsignedSaturate()
711 SetUint(vform, i, 0); in UnsignedSaturate()
724 LogicVRegister& Round(VectorFormat vform) { in Round() argument
725 for (int i = 0; i < LaneCountFromFormat(vform); i++) { in Round()
726 SetUint(vform, i, Uint(vform, i) + (GetRounding(i) ? 1 : 0)); in Round()
733 LogicVRegister& Uhalve(VectorFormat vform) { in Uhalve() argument
734 for (int i = 0; i < LaneCountFromFormat(vform); i++) { in Uhalve()
735 uint64_t val = Uint(vform, i); in Uhalve()
741 val |= (MaxUintFromFormat(vform) >> 1) + 1; in Uhalve()
743 SetInt(vform, i, val); in Uhalve()
749 LogicVRegister& Halve(VectorFormat vform) { in Halve() argument
750 for (int i = 0; i < LaneCountFromFormat(vform); i++) { in Halve()
751 int64_t val = Int(vform, i); in Halve()
755 SetInt(vform, i, val); in Halve()
760 SetUint(vform, i, uval ^ ((MaxUintFromFormat(vform) >> 1) + 1)); in Halve()
766 int LaneCountFromFormat(VectorFormat vform) const { in LaneCountFromFormat() argument
767 if (IsSVEFormat(vform)) { in LaneCountFromFormat()
768 return register_.GetSizeInBits() / LaneSizeInBitsFromFormat(vform); in LaneCountFromFormat()
770 return vixl::aarch64::LaneCountFromFormat(vform); in LaneCountFromFormat()
820 VectorFormat vform,
827 vector_form_(vform), in base_()
1734 VectorFormat vform,
1737 unsigned msize_in_bytes = LaneSizeInBytesFromFormat(vform);
1738 LoadUintToLane(dst, vform, msize_in_bytes, index, addr);
1742 VectorFormat vform,
1746 dst.SetUint(vform, index, MemReadUint(msize_in_bytes, addr));
1750 VectorFormat vform,
1754 dst.SetInt(vform, index, MemReadInt(msize_in_bytes, addr));
1758 VectorFormat vform,
1761 unsigned msize_in_bytes = LaneSizeInBytesFromFormat(vform);
1762 MemWrite(msize_in_bytes, addr, src.Uint(vform, index));
2079 PrintRegisterFormat GetPrintRegisterFormat(VectorFormat vform);
2080 PrintRegisterFormat GetPrintRegisterFormatFP(VectorFormat vform);
2650 unsigned RegisterSizeInBitsFromFormat(VectorFormat vform) const {
2651 if (IsSVEFormat(vform)) {
2654 return vixl::aarch64::RegisterSizeInBitsFromFormat(vform);
2658 unsigned RegisterSizeInBytesFromFormat(VectorFormat vform) const {
2659 unsigned size_in_bits = RegisterSizeInBitsFromFormat(vform);
2664 int LaneCountFromFormat(VectorFormat vform) const {
2665 if (IsSVEFormat(vform)) {
2666 return GetVectorLengthInBits() / LaneSizeInBitsFromFormat(vform);
2668 return vixl::aarch64::LaneCountFromFormat(vform);
2672 bool IsFirstActive(VectorFormat vform,
2675 for (int i = 0; i < LaneCountFromFormat(vform); i++) {
2676 if (mask.IsActive(vform, i)) {
2677 return bits.IsActive(vform, i);
2683 bool AreNoneActive(VectorFormat vform,
2686 for (int i = 0; i < LaneCountFromFormat(vform); i++) {
2687 if (mask.IsActive(vform, i) && bits.IsActive(vform, i)) {
2694 bool IsLastActive(VectorFormat vform,
2697 for (int i = LaneCountFromFormat(vform) - 1; i >= 0; i--) {
2698 if (mask.IsActive(vform, i)) {
2699 return bits.IsActive(vform, i);
2705 void PredTest(VectorFormat vform,
2708 ReadNzcv().SetN(IsFirstActive(vform, mask, bits));
2709 ReadNzcv().SetZ(AreNoneActive(vform, mask, bits));
2710 ReadNzcv().SetC(!IsLastActive(vform, mask, bits));
2839 void ld1(VectorFormat vform, LogicVRegister dst, uint64_t addr);
2840 void ld1(VectorFormat vform, LogicVRegister dst, int index, uint64_t addr);
2841 void ld1r(VectorFormat vform, LogicVRegister dst, uint64_t addr);
2842 void ld1r(VectorFormat vform,
2847 void ld2(VectorFormat vform,
2851 void ld2(VectorFormat vform,
2856 void ld2r(VectorFormat vform,
2860 void ld3(VectorFormat vform,
2865 void ld3(VectorFormat vform,
2871 void ld3r(VectorFormat vform,
2876 void ld4(VectorFormat vform,
2882 void ld4(VectorFormat vform,
2889 void ld4r(VectorFormat vform,
2895 void st1(VectorFormat vform, LogicVRegister src, uint64_t addr);
2896 void st1(VectorFormat vform, LogicVRegister src, int index, uint64_t addr);
2897 void st2(VectorFormat vform,
2901 void st2(VectorFormat vform,
2906 void st3(VectorFormat vform,
2911 void st3(VectorFormat vform,
2917 void st4(VectorFormat vform,
2923 void st4(VectorFormat vform,
2930 LogicVRegister cmp(VectorFormat vform,
2935 LogicVRegister cmp(VectorFormat vform,
2940 LogicVRegister cmptst(VectorFormat vform,
2944 LogicVRegister add(VectorFormat vform,
2950 LogicVRegister add_uint(VectorFormat vform,
2954 LogicVRegister addp(VectorFormat vform,
2976 LogicVRegister mla(VectorFormat vform,
2982 LogicVRegister mls(VectorFormat vform,
2987 LogicVRegister mul(VectorFormat vform,
2991 LogicVRegister mul(VectorFormat vform,
2996 LogicVRegister mla(VectorFormat vform,
3001 LogicVRegister mls(VectorFormat vform,
3006 LogicVRegister pmul(VectorFormat vform,
3010 LogicVRegister sdiv(VectorFormat vform,
3014 LogicVRegister udiv(VectorFormat vform,
3019 typedef LogicVRegister (Simulator::*ByElementOp)(VectorFormat vform,
3024 LogicVRegister fmul(VectorFormat vform,
3029 LogicVRegister fmla(VectorFormat vform,
3034 LogicVRegister fmlal(VectorFormat vform,
3039 LogicVRegister fmlal2(VectorFormat vform,
3044 LogicVRegister fmls(VectorFormat vform,
3049 LogicVRegister fmlsl(VectorFormat vform,
3054 LogicVRegister fmlsl2(VectorFormat vform,
3059 LogicVRegister fmulx(VectorFormat vform,
3064 LogicVRegister smulh(VectorFormat vform,
3068 LogicVRegister smull(VectorFormat vform,
3073 LogicVRegister smull2(VectorFormat vform,
3078 LogicVRegister umull(VectorFormat vform,
3083 LogicVRegister umull2(VectorFormat vform,
3088 LogicVRegister smlal(VectorFormat vform,
3093 LogicVRegister smlal2(VectorFormat vform,
3098 LogicVRegister umlal(VectorFormat vform,
3103 LogicVRegister umlal2(VectorFormat vform,
3108 LogicVRegister smlsl(VectorFormat vform,
3113 LogicVRegister smlsl2(VectorFormat vform,
3118 LogicVRegister umlsl(VectorFormat vform,
3123 LogicVRegister umlsl2(VectorFormat vform,
3128 LogicVRegister umulh(VectorFormat vform,
3132 LogicVRegister sqdmull(VectorFormat vform,
3137 LogicVRegister sqdmull2(VectorFormat vform,
3142 LogicVRegister sqdmlal(VectorFormat vform,
3147 LogicVRegister sqdmlal2(VectorFormat vform,
3152 LogicVRegister sqdmlsl(VectorFormat vform,
3157 LogicVRegister sqdmlsl2(VectorFormat vform,
3162 LogicVRegister sqdmulh(VectorFormat vform,
3167 LogicVRegister sqrdmulh(VectorFormat vform,
3172 LogicVRegister sdot(VectorFormat vform,
3177 LogicVRegister sqrdmlah(VectorFormat vform,
3182 LogicVRegister udot(VectorFormat vform,
3187 LogicVRegister sqrdmlsh(VectorFormat vform,
3192 LogicVRegister sub(VectorFormat vform,
3198 LogicVRegister sub_uint(VectorFormat vform,
3202 LogicVRegister and_(VectorFormat vform,
3206 LogicVRegister orr(VectorFormat vform,
3210 LogicVRegister orn(VectorFormat vform,
3214 LogicVRegister eor(VectorFormat vform,
3218 LogicVRegister bic(VectorFormat vform,
3222 LogicVRegister bic(VectorFormat vform,
3226 LogicVRegister bif(VectorFormat vform,
3230 LogicVRegister bit(VectorFormat vform,
3234 LogicVRegister bsl(VectorFormat vform,
3238 LogicVRegister cls(VectorFormat vform,
3241 LogicVRegister clz(VectorFormat vform,
3244 LogicVRegister cnot(VectorFormat vform,
3247 LogicVRegister cnt(VectorFormat vform,
3250 LogicVRegister not_(VectorFormat vform,
3253 LogicVRegister rbit(VectorFormat vform,
3256 LogicVRegister rev(VectorFormat vform,
3259 LogicVRegister rev_byte(VectorFormat vform,
3263 LogicVRegister rev16(VectorFormat vform,
3266 LogicVRegister rev32(VectorFormat vform,
3269 LogicVRegister rev64(VectorFormat vform,
3272 LogicVRegister addlp(VectorFormat vform,
3277 LogicVRegister saddlp(VectorFormat vform,
3280 LogicVRegister uaddlp(VectorFormat vform,
3283 LogicVRegister sadalp(VectorFormat vform,
3286 LogicVRegister uadalp(VectorFormat vform,
3289 LogicVRegister ext(VectorFormat vform,
3295 LogicVRegister fcadd(VectorFormat vform,
3300 LogicVRegister fcadd(VectorFormat vform,
3306 LogicVRegister fcmla(VectorFormat vform,
3313 LogicVRegister fcmla(VectorFormat vform,
3319 LogicVRegister fcmla(VectorFormat vform,
3326 LogicVRegister fadda(VectorFormat vform,
3330 LogicVRegister fadda(VectorFormat vform,
3334 LogicVRegister index(VectorFormat vform,
3338 LogicVRegister ins_element(VectorFormat vform,
3343 LogicVRegister ins_immediate(VectorFormat vform,
3347 LogicVRegister insr(VectorFormat vform, LogicVRegister dst, uint64_t imm);
3348 LogicVRegister dup_element(VectorFormat vform,
3352 LogicVRegister dup_elements_to_segments(VectorFormat vform,
3356 LogicVRegister dup_immediate(VectorFormat vform,
3359 LogicVRegister mov(VectorFormat vform,
3363 LogicVRegister mov_merging(VectorFormat vform,
3367 LogicVRegister mov_zeroing(VectorFormat vform,
3377 LogicVRegister movi(VectorFormat vform, LogicVRegister dst, uint64_t imm);
3378 LogicVRegister mvni(VectorFormat vform, LogicVRegister dst, uint64_t imm);
3379 LogicVRegister orr(VectorFormat vform,
3383 LogicVRegister sshl(VectorFormat vform,
3387 LogicVRegister ushl(VectorFormat vform,
3395 std::pair<bool, uint64_t> clast(VectorFormat vform,
3399 LogicVRegister compact(VectorFormat vform,
3403 LogicVRegister splice(VectorFormat vform,
3408 LogicVRegister sel(VectorFormat vform,
3417 LogicVRegister sminmax(VectorFormat vform,
3422 LogicVRegister smax(VectorFormat vform,
3426 LogicVRegister smin(VectorFormat vform,
3430 LogicVRegister sminmaxp(VectorFormat vform,
3435 LogicVRegister smaxp(VectorFormat vform,
3439 LogicVRegister sminp(VectorFormat vform,
3443 LogicVRegister addp(VectorFormat vform,
3446 LogicVRegister addv(VectorFormat vform,
3449 LogicVRegister uaddlv(VectorFormat vform,
3452 LogicVRegister saddlv(VectorFormat vform,
3455 LogicVRegister sminmaxv(VectorFormat vform,
3460 LogicVRegister smaxv(VectorFormat vform,
3463 LogicVRegister sminv(VectorFormat vform,
3466 LogicVRegister uxtl(VectorFormat vform,
3469 LogicVRegister uxtl2(VectorFormat vform,
3472 LogicVRegister sxtl(VectorFormat vform,
3475 LogicVRegister sxtl2(VectorFormat vform,
3478 LogicVRegister uxt(VectorFormat vform,
3482 LogicVRegister sxt(VectorFormat vform,
3486 LogicVRegister tbl(VectorFormat vform,
3490 LogicVRegister tbl(VectorFormat vform,
3495 LogicVRegister tbl(VectorFormat vform,
3501 LogicVRegister tbl(VectorFormat vform,
3508 LogicVRegister Table(VectorFormat vform,
3512 LogicVRegister Table(VectorFormat vform,
3520 LogicVRegister tbx(VectorFormat vform,
3524 LogicVRegister tbx(VectorFormat vform,
3529 LogicVRegister tbx(VectorFormat vform,
3535 LogicVRegister tbx(VectorFormat vform,
3542 LogicVRegister uaddl(VectorFormat vform,
3546 LogicVRegister uaddl2(VectorFormat vform,
3550 LogicVRegister uaddw(VectorFormat vform,
3554 LogicVRegister uaddw2(VectorFormat vform,
3558 LogicVRegister saddl(VectorFormat vform,
3562 LogicVRegister saddl2(VectorFormat vform,
3566 LogicVRegister saddw(VectorFormat vform,
3570 LogicVRegister saddw2(VectorFormat vform,
3574 LogicVRegister usubl(VectorFormat vform,
3578 LogicVRegister usubl2(VectorFormat vform,
3582 LogicVRegister usubw(VectorFormat vform,
3586 LogicVRegister usubw2(VectorFormat vform,
3590 LogicVRegister ssubl(VectorFormat vform,
3594 LogicVRegister ssubl2(VectorFormat vform,
3598 LogicVRegister ssubw(VectorFormat vform,
3602 LogicVRegister ssubw2(VectorFormat vform,
3606 LogicVRegister uminmax(VectorFormat vform,
3611 LogicVRegister umax(VectorFormat vform,
3615 LogicVRegister umin(VectorFormat vform,
3619 LogicVRegister uminmaxp(VectorFormat vform,
3624 LogicVRegister umaxp(VectorFormat vform,
3628 LogicVRegister uminp(VectorFormat vform,
3632 LogicVRegister uminmaxv(VectorFormat vform,
3637 LogicVRegister umaxv(VectorFormat vform,
3640 LogicVRegister uminv(VectorFormat vform,
3643 LogicVRegister trn1(VectorFormat vform,
3647 LogicVRegister trn2(VectorFormat vform,
3651 LogicVRegister zip1(VectorFormat vform,
3655 LogicVRegister zip2(VectorFormat vform,
3659 LogicVRegister uzp1(VectorFormat vform,
3663 LogicVRegister uzp2(VectorFormat vform,
3667 LogicVRegister shl(VectorFormat vform,
3671 LogicVRegister scvtf(VectorFormat vform,
3679 LogicVRegister scvtf(VectorFormat vform,
3684 LogicVRegister ucvtf(VectorFormat vform,
3692 LogicVRegister ucvtf(VectorFormat vform,
3697 LogicVRegister sshll(VectorFormat vform,
3701 LogicVRegister sshll2(VectorFormat vform,
3705 LogicVRegister shll(VectorFormat vform,
3708 LogicVRegister shll2(VectorFormat vform,
3711 LogicVRegister ushll(VectorFormat vform,
3715 LogicVRegister ushll2(VectorFormat vform,
3719 LogicVRegister sli(VectorFormat vform,
3723 LogicVRegister sri(VectorFormat vform,
3727 LogicVRegister sshr(VectorFormat vform,
3731 LogicVRegister ushr(VectorFormat vform,
3735 LogicVRegister ssra(VectorFormat vform,
3739 LogicVRegister usra(VectorFormat vform,
3743 LogicVRegister srsra(VectorFormat vform,
3747 LogicVRegister ursra(VectorFormat vform,
3751 LogicVRegister suqadd(VectorFormat vform,
3754 LogicVRegister usqadd(VectorFormat vform,
3757 LogicVRegister sqshl(VectorFormat vform,
3761 LogicVRegister uqshl(VectorFormat vform,
3765 LogicVRegister sqshlu(VectorFormat vform,
3769 LogicVRegister abs(VectorFormat vform,
3772 LogicVRegister neg(VectorFormat vform,
3775 LogicVRegister extractnarrow(VectorFormat vform,
3780 LogicVRegister xtn(VectorFormat vform,
3783 LogicVRegister sqxtn(VectorFormat vform,
3786 LogicVRegister uqxtn(VectorFormat vform,
3789 LogicVRegister sqxtun(VectorFormat vform,
3792 LogicVRegister absdiff(VectorFormat vform,
3797 LogicVRegister saba(VectorFormat vform,
3801 LogicVRegister uaba(VectorFormat vform,
3805 LogicVRegister shrn(VectorFormat vform,
3809 LogicVRegister shrn2(VectorFormat vform,
3813 LogicVRegister rshrn(VectorFormat vform,
3817 LogicVRegister rshrn2(VectorFormat vform,
3821 LogicVRegister uqshrn(VectorFormat vform,
3825 LogicVRegister uqshrn2(VectorFormat vform,
3829 LogicVRegister uqrshrn(VectorFormat vform,
3833 LogicVRegister uqrshrn2(VectorFormat vform,
3837 LogicVRegister sqshrn(VectorFormat vform,
3841 LogicVRegister sqshrn2(VectorFormat vform,
3845 LogicVRegister sqrshrn(VectorFormat vform,
3849 LogicVRegister sqrshrn2(VectorFormat vform,
3853 LogicVRegister sqshrun(VectorFormat vform,
3857 LogicVRegister sqshrun2(VectorFormat vform,
3861 LogicVRegister sqrshrun(VectorFormat vform,
3865 LogicVRegister sqrshrun2(VectorFormat vform,
3869 LogicVRegister sqrdmulh(VectorFormat vform,
3874 LogicVRegister dot(VectorFormat vform,
3879 LogicVRegister sdot(VectorFormat vform,
3883 LogicVRegister udot(VectorFormat vform,
3887 LogicVRegister sqrdmlash(VectorFormat vform,
3893 LogicVRegister sqrdmlah(VectorFormat vform,
3898 LogicVRegister sqrdmlsh(VectorFormat vform,
3903 LogicVRegister sqdmulh(VectorFormat vform,
3946 LogicVRegister FXN(VectorFormat vform, \
3966 LogicVRegister FN(VectorFormat vform, \
3970 LogicVRegister FN(VectorFormat vform, \
3985 LogicVRegister FNP(VectorFormat vform, \
3989 LogicVRegister FNP(VectorFormat vform, \
4002 LogicVRegister frecps(VectorFormat vform,
4006 LogicVRegister frecps(VectorFormat vform,
4011 LogicVRegister frsqrts(VectorFormat vform,
4015 LogicVRegister frsqrts(VectorFormat vform,
4020 LogicVRegister fmla(VectorFormat vform,
4025 LogicVRegister fmla(VectorFormat vform,
4031 LogicVRegister fmls(VectorFormat vform,
4036 LogicVRegister fmls(VectorFormat vform,
4041 LogicVRegister fnmul(VectorFormat vform,
4046 LogicVRegister fmlal(VectorFormat vform,
4050 LogicVRegister fmlal2(VectorFormat vform,
4054 LogicVRegister fmlsl(VectorFormat vform,
4058 LogicVRegister fmlsl2(VectorFormat vform,
4064 LogicVRegister fcmp(VectorFormat vform,
4069 LogicVRegister fcmp(VectorFormat vform,
4074 LogicVRegister fabscmp(VectorFormat vform,
4079 LogicVRegister fcmp_zero(VectorFormat vform,
4085 LogicVRegister fneg(VectorFormat vform,
4088 LogicVRegister fneg(VectorFormat vform,
4092 LogicVRegister frecpx(VectorFormat vform,
4095 LogicVRegister frecpx(VectorFormat vform,
4098 LogicVRegister ftsmul(VectorFormat vform,
4102 LogicVRegister ftssel(VectorFormat vform,
4106 LogicVRegister ftmad(VectorFormat vform,
4111 LogicVRegister fexpa(VectorFormat vform,
4115 LogicVRegister fscale(VectorFormat vform,
4119 LogicVRegister fscale(VectorFormat vform,
4124 LogicVRegister fabs_(VectorFormat vform,
4127 LogicVRegister fabs_(VectorFormat vform,
4130 LogicVRegister fabd(VectorFormat vform,
4134 LogicVRegister frint(VectorFormat vform,
4140 LogicVRegister fcvt(VectorFormat vform,
4146 LogicVRegister fcvts(VectorFormat vform,
4154 LogicVRegister fcvts(VectorFormat vform,
4159 LogicVRegister fcvtu(VectorFormat vform,
4167 LogicVRegister fcvtu(VectorFormat vform,
4172 LogicVRegister fcvtl(VectorFormat vform,
4175 LogicVRegister fcvtl2(VectorFormat vform,
4178 LogicVRegister fcvtn(VectorFormat vform,
4181 LogicVRegister fcvtn2(VectorFormat vform,
4184 LogicVRegister fcvtxn(VectorFormat vform,
4187 LogicVRegister fcvtxn2(VectorFormat vform,
4190 LogicVRegister fsqrt(VectorFormat vform,
4193 LogicVRegister frsqrte(VectorFormat vform,
4196 LogicVRegister frecpe(VectorFormat vform,
4200 LogicVRegister ursqrte(VectorFormat vform,
4203 LogicVRegister urecpe(VectorFormat vform,
4211 LogicPRegister ptrue(VectorFormat vform, LogicPRegister dst, int pattern);
4212 LogicPRegister pnext(VectorFormat vform,
4217 LogicVRegister asrd(VectorFormat vform,
4222 LogicVRegister andv(VectorFormat vform,
4226 LogicVRegister eorv(VectorFormat vform,
4230 LogicVRegister orv(VectorFormat vform,
4234 LogicVRegister saddv(VectorFormat vform,
4238 LogicVRegister sminv(VectorFormat vform,
4242 LogicVRegister smaxv(VectorFormat vform,
4246 LogicVRegister uaddv(VectorFormat vform,
4250 LogicVRegister uminv(VectorFormat vform,
4254 LogicVRegister umaxv(VectorFormat vform,
4265 LogicVRegister FPPairedAcrossHelper(VectorFormat vform,
4272 VectorFormat vform,
4280 LogicVRegister fminv(VectorFormat vform,
4283 LogicVRegister fmaxv(VectorFormat vform,
4286 LogicVRegister fminnmv(VectorFormat vform,
4289 LogicVRegister fmaxnmv(VectorFormat vform,
4292 LogicVRegister faddv(VectorFormat vform,
4408 VectorFormat vform,
4419 VectorFormat vform,
4424 LogicVRegister unpk(VectorFormat vform,
4431 VectorFormat vform,
4440 VectorFormat vform,
4449 void SVEStructuredStoreHelper(VectorFormat vform,
4454 void SVEStructuredLoadHelper(VectorFormat vform,
4480 void SVEFaultTolerantLoadHelper(VectorFormat vform,
4488 VectorFormat vform,
4495 LogicVRegister FTMaddHelper(VectorFormat vform,
4503 int GetFirstActive(VectorFormat vform, const LogicPRegister& pg) const;
4504 int GetLastActive(VectorFormat vform, const LogicPRegister& pg) const;
4506 int CountActiveLanes(VectorFormat vform, const LogicPRegister& pg) const;
4509 int CountActiveAndTrueLanes(VectorFormat vform,
4516 int GetPredicateConstraintLaneCount(VectorFormat vform, int pattern) const;
4690 void ExtractFromSimVRegister(VectorFormat vform,