Lines Matching refs:fpreg
225 const VRegister& fpreg) { in EqualFP16() argument
226 VIXL_ASSERT(fpreg.Is16Bits()); in EqualFP16()
229 uint64_t result_64 = core->dreg_bits(fpreg.GetCode()); in EqualFP16()
237 return EqualFP16(expected, core, core->hreg(fpreg.GetCode())); in EqualFP16()
243 const VRegister& fpreg) { in EqualFP32() argument
244 VIXL_ASSERT(fpreg.Is32Bits()); in EqualFP32()
247 uint64_t result_64 = core->dreg_bits(fpreg.GetCode()); in EqualFP32()
256 return EqualFP32(expected, core, core->sreg(fpreg.GetCode())); in EqualFP32()
262 const VRegister& fpreg) { in EqualFP64() argument
263 VIXL_ASSERT(fpreg.Is64Bits()); in EqualFP64()
264 return EqualFP64(expected, core, core->dreg(fpreg.GetCode())); in EqualFP64()