00@P@PPAPPBPPCPPDPPEPPFPPGPPHPPRPPSPPTPPUPPVPPWPPXPPYPPZP P`P!PaP"PbP#PcP$PdP%PeP&PfP(PhP)PiP*PjP+PkP,PlP-PmP.PnP/PoP0PpP1PqP2PrP3PsP4PtP5PuP6PvP7PwP8PxP9PyP:PzP;P{PPPPPPPPPPPPPPPPPPPPPPPPPPPPHPPPPPPPPPPPPPPPPPPPPPPPPPPPPPPPPPPPPP@ABCDEFGHRSTU `*j+k,lu.D u0PD u>PD u\`aD ua7pD u5u3PuQ`u_`u0p TME_FAILURE_CHECK_ERROR::TME failure cause mismatch! Exp_Cause:%x Act_Cause:0x%lx (Exp_dest_reg=0x%lx, Act_dest_reg=0x%lx) TME_FAILURE_CHECK_ERROR::TME failure rtry mismatch! Exp_Retry:%x Act_Retry:0x%lx (Exp_dest_reg=0x%lx, Act_dest_reg=0x%lx) TME_FAILURE_CHECK_ERROR::TM tcancel reason mismatch!Exp_Reason:%x Act_Reason:0x%lx (Exp_dest_reg=0x%lx, Act_dest_reg=0x%lx) TEST_INEFFECTIVENESS_ERROR::TME failed with IMP/SIZE cause(Xd = 0x%lx) TME_PE_STATE_CHECK_ERROR::PE expected to be in TM state but found in NON-TM state NONTM_PE_STATE_CHECK_ERROR::PE expected to be in NON-TM state but found in TM state (TTEST X%d = 0x%x) TME PART PASS TME PART FAIL TCANCEL #(0x%x) instruction did not cancel the transaction at tm_cancel_%d TEST_INFO: This test exercises TM instructions and verifies the expected behavior. Test may fail withPE state mismatch (transactional or non-transactional state) TCANCEL instruction expected behavior mismatch or TM failure with mismatched cause reporting TCANCEL #(0x%x) instruction did not cancel the transaction at tm_cancel_%d Execution of TCOMMIT_%d in non-tm state didnt result in sync exception Exception Code mismatch when NON-TM TCOMMIT execution at part_%d! Expected EC:0x%lx Actual EC:0x%lx TEST_INFO: This test exercises TCOMMIT instructions in NON-TM mode and expects sync exception Test may fail with Exception code mismatch or TCOMMIT expected behavior mismatch where no exception observed Test failure due to speculative TCANCEL #0x%x (x%d=0x%x) in mispredicted path canceled the transaction Test failure due to speculative TSTART X%d (0x%x) in mispredicted path changed PE state to TM mode Test failed due to speculative svc/hvc/smc in mispredicted path failed the transaction Test failed due to speculative brk instruction in mispredicted path failed the transaction Test failed due to speculative tlbi alle1 instruction in mispredicted path failed the transaction Test failed due to speculative at s1e0r,x1 instruction in mispredicted path failed the transaction Test failed due to speculative ic/dc ivac instruction in mispredicted path failed the transaction Test failed due to speculative dsb/esb instruction in mispredicted path failed the transaction TEST_INFO: This test exercises and verfies the PE state after execution of TME instruction in mispredicted path Forbidden instruction inside TM did not fail the transaction at tm_start_%d Specuative read to MUT address not expected to be cached! and time taken for different access Timing details: Tx=%d, Ty=%d, Tz=%d PE expected to be in Open access state on TM entry between LDXR and STXR, mismatch observed PE expected to be in Open access state on TM exit between LDXR and STXR, mismatch observed PE expected to be in Open access state on EmptyTM between LDXR and STXR, mismatch observed PE expected to be in Open access state upon clrex between LDXR and STXR, mismatch observed TEST_INFO: This test exercises TM Entry and exit conditions b/w LDXR and STXR instructions Test may fail with PE monitor state mismatch or TM failure with IMP cause PE expected to be in Open access state on TM Entry/Exit/Cancel between LDXR and STXR, mismatch observed PE global monitor state is transisition not expected on TM Entry/Exit/Cancel from another PE TEST_INFO: This test exercisesGlobal monitor state unchanged upon TM entry/exit/cancel from different PE Test may fail with PE global monitor state mismatch or TM failure with IMP cause Unique MUT location values observed at CPU%d = %d (total observation attempts = %d) Containment failure observed at CPU%d and last valid value observed = %x No Unique MUT location values observed at CPU%d = %d (total observation attempts = %d) WFE failure observed at CPU%d = %d (total wfe attempts = %d) No Unique MUT location value observed at CPU%d = %d (total observation attempts = %d) Unique MUT location values observed at CPU%d = %d (total observation attempts = %d) Noninterfernce failure observed at CPU%d and last valid value observed = %x Load mismatch observed at CPU%d and last valid loads observed load1= %x load2= %x Load X mismatch observed at CPU%d and last valid loads observed load1= %x load2= %x Load Y mismatch observed at CPU%d and last valid loads observed load1= %x load2= %x No Unique MUT location value observed at CPU%d = %d (total observation attempts = %d) TME_MEM_CHECK_ERROR: Memory writes mismatch Address: 0x%x Expected Value 0x%x Actual Value : 0x%x TME_COMMIT_ERROR: TM was expected to fail/cancel but TM commit observed TME_NEST_FLATTENDED_ERROR: Nested transaction failure was not reported to outermost destination register. Inner transaction number failed : %d TME_NEST_OBSERVER_ERROR: Changes of outer transaction was not visible to inner level transaction TME_NEST_DEPTH_OVRF_ERROR: Transaction did not fail after crossing max nesting depth limit TM_PE_STATE_CHECK_ERROR: PE expected to be in Nested Transactional state TME_ROLLBACK_ERROR: TME didnot rollback on failure when TSTART+4 instruction start next transaction TME_ERET_ERROR: ERET execution in TME resulted in branch to elr TME_SVE_SKIP: Skipping the part because SVE is not implemented TME_FP_SKIP: Skipping the part because FP is not implemented TME_FFR_ERROR: FFR checks failed TME_ZREG_ERROR: Register Check fail for Z register. Iter. no.: %d, ZReg: %d, Expected:%lx, Actual:%lx TME_PREG_ERROR: Register Check fail for P register. Iter. no.: %d, PReg: %d, Expected:%lx, Actual:%lx TME_VREG_ERROR: Register Check fail for V register. Iter. no.: %d, VReg: %d, Expected:%lx, Actual:%lx TME_NONTM_WR_OBS_ERROR: NONTM vector writes were not observed in tm at address: %0x TME_NOT_IN_EL3_SKIP: Skipping the part because it is applicable only if test is executed in EL < EL3 TME_IS_IN_EL0_SKIP: Skipping the part because it is applicable only if test is executed in EL > EL0 TME_NOT_IN_NS_SKIP: Skipping the part because it is applicable only if test is executed in EL is NON-SECURE TME_NOT_IN_EL0_SKIP: Skipping the part because it is applicable only if test is executed in EL0 TME_NOT_IN_EL1s_SKIP: Skipping the part because it is applicable only if test is executed in S-EL1 TME_NOT_IN_EL01_SKIP: Skipping the part because it is applicable only if test is executed in EL0 or EL1 TME_NOT_IN_EL1_SKIP: Skipping the part because it is applicable only if test is executed in EL1 TME_NOT_IN_EL1SKIP: Skipping the part because it is applicable only if test is executed in EL1 Secure State TME_NOT_IN_E2H_TGE_SKIP: Skipping the part because it is not applicable when test is executed with {E2H,TGE=1,1} TME_NOT_IN_NON_SECURE_STATE: Skipping the part because current EL is not in Non-Secure State TME_NOT_IN_SECURE_STATE: Skipping the part because current EL is not in Secure State TME_IS_GT_EL1_SKIP: Skipping the part because it is applicable only if current EL <= EL1 TME_IS_GT_EL1s_SKIP: Skipping the part because it is applicable only if current EL <= EL1 and in Secure State TME_NOT_IN_EL2s_SKIP: Skipping the part because EL2 is not in Secure State TME_NOT_IN_EL2_SKIP: Skipping the part because EL2 is not implemented TME_NOT_IN_EL3_SKIP: Skipping the part because EL3 is not implemented TME_NOT_IN_EL23_SKIP: Skipping the part because both EL2 and EL3 is not implemented TME_FPTRAP_SKIP: Skipping the part because DUT does not support traps on FP Exception TME_EXT_ABORT_SKIP: Skipping the part because STR_NORMAL_WB_ABORT_BEHAVE != SEA TME_EXT_ABORT_SKIP: Skipping the part because LOAD_NORMAL_WB_ABORT_BEHAVE != SEA TME_EXT_ABORT_SKIP: Skipping the part because FETCH_NORMAL_WB_ABORT_BEHAVE != SEA TEST_INEFFECTIVENESS_ERROR: Synchronous External Abort not generated for Transactional Store at 0x%x TEST_INFO: This test exercises allowed a64 instructions inside TM and expected TM to commit successfull Test may fail with TM failure with various cause or IMP cause where test is ineffective TEST_INFO: This test exercises forbidden a64 instructions inside TM and expected TM to fail Test may fail with TM commit due to forbidden condition not causing TM failure or IMP cause where test will be ineffective Instruction modification observed at CPU%d = %d (total observation attempts = %x) Instruction modification mismatch observed at CPU%d and last valid value observed = %x Code conflict observed at CPU%d = %d (total observation attempts = %x) Dependency-order-before/Address dependency violated, expected memory value = %d and actual memory value = %d Dependency-order-before/control dependency violated, expected memory value = %d and actual memory value = %d Dependency-order-before/data dependency violated, expected memory value = %d and actual memory value = %d Atomic-order-before/different address violated, expected memory value = %d and actual memory value = %d Barrier-order-before/dmb sy violated, expected memory value = %d and actual memory value = %d Barrier-order-before/acquire,release violated, expected memory value = %d and actual memory value = %d Barrier-order-before/dmb ld violated, expected memory value = %d and actual memory value = %d Barrier-order-before/acquire violated, expected memory value = %d and actual memory value = %d Barrier-order-before/dmb st violated, expected memory value = %d and actual memory value = %d Barrier-order-before/release violated, expected memory value = %d and actual memory value = %d Atomic-order-before/different address test ineffective due to exclusive failure TEST_INFO: This test exercises ordering and observability cases inside TM Test exercises DOB (Dependency-order-Before) AOB (Address-order-Before)BOB (Barrier-order-Before) ordering rules Test may fail with ordering violations or IMP cause where test will be ineffective TEST_INFO: This test exercises commit atomicity where memory locations modified inside TM and registers updated inside TM are verfied against the modified values after TCOMMIT Test may fail with memory or register update mismatch or IMP cause Where test will be ineffective TEST_INFO: This test exercises commit atomicity where SVE register updated inside TM are verified against the update values after TCOMMIT Test may fail with register update mismatch or IMP cause Where test will be ineffective TEST_INFO: This test exercises different memory attribute access inside TM and verify the commited memory effect or rollback effect in case of unsupported attribute inside TM Test may fail with memory mismatch or IMP failure due to unsupported memory access inside TM TEST_INFO: This test exercises nested transaction cases Transaction failure at different nest level and flattend commit atomicity at different nesting levels max nest depth testing Test may fail with memory mismath or cause mismatch or IMP cause where test will be ineffective TEST_INFO: This test exercises different register (X/V) and system register update inside TM and perform rollback checks when TM fails Test may fail with register value mismatch or IMP cause where test will be ineffective TEST_INFO: This test exercisesdifferent sve register (Z/P) update inside TM and perform rollback checks when TM fails Test may fail with register value mismatch or IMP cause where test will be ineffective TEST_INFO: This test exercises various sync exception generation cases inside TM and verifies the TM failure cause Test may fail with cause mismatch or IMP cause where test will be ineffective TEST_INFO: This test exercises asizef sync exception generation cases inside TM and verifies the TM failure cause Test may fail with cause mismatch or IMP cause where test will be ineffective TEST_INFO: This test exercises sync exception when SVE instructions access inside TM and verifies the TM failure cause Test may fail with cause mismatch or IMP cause where test will be ineffective TME_MESSAGE_PASSING_INEFFECTIVENESS:: Unique MUT location values observed at CPU%d = %d (total observation attempts = %d) TME_MESSAGE_PASSING_FAILURE:: Ordering observation voilation where Loc_X > Loc_Y(Loc_X=%d and Loc_Y=%d) TME_SVE_MEM: Transaction cancelled due to failure of Z-reg visibility from inner to outer transaction, 0x%x TME_SVE_MEM: PE was expected to complete transaction but it Failed with cause = 0x%x TME_SVE_MEM: PE was expected to FAIL transaction with cause = 0x%x, but it Succeded! TME_SVE_MEM_INEFFECTIVE: VectorOp[%d], Expected Active Elements Count : %d, Actual Active Elements Count = %d TME_SYS_REG: Sys Reg access Check Failed TME_SYS_REG: MSR Sys Reg Write check failed, Expected Value : %d, Actual value = %d TME_SYS_REG: MSR Sys Reg Write side effect check failed, Expected Value : %d, Actual value = %d TME_SYS_REG: PE was expected to FAIL transaction with cause = 0x%x, but it Succeded! TME_SYS_REG: Unexpected Exception Observed! TME_ADR_TRAN: PE was expected to FAIL transaction with cause = 0x%x, but it Succeded! TME_ADR_TRAN: Memory read mismatch @Address: 0x%x, Expected Value 0x%x, Actual Value : 0x%x TME_ADR_TRAN: Memory write mismatch @Addr: 0x%x, (@Alias Addr: 0x%x), Exp Val 0x%x, Actual Value : 0x%x TME_ADR_TRAN: AF Flag Not Set in Leaf Descriptor ( 0x%x ) for Transactional access of Memory @ 0x%x TME_ADR_TRAN: AP2 Flag Not Cleared in Leaf Descriptor ( 0x%x ) for Transactional access of Memory @ 0x%x TME_ADR_TRAN: HCR_EL2_E2H mismatch: Expected Value 0 ACtual Value 1 TME_ADR_TRAN: HCR_EL2_E2H mismatch: Expected Value 1 ACtual Value 0 TME_ADR_TRAN: Hardware updates to Access flag not Supported TME_ADR_TRAN: Hardware updates to Access flag and Dirty state not Supported TME_SH_DBG: PE was expected to FAIL transaction with cause = %d, but it Succeded! TME_INTERRUPT: Interrupt setup Failed TME_INTERRUPT: PE was expected to FAIL transaction with cause = 0x%x, but it Succeded! TME_INTERRUPT: PE was expected to Succeed transaction but failed with cause = 0x%x TME_INTERRUPT: Transaction Loop Count Check Failed, Expected Value = 0x%x, Actual Value = 0x%x TME_INTERRUPT: Unexpected Interrupt Event, TX_INTERRUPT_FLAG Exp Val: 0x%x, Actual Value : 0x%x TME_INTERRUPT: No Interrupt received, TX_INTERRUPT_FLAG Exp Val: 0x%x, Actual Value : 0x%x TME_INTERRUPT: Interrupt Gen Clean Failed with status : 0x%x TME_INTERRUPT: Interrupt Gen Stop Failed with status : 0x%x TME_INTERRUPT: X reg restore didn't succeed after transaction failure DC conflict observed at CPU%d = %d (total observation attempts = %x) Prefetch conflict observed at CPU%d = %d (total observation attempts = %x) TME_PMU: Skipping the part because PMU is not implemented TME_PMU: Skipping the part because implemented PMUVer is not supported TME_PMU: Skipping the part because Minimum PMU counters not available TME_PMU_ERROR: PMU Event Code (0x%x), PMU Counter Number ( %d), PMU Counter Expected Value: %d, Actual Value : %d TME_PMU_INEFFECTIVE: PMU Event Code (0x%x), PMU Counter Number ( %d), PMU Counter Expected Value: Non-zero, Actual Value : %d TME_PMU_ERROR: PMU Event Code (0x%x), PMU Counter Number ( %d), Overflow Status: Expected Value: %d, Actual Value : %d TME_MTE_ERROR: Tag Store Failed: Expected Tag Value: 0x%x, Actual Tag Value : 0x%x TME_MTE_ERROR: Tag ReStore Failed for Failed/Cancelled Transaction. Expected Tag Value: 0x%x, Actual Tag Value : 0x%x TME_MTE_ERROR: Checked Access failed Expected Mem Value: 0x%x, Actual Mem Value : 0x%x TME_MTE: PE was expected to complete transaction but it Failed with cause = 0x%x TME_MTE: PE was expected to FAIL transaction with cause = 0x%x, but it Succeded! TME_MTE: Tag Check Fail Asynchronous status not captured! TME_ENABLE_CONTROL: UNDEFINED Exception not generated !! TME_ENABLE_CONTROL: TME Undefined Exception: Expected ID_AA64ISAR0_EL1.TME = 0x0, Actual Value 0x%x !! TME_ENABLE_CONTROL: TME TRAP Exception: Expected EC Value = 0x1b, Actual EC Value 0x%x !! TME_ENABLE_CONTROL: Transaction Succeeded but was expected to fail with cause = 0x%x TME_BTI: Skipping part because BTI is not implemented TME_MEM_CONFLICT: Transaction Succeeded but was expected to fail with cause = 0x%x TME_MEM_CONFLICT: Transaction was expected to Fail with cause = 0x%x TME_MEM_CONFLICT: Transaction failure cause mismatch, Expected cause = 0x%x, Actual cause = 0x%x TME_RESET: Resume after Reset TME_SIMPLE_ISA TME_FAILURE_CHECK_ERROR::TME failure cause mismatch! Exp_Cause:%x Act_Cause:0x%lx (Exp_dest_reg=0x%lx, Act_dest_reg=0x%lx) TME_FAILURE_CHECK_ERROR::TME failure rtry mismatch! Exp_Retry:%x Act_Retry:0x%lx (Exp_dest_reg=0x%lx, Act_dest_reg=0x%lx) TME_FAILURE_CHECK_ERROR::TM tcancel reason mismatch!Exp_Reason:%x Act_Reason:0x%lx (Exp_dest_reg=0x%lx, Act_dest_reg=0x%lx) TEST_INEFFECTIVENESS_ERROR::TME failed with IMP/SIZE cause(Xd = 0x%lx) TME_PE_STATE_CHECK_ERROR::PE expected to be in TM state but found in NON-TM state NONTM_PE_STATE_CHECK_ERROR::PE expected to be in NON-TM state but found in TM state (TTEST X%d = 0x%x) TME PART PASS TME PART FAIL TCANCEL #(0x%x) instruction did not cancel the transaction at tm_cancel_%d TEST_INFO: This test exercises TM instructions and verifies the expected behavior. Test may fail withPE state mismatch (transactional or non-transactional state) TCANCEL instruction expected behavior mismatch or TM failure with mismatched cause reporting TCANCEL #(0x%x) instruction did not cancel the transaction at tm_cancel_%d Execution of TCOMMIT_%d in non-tm state didnt result in sync exception Exception Code mismatch when NON-TM TCOMMIT execution at part_%d! Expected EC:0x%lx Actual EC:0x%lx TEST_INFO: This test exercises TCOMMIT instructions in NON-TM mode and expects sync exception Test may fail with Exception code mismatch or TCOMMIT expected behavior mismatch where no exception observed Test failure due to speculative TCANCEL #0x%x (x%d=0x%x) in mispredicted path canceled the transaction Test failure due to speculative TSTART X%d (0x%x) in mispredicted path changed PE state to TM mode Test failed due to speculative svc/hvc/smc in mispredicted path failed the transaction Test failed due to speculative brk instruction in mispredicted path failed the transaction Test failed due to speculative tlbi alle1 instruction in mispredicted path failed the transaction Test failed due to speculative at s1e0r,x1 instruction in mispredicted path failed the transaction Test failed due to speculative ic/dc ivac instruction in mispredicted path failed the transaction Test failed due to speculative dsb/esb instruction in mispredicted path failed the transaction TEST_INFO: This test exercises and verfies the PE state after execution of TME instruction in mispredicted path Forbidden instruction inside TM did not fail the transaction at tm_start_%d Specuative read to MUT address not expected to be cached! and time taken for different access Timing details: Tx=%d, Ty=%d, Tz=%d PE expected to be in Open access state on TM entry between LDXR and STXR, mismatch observed PE expected to be in Open access state on TM exit between LDXR and STXR, mismatch observed PE expected to be in Open access state on EmptyTM between LDXR and STXR, mismatch observed PE expected to be in Open access state upon clrex between LDXR and STXR, mismatch observed TEST_INFO: This test exercises TM Entry and exit conditions b/w LDXR and STXR instructions Test may fail with PE monitor state mismatch or TM failure with IMP cause PE expected to be in Open access state on TM Entry/Exit/Cancel between LDXR and STXR, mismatch observed PE global monitor state is transisition not expected on TM Entry/Exit/Cancel from another PE TEST_INFO: This test exercisesGlobal monitor state unchanged upon TM entry/exit/cancel from different PE Test may fail with PE global monitor state mismatch or TM failure with IMP cause Unique MUT location values observed at CPU%d = %d (total observation attempts = %d) Containment failure observed at CPU%d and last valid value observed = %x No Unique MUT location values observed at CPU%d = %d (total observation attempts = %d) WFE failure observed at CPU%d = %d (total wfe attempts = %d) No Unique MUT location value observed at CPU%d = %d (total observation attempts = %d) Unique MUT location values observed at CPU%d = %d (total observation attempts = %d) Noninterfernce failure observed at CPU%d and last valid value observed = %x Load mismatch observed at CPU%d and last valid loads observed load1= %x load2= %x Load X mismatch observed at CPU%d and last valid loads observed load1= %x load2= %x Load Y mismatch observed at CPU%d and last valid loads observed load1= %x load2= %x No Unique MUT location value observed at CPU%d = %d (total observation attempts = %d) TME_MEM_CHECK_ERROR: Memory writes mismatch Address: 0x%x Expected Value 0x%x Actual Value : 0x%x TME_COMMIT_ERROR: TM was expected to fail/cancel but TM commit observed TME_NEST_FLATTENDED_ERROR: Nested transaction failure was not reported to outermost destination register. Inner transaction number failed : %d TME_NEST_OBSERVER_ERROR: Changes of outer transaction was not visible to inner level transaction TME_NEST_DEPTH_OVRF_ERROR: Transaction did not fail after crossing max nesting depth limit TM_PE_STATE_CHECK_ERROR: PE expected to be in Nested Transactional state TME_ROLLBACK_ERROR: TME didnot rollback on failure when TSTART+4 instruction start next transaction TME_ERET_ERROR: ERET execution in TME resulted in branch to elr TME_SVE_SKIP: Skipping the part because SVE is not implemented TME_FP_SKIP: Skipping the part because FP is not implemented TME_FFR_ERROR: FFR checks failed TME_ZREG_ERROR: Register Check fail for Z register. Iter. no.: %d, ZReg: %d, Expected:%lx, Actual:%lx TME_PREG_ERROR: Register Check fail for P register. Iter. no.: %d, PReg: %d, Expected:%lx, Actual:%lx TME_VREG_ERROR: Register Check fail for V register. Iter. no.: %d, VReg: %d, Expected:%lx, Actual:%lx TME_NONTM_WR_OBS_ERROR: NONTM vector writes were not observed in tm at address: %0x TME_NOT_IN_EL3_SKIP: Skipping the part because it is applicable only if test is executed in EL < EL3 TME_IS_IN_EL0_SKIP: Skipping the part because it is applicable only if test is executed in EL > EL0 TME_NOT_IN_NS_SKIP: Skipping the part because it is applicable only if test is executed in EL is NON-SECURE TME_NOT_IN_EL0_SKIP: Skipping the part because it is applicable only if test is executed in EL0 TME_NOT_IN_EL1s_SKIP: Skipping the part because it is applicable only if test is executed in S-EL1 TME_NOT_IN_EL01_SKIP: Skipping the part because it is applicable only if test is executed in EL0 or EL1 TME_NOT_IN_EL1_SKIP: Skipping the part because it is applicable only if test is executed in EL1 TME_NOT_IN_EL1SKIP: Skipping the part because it is applicable only if test is executed in EL1 Secure State TME_NOT_IN_E2H_TGE_SKIP: Skipping the part because it is not applicable when test is executed with {E2H,TGE=1,1} TME_NOT_IN_NON_SECURE_STATE: Skipping the part because current EL is not in Non-Secure State TME_NOT_IN_SECURE_STATE: Skipping the part because current EL is not in Secure State TME_IS_GT_EL1_SKIP: Skipping the part because it is applicable only if current EL <= EL1 TME_IS_GT_EL1s_SKIP: Skipping the part because it is applicable only if current EL <= EL1 and in Secure State TME_NOT_IN_EL2s_SKIP: Skipping the part because EL2 is not in Secure State TME_NOT_IN_EL2_SKIP: Skipping the part because EL2 is not implemented TME_NOT_IN_EL3_SKIP: Skipping the part because EL3 is not implemented TME_NOT_IN_EL23_SKIP: Skipping the part because both EL2 and EL3 is not implemented TME_FPTRAP_SKIP: Skipping the part because DUT does not support traps on FP Exception TME_EXT_ABORT_SKIP: Skipping the part because STR_NORMAL_WB_ABORT_BEHAVE != SEA TME_EXT_ABORT_SKIP: Skipping the part because LOAD_NORMAL_WB_ABORT_BEHAVE != SEA TME_EXT_ABORT_SKIP: Skipping the part because FETCH_NORMAL_WB_ABORT_BEHAVE != SEA TEST_INEFFECTIVENESS_ERROR: Synchronous External Abort not generated for Transactional Store at 0x%x TEST_INFO: This test exercises allowed a64 instructions inside TM and expected TM to commit successfull Test may fail with TM failure with various cause or IMP cause where test is ineffective TEST_INFO: This test exercises forbidden a64 instructions inside TM and expected TM to fail Test may fail with TM commit due to forbidden condition not causing TM failure or IMP cause where test will be ineffective Instruction modification observed at CPU%d = %d (total observation attempts = %x) Instruction modification mismatch observed at CPU%d and last valid value observed = %x Code conflict observed at CPU%d = %d (total observation attempts = %x) Dependency-order-before/Address dependency violated, expected memory value = %d and actual memory value = %d Dependency-order-before/control dependency violated, expected memory value = %d and actual memory value = %d Dependency-order-before/data dependency violated, expected memory value = %d and actual memory value = %d Atomic-order-before/different address violated, expected memory value = %d and actual memory value = %d Barrier-order-before/dmb sy violated, expected memory value = %d and actual memory value = %d Barrier-order-before/acquire,release violated, expected memory value = %d and actual memory value = %d Barrier-order-before/dmb ld violated, expected memory value = %d and actual memory value = %d Barrier-order-before/acquire violated, expected memory value = %d and actual memory value = %d Barrier-order-before/dmb st violated, expected memory value = %d and actual memory value = %d Barrier-order-before/release violated, expected memory value = %d and actual memory value = %d Atomic-order-before/different address test ineffective due to exclusive failure TEST_INFO: This test exercises ordering and observability cases inside TM Test exercises DOB (Dependency-order-Before) AOB (Address-order-Before)BOB (Barrier-order-Before) ordering rules Test may fail with ordering violations or IMP cause where test will be ineffective TEST_INFO: This test exercises commit atomicity where memory locations modified inside TM and registers updated inside TM are verfied against the modified values after TCOMMIT Test may fail with memory or register update mismatch or IMP cause Where test will be ineffective TEST_INFO: This test exercises commit atomicity where SVE register updated inside TM are verified against the update values after TCOMMIT Test may fail with register update mismatch or IMP cause Where test will be ineffective TEST_INFO: This test exercises different memory attribute access inside TM and verify the commited memory effect or rollback effect in case of unsupported attribute inside TM Test may fail with memory mismatch or IMP failure due to unsupported memory access inside TM TEST_INFO: This test exercises nested transaction cases Transaction failure at different nest level and flattend commit atomicity at different nesting levels max nest depth testing Test may fail with memory mismath or cause mismatch or IMP cause where test will be ineffective TEST_INFO: This test exercises different register (X/V) and system register update inside TM and perform rollback checks when TM fails Test may fail with register value mismatch or IMP cause where test will be ineffective TEST_INFO: This test exercisesdifferent sve register (Z/P) update inside TM and perform rollback checks when TM fails Test may fail with register value mismatch or IMP cause where test will be ineffective TEST_INFO: This test exercises various sync exception generation cases inside TM and verifies the TM failure cause Test may fail with cause mismatch or IMP cause where test will be ineffective TEST_INFO: This test exercises asizef sync exception generation cases inside TM and verifies the TM failure cause Test may fail with cause mismatch or IMP cause where test will be ineffective TEST_INFO: This test exercises sync exception when SVE instructions access inside TM and verifies the TM failure cause Test may fail with cause mismatch or IMP cause where test will be ineffective TME_MESSAGE_PASSING_INEFFECTIVENESS:: Unique MUT location values observed at CPU%d = %d (total observation attempts = %d) TME_MESSAGE_PASSING_FAILURE:: Ordering observation voilation where Loc_X > Loc_Y(Loc_X=%d and Loc_Y=%d) TME_SVE_MEM: Transaction cancelled due to failure of Z-reg visibility from inner to outer transaction, 0x%x TME_SVE_MEM: PE was expected to complete transaction but it Failed with cause = 0x%x TME_SVE_MEM: PE was expected to FAIL transaction with cause = 0x%x, but it Succeded! TME_SVE_MEM_INEFFECTIVE: VectorOp[%d], Expected Active Elements Count : %d, Actual Active Elements Count = %d TME_SYS_REG: Sys Reg access Check Failed TME_SYS_REG: MSR Sys Reg Write check failed, Expected Value : %d, Actual value = %d TME_SYS_REG: MSR Sys Reg Write side effect check failed, Expected Value : %d, Actual value = %d TME_SYS_REG: PE was expected to FAIL transaction with cause = 0x%x, but it Succeded! TME_SYS_REG: Unexpected Exception Observed! TME_ADR_TRAN: PE was expected to FAIL transaction with cause = 0x%x, but it Succeded! TME_ADR_TRAN: Memory read mismatch @Address: 0x%x, Expected Value 0x%x, Actual Value : 0x%x TME_ADR_TRAN: Memory write mismatch @Addr: 0x%x, (@Alias Addr: 0x%x), Exp Val 0x%x, Actual Value : 0x%x TME_ADR_TRAN: AF Flag Not Set in Leaf Descriptor ( 0x%x ) for Transactional access of Memory @ 0x%x TME_ADR_TRAN: AP2 Flag Not Cleared in Leaf Descriptor ( 0x%x ) for Transactional access of Memory @ 0x%x TME_ADR_TRAN: HCR_EL2_E2H mismatch: Expected Value 0 ACtual Value 1 TME_ADR_TRAN: HCR_EL2_E2H mismatch: Expected Value 1 ACtual Value 0 TME_ADR_TRAN: Hardware updates to Access flag not Supported TME_ADR_TRAN: Hardware updates to Access flag and Dirty state not Supported TME_SH_DBG: PE was expected to FAIL transaction with cause = %d, but it Succeded! TME_INTERRUPT: Interrupt setup Failed TME_INTERRUPT: PE was expected to FAIL transaction with cause = 0x%x, but it Succeded! TME_INTERRUPT: PE was expected to Succeed transaction but failed with cause = 0x%x TME_INTERRUPT: Transaction Loop Count Check Failed, Expected Value = 0x%x, Actual Value = 0x%x TME_INTERRUPT: Unexpected Interrupt Event, TX_INTERRUPT_FLAG Exp Val: 0x%x, Actual Value : 0x%x TME_INTERRUPT: No Interrupt received, TX_INTERRUPT_FLAG Exp Val: 0x%x, Actual Value : 0x%x TME_INTERRUPT: Interrupt Gen Clean Failed with status : 0x%x TME_INTERRUPT: Interrupt Gen Stop Failed with status : 0x%x TME_INTERRUPT: X reg restore didn't succeed after transaction failure DC conflict observed at CPU%d = %d (total observation attempts = %x) Prefetch conflict observed at CPU%d = %d (total observation attempts = %x) TME_PMU: Skipping the part because PMU is not implemented TME_PMU: Skipping the part because implemented PMUVer is not supported TME_PMU: Skipping the part because Minimum PMU counters not available TME_PMU_ERROR: PMU Event Code (0x%x), PMU Counter Number ( %d), PMU Counter Expected Value: %d, Actual Value : %d TME_PMU_INEFFECTIVE: PMU Event Code (0x%x), PMU Counter Number ( %d), PMU Counter Expected Value: Non-zero, Actual Value : %d TME_PMU_ERROR: PMU Event Code (0x%x), PMU Counter Number ( %d), Overflow Status: Expected Value: %d, Actual Value : %d TME_MTE_ERROR: Tag Store Failed: Expected Tag Value: 0x%x, Actual Tag Value : 0x%x TME_MTE_ERROR: Tag ReStore Failed for Failed/Cancelled Transaction. Expected Tag Value: 0x%x, Actual Tag Value : 0x%x TME_MTE_ERROR: Checked Access failed Expected Mem Value: 0x%x, Actual Mem Value : 0x%x TME_MTE: PE was expected to complete transaction but it Failed with cause = 0x%x TME_MTE: PE was expected to FAIL transaction with cause = 0x%x, but it Succeded! TME_MTE: Tag Check Fail Asynchronous status not captured! TME_ENABLE_CONTROL: UNDEFINED Exception not generated !! TME_ENABLE_CONTROL: TME Undefined Exception: Expected ID_AA64ISAR0_EL1.TME = 0x0, Actual Value 0x%x !! TME_ENABLE_CONTROL: TME TRAP Exception: Expected EC Value = 0x1b, Actual EC Value 0x%x !! TME_ENABLE_CONTROL: Transaction Succeeded but was expected to fail with cause = 0x%x TME_BTI: Skipping part because BTI is not implemented TME_MEM_CONFLICT: Transaction Succeeded but was expected to fail with cause = 0x%x TME_MEM_CONFLICT: Transaction was expected to Fail with cause = 0x%x TME_MEM_CONFLICT: Transaction failure cause mismatch, Expected cause = 0x%x, Actual cause = 0x%x TME_RESET: Resume after Reset TME_FAILURE_CHECK_ERROR::TME failure cause mismatch! Exp_Cause:%x Act_Cause:0x%lx (Exp_dest_reg=0x%lx, Act_dest_reg=0x%lx) TME_FAILURE_CHECK_ERROR::TME failure rtry mismatch! Exp_Retry:%x Act_Retry:0x%lx (Exp_dest_reg=0x%lx, Act_dest_reg=0x%lx) TME_FAILURE_CHECK_ERROR::TM tcancel reason mismatch!Exp_Reason:%x Act_Reason:0x%lx (Exp_dest_reg=0x%lx, Act_dest_reg=0x%lx) TEST_INEFFECTIVENESS_ERROR::TME failed with IMP/SIZE cause(Xd = 0x%lx) TME_PE_STATE_CHECK_ERROR::PE expected to be in TM state but found in NON-TM state NONTM_PE_STATE_CHECK_ERROR::PE expected to be in NON-TM state but found in TM state (TTEST X%d = 0x%x) TME PART PASS TME PART FAIL TCANCEL #(0x%x) instruction did not cancel the transaction at tm_cancel_%d TEST_INFO: This test exercises TM instructions and verifies the expected behavior. Test may fail withPE state mismatch (transactional or non-transactional state) TCANCEL instruction expected behavior mismatch or TM failure with mismatched cause reporting TCANCEL #(0x%x) instruction did not cancel the transaction at tm_cancel_%d Execution of TCOMMIT_%d in non-tm state didnt result in sync exception Exception Code mismatch when NON-TM TCOMMIT execution at part_%d! Expected EC:0x%lx Actual EC:0x%lx TEST_INFO: This test exercises TCOMMIT instructions in NON-TM mode and expects sync exception Test may fail with Exception code mismatch or TCOMMIT expected behavior mismatch where no exception observed Test failure due to speculative TCANCEL #0x%x (x%d=0x%x) in mispredicted path canceled the transaction Test failure due to speculative TSTART X%d (0x%x) in mispredicted path changed PE state to TM mode Test failed due to speculative svc/hvc/smc in mispredicted path failed the transaction Test failed due to speculative brk instruction in mispredicted path failed the transaction Test failed due to speculative tlbi alle1 instruction in mispredicted path failed the transaction Test failed due to speculative at s1e0r,x1 instruction in mispredicted path failed the transaction Test failed due to speculative ic/dc ivac instruction in mispredicted path failed the transaction Test failed due to speculative dsb/esb instruction in mispredicted path failed the transaction TEST_INFO: This test exercises and verfies the PE state after execution of TME instruction in mispredicted path Forbidden instruction inside TM did not fail the transaction at tm_start_%d Specuative read to MUT address not expected to be cached! and time taken for different access Timing details: Tx=%d, Ty=%d, Tz=%d PE expected to be in Open access state on TM entry between LDXR and STXR, mismatch observed PE expected to be in Open access state on TM exit between LDXR and STXR, mismatch observed PE expected to be in Open access state on EmptyTM between LDXR and STXR, mismatch observed PE expected to be in Open access state upon clrex between LDXR and STXR, mismatch observed TEST_INFO: This test exercises TM Entry and exit conditions b/w LDXR and STXR instructions Test may fail with PE monitor state mismatch or TM failure with IMP cause PE expected to be in Open access state on TM Entry/Exit/Cancel between LDXR and STXR, mismatch observed PE global monitor state is transisition not expected on TM Entry/Exit/Cancel from another PE TEST_INFO: This test exercisesGlobal monitor state unchanged upon TM entry/exit/cancel from different PE Test may fail with PE global monitor state mismatch or TM failure with IMP cause Unique MUT location values observed at CPU%d = %d (total observation attempts = %d) Containment failure observed at CPU%d and last valid value observed = %x No Unique MUT location values observed at CPU%d = %d (total observation attempts = %d) WFE failure observed at CPU%d = %d (total wfe attempts = %d) No Unique MUT location value observed at CPU%d = %d (total observation attempts = %d) Unique MUT location values observed at CPU%d = %d (total observation attempts = %d) Noninterfernce failure observed at CPU%d and last valid value observed = %x Load mismatch observed at CPU%d and last valid loads observed load1= %x load2= %x Load X mismatch observed at CPU%d and last valid loads observed load1= %x load2= %x Load Y mismatch observed at CPU%d and last valid loads observed load1= %x load2= %x No Unique MUT location value observed at CPU%d = %d (total observation attempts = %d) TME_MEM_CHECK_ERROR: Memory writes mismatch Address: 0x%x Expected Value 0x%x Actual Value : 0x%x TME_COMMIT_ERROR: TM was expected to fail/cancel but TM commit observed TME_NEST_FLATTENDED_ERROR: Nested transaction failure was not reported to outermost destination register. Inner transaction number failed : %d TME_NEST_OBSERVER_ERROR: Changes of outer transaction was not visible to inner level transaction TME_NEST_DEPTH_OVRF_ERROR: Transaction did not fail after crossing max nesting depth limit TM_PE_STATE_CHECK_ERROR: PE expected to be in Nested Transactional state TME_ROLLBACK_ERROR: TME didnot rollback on failure when TSTART+4 instruction start next transaction TME_ERET_ERROR: ERET execution in TME resulted in branch to elr TME_SVE_SKIP: Skipping the part because SVE is not implemented TME_FP_SKIP: Skipping the part because FP is not implemented TME_FFR_ERROR: FFR checks failed TME_ZREG_ERROR: Register Check fail for Z register. Iter. no.: %d, ZReg: %d, Expected:%lx, Actual:%lx TME_PREG_ERROR: Register Check fail for P register. Iter. no.: %d, PReg: %d, Expected:%lx, Actual:%lx TME_VREG_ERROR: Register Check fail for V register. Iter. no.: %d, VReg: %d, Expected:%lx, Actual:%lx TME_NONTM_WR_OBS_ERROR: NONTM vector writes were not observed in tm at address: %0x TME_NOT_IN_EL3_SKIP: Skipping the part because it is applicable only if test is executed in EL < EL3 TME_IS_IN_EL0_SKIP: Skipping the part because it is applicable only if test is executed in EL > EL0 TME_NOT_IN_NS_SKIP: Skipping the part because it is applicable only if test is executed in EL is NON-SECURE TME_NOT_IN_EL0_SKIP: Skipping the part because it is applicable only if test is executed in EL0 TME_NOT_IN_EL1s_SKIP: Skipping the part because it is applicable only if test is executed in S-EL1 TME_NOT_IN_EL01_SKIP: Skipping the part because it is applicable only if test is executed in EL0 or EL1 TME_NOT_IN_EL1_SKIP: Skipping the part because it is applicable only if test is executed in EL1 TME_NOT_IN_EL1SKIP: Skipping the part because it is applicable only if test is executed in EL1 Secure State TME_NOT_IN_E2H_TGE_SKIP: Skipping the part because it is not applicable when test is executed with {E2H,TGE=1,1} TME_NOT_IN_NON_SECURE_STATE: Skipping the part because current EL is not in Non-Secure State TME_NOT_IN_SECURE_STATE: Skipping the part because current EL is not in Secure State TME_IS_GT_EL1_SKIP: Skipping the part because it is applicable only if current EL <= EL1 TME_IS_GT_EL1s_SKIP: Skipping the part because it is applicable only if current EL <= EL1 and in Secure State TME_NOT_IN_EL2s_SKIP: Skipping the part because EL2 is not in Secure State TME_NOT_IN_EL2_SKIP: Skipping the part because EL2 is not implemented TME_NOT_IN_EL3_SKIP: Skipping the part because EL3 is not implemented TME_NOT_IN_EL23_SKIP: Skipping the part because both EL2 and EL3 is not implemented TME_FPTRAP_SKIP: Skipping the part because DUT does not support traps on FP Exception TME_EXT_ABORT_SKIP: Skipping the part because STR_NORMAL_WB_ABORT_BEHAVE != SEA TME_EXT_ABORT_SKIP: Skipping the part because LOAD_NORMAL_WB_ABORT_BEHAVE != SEA TME_EXT_ABORT_SKIP: Skipping the part because FETCH_NORMAL_WB_ABORT_BEHAVE != SEA TEST_INEFFECTIVENESS_ERROR: Synchronous External Abort not generated for Transactional Store at 0x%x TEST_INFO: This test exercises allowed a64 instructions inside TM and expected TM to commit successfull Test may fail with TM failure with various cause or IMP cause where test is ineffective TEST_INFO: This test exercises forbidden a64 instructions inside TM and expected TM to fail Test may fail with TM commit due to forbidden condition not causing TM failure or IMP cause where test will be ineffective Instruction modification observed at CPU%d = %d (total observation attempts = %x) Instruction modification mismatch observed at CPU%d and last valid value observed = %x Code conflict observed at CPU%d = %d (total observation attempts = %x) Dependency-order-before/Address dependency violated, expected memory value = %d and actual memory value = %d Dependency-order-before/control dependency violated, expected memory value = %d and actual memory value = %d Dependency-order-before/data dependency violated, expected memory value = %d and actual memory value = %d Atomic-order-before/different address violated, expected memory value = %d and actual memory value = %d Barrier-order-before/dmb sy violated, expected memory value = %d and actual memory value = %d Barrier-order-before/acquire,release violated, expected memory value = %d and actual memory value = %d Barrier-order-before/dmb ld violated, expected memory value = %d and actual memory value = %d Barrier-order-before/acquire violated, expected memory value = %d and actual memory value = %d Barrier-order-before/dmb st violated, expected memory value = %d and actual memory value = %d Barrier-order-before/release violated, expected memory value = %d and actual memory value = %d Atomic-order-before/different address test ineffective due to exclusive failure TEST_INFO: This test exercises ordering and observability cases inside TM Test exercises DOB (Dependency-order-Before) AOB (Address-order-Before)BOB (Barrier-order-Before) ordering rules Test may fail with ordering violations or IMP cause where test will be ineffective TEST_INFO: This test exercises commit atomicity where memory locations modified inside TM and registers updated inside TM are verfied against the modified values after TCOMMIT Test may fail with memory or register update mismatch or IMP cause Where test will be ineffective TEST_INFO: This test exercises commit atomicity where SVE register updated inside TM are verified against the update values after TCOMMIT Test may fail with register update mismatch or IMP cause Where test will be ineffective TEST_INFO: This test exercises different memory attribute access inside TM and verify the commited memory effect or rollback effect in case of unsupported attribute inside TM Test may fail with memory mismatch or IMP failure due to unsupported memory access inside TM TEST_INFO: This test exercises nested transaction cases Transaction failure at different nest level and flattend commit atomicity at different nesting levels max nest depth testing Test may fail with memory mismath or cause mismatch or IMP cause where test will be ineffective TEST_INFO: This test exercises different register (X/V) and system register update inside TM and perform rollback checks when TM fails Test may fail with register value mismatch or IMP cause where test will be ineffective TEST_INFO: This test exercisesdifferent sve register (Z/P) update inside TM and perform rollback checks when TM fails Test may fail with register value mismatch or IMP cause where test will be ineffective TEST_INFO: This test exercises various sync exception generation cases inside TM and verifies the TM failure cause Test may fail with cause mismatch or IMP cause where test will be ineffective TEST_INFO: This test exercises asizef sync exception generation cases inside TM and verifies the TM failure cause Test may fail with cause mismatch or IMP cause where test will be ineffective TEST_INFO: This test exercises sync exception when SVE instructions access inside TM and verifies the TM failure cause Test may fail with cause mismatch or IMP cause where test will be ineffective TME_MESSAGE_PASSING_INEFFECTIVENESS:: Unique MUT location values observed at CPU%d = %d (total observation attempts = %d) TME_MESSAGE_PASSING_FAILURE:: Ordering observation voilation where Loc_X > Loc_Y(Loc_X=%d and Loc_Y=%d) TME_SVE_MEM: Transaction cancelled due to failure of Z-reg visibility from inner to outer transaction, 0x%x TME_SVE_MEM: PE was expected to complete transaction but it Failed with cause = 0x%x TME_SVE_MEM: PE was expected to FAIL transaction with cause = 0x%x, but it Succeded! TME_SVE_MEM_INEFFECTIVE: VectorOp[%d], Expected Active Elements Count : %d, Actual Active Elements Count = %d TME_SYS_REG: Sys Reg access Check Failed TME_SYS_REG: MSR Sys Reg Write check failed, Expected Value : %d, Actual value = %d TME_SYS_REG: MSR Sys Reg Write side effect check failed, Expected Value : %d, Actual value = %d TME_SYS_REG: PE was expected to FAIL transaction with cause = 0x%x, but it Succeded! TME_SYS_REG: Unexpected Exception Observed! TME_ADR_TRAN: PE was expected to FAIL transaction with cause = 0x%x, but it Succeded! TME_ADR_TRAN: Memory read mismatch @Address: 0x%x, Expected Value 0x%x, Actual Value : 0x%x TME_ADR_TRAN: Memory write mismatch @Addr: 0x%x, (@Alias Addr: 0x%x), Exp Val 0x%x, Actual Value : 0x%x TME_ADR_TRAN: AF Flag Not Set in Leaf Descriptor ( 0x%x ) for Transactional access of Memory @ 0x%x TME_ADR_TRAN: AP2 Flag Not Cleared in Leaf Descriptor ( 0x%x ) for Transactional access of Memory @ 0x%x TME_ADR_TRAN: HCR_EL2_E2H mismatch: Expected Value 0 ACtual Value 1 TME_ADR_TRAN: HCR_EL2_E2H mismatch: Expected Value 1 ACtual Value 0 TME_ADR_TRAN: Hardware updates to Access flag not Supported TME_ADR_TRAN: Hardware updates to Access flag and Dirty state not Supported TME_SH_DBG: PE was expected to FAIL transaction with cause = %d, but it Succeded! TME_INTERRUPT: Interrupt setup Failed TME_INTERRUPT: PE was expected to FAIL transaction with cause = 0x%x, but it Succeded! TME_INTERRUPT: PE was expected to Succeed transaction but failed with cause = 0x%x TME_INTERRUPT: Transaction Loop Count Check Failed, Expected Value = 0x%x, Actual Value = 0x%x TME_INTERRUPT: Unexpected Interrupt Event, TX_INTERRUPT_FLAG Exp Val: 0x%x, Actual Value : 0x%x TME_INTERRUPT: No Interrupt received, TX_INTERRUPT_FLAG Exp Val: 0x%x, Actual Value : 0x%x TME_INTERRUPT: Interrupt Gen Clean Failed with status : 0x%x TME_INTERRUPT: Interrupt Gen Stop Failed with status : 0x%x TME_INTERRUPT: X reg restore didn't succeed after transaction failure DC conflict observed at CPU%d = %d (total observation attempts = %x) Prefetch conflict observed at CPU%d = %d (total observation attempts = %x) TME_PMU: Skipping the part because PMU is not implemented TME_PMU: Skipping the part because implemented PMUVer is not supported TME_PMU: Skipping the part because Minimum PMU counters not available TME_PMU_ERROR: PMU Event Code (0x%x), PMU Counter Number ( %d), PMU Counter Expected Value: %d, Actual Value : %d TME_PMU_INEFFECTIVE: PMU Event Code (0x%x), PMU Counter Number ( %d), PMU Counter Expected Value: Non-zero, Actual Value : %d TME_PMU_ERROR: PMU Event Code (0x%x), PMU Counter Number ( %d), Overflow Status: Expected Value: %d, Actual Value : %d TME_MTE_ERROR: Tag Store Failed: Expected Tag Value: 0x%x, Actual Tag Value : 0x%x TME_MTE_ERROR: Tag ReStore Failed for Failed/Cancelled Transaction. Expected Tag Value: 0x%x, Actual Tag Value : 0x%x TME_MTE_ERROR: Checked Access failed Expected Mem Value: 0x%x, Actual Mem Value : 0x%x TME_MTE: PE was expected to complete transaction but it Failed with cause = 0x%x TME_MTE: PE was expected to FAIL transaction with cause = 0x%x, but it Succeded! TME_MTE: Tag Check Fail Asynchronous status not captured! TME_ENABLE_CONTROL: UNDEFINED Exception not generated !! TME_ENABLE_CONTROL: TME Undefined Exception: Expected ID_AA64ISAR0_EL1.TME = 0x0, Actual Value 0x%x !! TME_ENABLE_CONTROL: TME TRAP Exception: Expected EC Value = 0x1b, Actual EC Value 0x%x !! TME_ENABLE_CONTROL: Transaction Succeeded but was expected to fail with cause = 0x%x TME_BTI: Skipping part because BTI is not implemented TME_MEM_CONFLICT: Transaction Succeeded but was expected to fail with cause = 0x%x TME_MEM_CONFLICT: Transaction was expected to Fail with cause = 0x%x TME_MEM_CONFLICT: Transaction failure cause mismatch, Expected cause = 0x%x, Actual cause = 0x%x TME_RESET: Resume after Reset TME_FAILURE_CHECK_ERROR::TME failure cause mismatch! Exp_Cause:%x Act_Cause:0x%lx (Exp_dest_reg=0x%lx, Act_dest_reg=0x%lx) TME_FAILURE_CHECK_ERROR::TME failure rtry mismatch! Exp_Retry:%x Act_Retry:0x%lx (Exp_dest_reg=0x%lx, Act_dest_reg=0x%lx) TME_FAILURE_CHECK_ERROR::TM tcancel reason mismatch!Exp_Reason:%x Act_Reason:0x%lx (Exp_dest_reg=0x%lx, Act_dest_reg=0x%lx) TEST_INEFFECTIVENESS_ERROR::TME failed with IMP/SIZE cause(Xd = 0x%lx) TME_PE_STATE_CHECK_ERROR::PE expected to be in TM state but found in NON-TM state NONTM_PE_STATE_CHECK_ERROR::PE expected to be in NON-TM state but found in TM state (TTEST X%d = 0x%x) TME PART PASS TME PART FAIL TCANCEL #(0x%x) instruction did not cancel the transaction at tm_cancel_%d TEST_INFO: This test exercises TM instructions and verifies the expected behavior. Test may fail withPE state mismatch (transactional or non-transactional state) TCANCEL instruction expected behavior mismatch or TM failure with mismatched cause reporting TCANCEL #(0x%x) instruction did not cancel the transaction at tm_cancel_%d Execution of TCOMMIT_%d in non-tm state didnt result in sync exception Exception Code mismatch when NON-TM TCOMMIT execution at part_%d! Expected EC:0x%lx Actual EC:0x%lx TEST_INFO: This test exercises TCOMMIT instructions in NON-TM mode and expects sync exception Test may fail with Exception code mismatch or TCOMMIT expected behavior mismatch where no exception observed Test failure due to speculative TCANCEL #0x%x (x%d=0x%x) in mispredicted path canceled the transaction Test failure due to speculative TSTART X%d (0x%x) in mispredicted path changed PE state to TM mode Test failed due to speculative svc/hvc/smc in mispredicted path failed the transaction Test failed due to speculative brk instruction in mispredicted path failed the transaction Test failed due to speculative tlbi alle1 instruction in mispredicted path failed the transaction Test failed due to speculative at s1e0r,x1 instruction in mispredicted path failed the transaction Test failed due to speculative ic/dc ivac instruction in mispredicted path failed the transaction Test failed due to speculative dsb/esb instruction in mispredicted path failed the transaction TEST_INFO: This test exercises and verfies the PE state after execution of TME instruction in mispredicted path Forbidden instruction inside TM did not fail the transaction at tm_start_%d Specuative read to MUT address not expected to be cached! and time taken for different access Timing details: Tx=%d, Ty=%d, Tz=%d PE expected to be in Open access state on TM entry between LDXR and STXR, mismatch observed PE expected to be in Open access state on TM exit between LDXR and STXR, mismatch observed PE expected to be in Open access state on EmptyTM between LDXR and STXR, mismatch observed PE expected to be in Open access state upon clrex between LDXR and STXR, mismatch observed TEST_INFO: This test exercises TM Entry and exit conditions b/w LDXR and STXR instructions Test may fail with PE monitor state mismatch or TM failure with IMP cause PE expected to be in Open access state on TM Entry/Exit/Cancel between LDXR and STXR, mismatch observed PE global monitor state is transisition not expected on TM Entry/Exit/Cancel from another PE TEST_INFO: This test exercisesGlobal monitor state unchanged upon TM entry/exit/cancel from different PE Test may fail with PE global monitor state mismatch or TM failure with IMP cause Unique MUT location values observed at CPU%d = %d (total observation attempts = %d) Containment failure observed at CPU%d and last valid value observed = %x No Unique MUT location values observed at CPU%d = %d (total observation attempts = %d) WFE failure observed at CPU%d = %d (total wfe attempts = %d) No Unique MUT location value observed at CPU%d = %d (total observation attempts = %d) Unique MUT location values observed at CPU%d = %d (total observation attempts = %d) Noninterfernce failure observed at CPU%d and last valid value observed = %x Load mismatch observed at CPU%d and last valid loads observed load1= %x load2= %x Load X mismatch observed at CPU%d and last valid loads observed load1= %x load2= %x Load Y mismatch observed at CPU%d and last valid loads observed load1= %x load2= %x No Unique MUT location value observed at CPU%d = %d (total observation attempts = %d) TME_MEM_CHECK_ERROR: Memory writes mismatch Address: 0x%x Expected Value 0x%x Actual Value : 0x%x TME_COMMIT_ERROR: TM was expected to fail/cancel but TM commit observed TME_NEST_FLATTENDED_ERROR: Nested transaction failure was not reported to outermost destination register. Inner transaction number failed : %d TME_NEST_OBSERVER_ERROR: Changes of outer transaction was not visible to inner level transaction TME_NEST_DEPTH_OVRF_ERROR: Transaction did not fail after crossing max nesting depth limit TM_PE_STATE_CHECK_ERROR: PE expected to be in Nested Transactional state TME_ROLLBACK_ERROR: TME didnot rollback on failure when TSTART+4 instruction start next transaction TME_ERET_ERROR: ERET execution in TME resulted in branch to elr TME_SVE_SKIP: Skipping the part because SVE is not implemented TME_FP_SKIP: Skipping the part because FP is not implemented TME_FFR_ERROR: FFR checks failed TME_ZREG_ERROR: Register Check fail for Z register. Iter. no.: %d, ZReg: %d, Expected:%lx, Actual:%lx TME_PREG_ERROR: Register Check fail for P register. Iter. no.: %d, PReg: %d, Expected:%lx, Actual:%lx TME_VREG_ERROR: Register Check fail for V register. Iter. no.: %d, VReg: %d, Expected:%lx, Actual:%lx TME_NONTM_WR_OBS_ERROR: NONTM vector writes were not observed in tm at address: %0x TME_NOT_IN_EL3_SKIP: Skipping the part because it is applicable only if test is executed in EL < EL3 TME_IS_IN_EL0_SKIP: Skipping the part because it is applicable only if test is executed in EL > EL0 TME_NOT_IN_NS_SKIP: Skipping the part because it is applicable only if test is executed in EL is NON-SECURE TME_NOT_IN_EL0_SKIP: Skipping the part because it is applicable only if test is executed in EL0 TME_NOT_IN_EL1s_SKIP: Skipping the part because it is applicable only if test is executed in S-EL1 TME_NOT_IN_EL01_SKIP: Skipping the part because it is applicable only if test is executed in EL0 or EL1 TME_NOT_IN_EL1_SKIP: Skipping the part because it is applicable only if test is executed in EL1 TME_NOT_IN_EL1SKIP: Skipping the part because it is applicable only if test is executed in EL1 Secure State TME_NOT_IN_E2H_TGE_SKIP: Skipping the part because it is not applicable when test is executed with {E2H,TGE=1,1} TME_NOT_IN_NON_SECURE_STATE: Skipping the part because current EL is not in Non-Secure State TME_NOT_IN_SECURE_STATE: Skipping the part because current EL is not in Secure State TME_IS_GT_EL1_SKIP: Skipping the part because it is applicable only if current EL <= EL1 TME_IS_GT_EL1s_SKIP: Skipping the part because it is applicable only if current EL <= EL1 and in Secure State TME_NOT_IN_EL2s_SKIP: Skipping the part because EL2 is not in Secure State TME_NOT_IN_EL2_SKIP: Skipping the part because EL2 is not implemented TME_NOT_IN_EL3_SKIP: Skipping the part because EL3 is not implemented TME_NOT_IN_EL23_SKIP: Skipping the part because both EL2 and EL3 is not implemented TME_FPTRAP_SKIP: Skipping the part because DUT does not support traps on FP Exception TME_EXT_ABORT_SKIP: Skipping the part because STR_NORMAL_WB_ABORT_BEHAVE != SEA TME_EXT_ABORT_SKIP: Skipping the part because LOAD_NORMAL_WB_ABORT_BEHAVE != SEA TME_EXT_ABORT_SKIP: Skipping the part because FETCH_NORMAL_WB_ABORT_BEHAVE != SEA TEST_INEFFECTIVENESS_ERROR: Synchronous External Abort not generated for Transactional Store at 0x%x TEST_INFO: This test exercises allowed a64 instructions inside TM and expected TM to commit successfull Test may fail with TM failure with various cause or IMP cause where test is ineffective TEST_INFO: This test exercises forbidden a64 instructions inside TM and expected TM to fail Test may fail with TM commit due to forbidden condition not causing TM failure or IMP cause where test will be ineffective Instruction modification observed at CPU%d = %d (total observation attempts = %x) Instruction modification mismatch observed at CPU%d and last valid value observed = %x Code conflict observed at CPU%d = %d (total observation attempts = %x) Dependency-order-before/Address dependency violated, expected memory value = %d and actual memory value = %d Dependency-order-before/control dependency violated, expected memory value = %d and actual memory value = %d Dependency-order-before/data dependency violated, expected memory value = %d and actual memory value = %d Atomic-order-before/different address violated, expected memory value = %d and actual memory value = %d Barrier-order-before/dmb sy violated, expected memory value = %d and actual memory value = %d Barrier-order-before/acquire,release violated, expected memory value = %d and actual memory value = %d Barrier-order-before/dmb ld violated, expected memory value = %d and actual memory value = %d Barrier-order-before/acquire violated, expected memory value = %d and actual memory value = %d Barrier-order-before/dmb st violated, expected memory value = %d and actual memory value = %d Barrier-order-before/release violated, expected memory value = %d and actual memory value = %d Atomic-order-before/different address test ineffective due to exclusive failure TEST_INFO: This test exercises ordering and observability cases inside TM Test exercises DOB (Dependency-order-Before) AOB (Address-order-Before)BOB (Barrier-order-Before) ordering rules Test may fail with ordering violations or IMP cause where test will be ineffective TEST_INFO: This test exercises commit atomicity where memory locations modified inside TM and registers updated inside TM are verfied against the modified values after TCOMMIT Test may fail with memory or register update mismatch or IMP cause Where test will be ineffective TEST_INFO: This test exercises commit atomicity where SVE register updated inside TM are verified against the update values after TCOMMIT Test may fail with register update mismatch or IMP cause Where test will be ineffective TEST_INFO: This test exercises different memory attribute access inside TM and verify the commited memory effect or rollback effect in case of unsupported attribute inside TM Test may fail with memory mismatch or IMP failure due to unsupported memory access inside TM TEST_INFO: This test exercises nested transaction cases Transaction failure at different nest level and flattend commit atomicity at different nesting levels max nest depth testing Test may fail with memory mismath or cause mismatch or IMP cause where test will be ineffective TEST_INFO: This test exercises different register (X/V) and system register update inside TM and perform rollback checks when TM fails Test may fail with register value mismatch or IMP cause where test will be ineffective TEST_INFO: This test exercisesdifferent sve register (Z/P) update inside TM and perform rollback checks when TM fails Test may fail with register value mismatch or IMP cause where test will be ineffective TEST_INFO: This test exercises various sync exception generation cases inside TM and verifies the TM failure cause Test may fail with cause mismatch or IMP cause where test will be ineffective TEST_INFO: This test exercises asizef sync exception generation cases inside TM and verifies the TM failure cause Test may fail with cause mismatch or IMP cause where test will be ineffective TEST_INFO: This test exercises sync exception when SVE instructions access inside TM and verifies the TM failure cause Test may fail with cause mismatch or IMP cause where test will be ineffective TME_MESSAGE_PASSING_INEFFECTIVENESS:: Unique MUT location values observed at CPU%d = %d (total observation attempts = %d) TME_MESSAGE_PASSING_FAILURE:: Ordering observation voilation where Loc_X > Loc_Y(Loc_X=%d and Loc_Y=%d) TME_SVE_MEM: Transaction cancelled due to failure of Z-reg visibility from inner to outer transaction, 0x%x TME_SVE_MEM: PE was expected to complete transaction but it Failed with cause = 0x%x TME_SVE_MEM: PE was expected to FAIL transaction with cause = 0x%x, but it Succeded! TME_SVE_MEM_INEFFECTIVE: VectorOp[%d], Expected Active Elements Count : %d, Actual Active Elements Count = %d TME_SYS_REG: Sys Reg access Check Failed TME_SYS_REG: MSR Sys Reg Write check failed, Expected Value : %d, Actual value = %d TME_SYS_REG: MSR Sys Reg Write side effect check failed, Expected Value : %d, Actual value = %d TME_SYS_REG: PE was expected to FAIL transaction with cause = 0x%x, but it Succeded! TME_SYS_REG: Unexpected Exception Observed! TME_ADR_TRAN: PE was expected to FAIL transaction with cause = 0x%x, but it Succeded! TME_ADR_TRAN: Memory read mismatch @Address: 0x%x, Expected Value 0x%x, Actual Value : 0x%x TME_ADR_TRAN: Memory write mismatch @Addr: 0x%x, (@Alias Addr: 0x%x), Exp Val 0x%x, Actual Value : 0x%x TME_ADR_TRAN: AF Flag Not Set in Leaf Descriptor ( 0x%x ) for Transactional access of Memory @ 0x%x TME_ADR_TRAN: AP2 Flag Not Cleared in Leaf Descriptor ( 0x%x ) for Transactional access of Memory @ 0x%x TME_ADR_TRAN: HCR_EL2_E2H mismatch: Expected Value 0 ACtual Value 1 TME_ADR_TRAN: HCR_EL2_E2H mismatch: Expected Value 1 ACtual Value 0 TME_ADR_TRAN: Hardware updates to Access flag not Supported TME_ADR_TRAN: Hardware updates to Access flag and Dirty state not Supported TME_SH_DBG: PE was expected to FAIL transaction with cause = %d, but it Succeded! TME_INTERRUPT: Interrupt setup Failed TME_INTERRUPT: PE was expected to FAIL transaction with cause = 0x%x, but it Succeded! TME_INTERRUPT: PE was expected to Succeed transaction but failed with cause = 0x%x TME_INTERRUPT: Transaction Loop Count Check Failed, Expected Value = 0x%x, Actual Value = 0x%x TME_INTERRUPT: Unexpected Interrupt Event, TX_INTERRUPT_FLAG Exp Val: 0x%x, Actual Value : 0x%x TME_INTERRUPT: No Interrupt received, TX_INTERRUPT_FLAG Exp Val: 0x%x, Actual Value : 0x%x TME_INTERRUPT: Interrupt Gen Clean Failed with status : 0x%x TME_INTERRUPT: Interrupt Gen Stop Failed with status : 0x%x TME_INTERRUPT: X reg restore didn't succeed after transaction failure DC conflict observed at CPU%d = %d (total observation attempts = %x) Prefetch conflict observed at CPU%d = %d (total observation attempts = %x) TME_PMU: Skipping the part because PMU is not implemented TME_PMU: Skipping the part because implemented PMUVer is not supported TME_PMU: Skipping the part because Minimum PMU counters not available TME_PMU_ERROR: PMU Event Code (0x%x), PMU Counter Number ( %d), PMU Counter Expected Value: %d, Actual Value : %d TME_PMU_INEFFECTIVE: PMU Event Code (0x%x), PMU Counter Number ( %d), PMU Counter Expected Value: Non-zero, Actual Value : %d TME_PMU_ERROR: PMU Event Code (0x%x), PMU Counter Number ( %d), Overflow Status: Expected Value: %d, Actual Value : %d TME_MTE_ERROR: Tag Store Failed: Expected Tag Value: 0x%x, Actual Tag Value : 0x%x TME_MTE_ERROR: Tag ReStore Failed for Failed/Cancelled Transaction. Expected Tag Value: 0x%x, Actual Tag Value : 0x%x TME_MTE_ERROR: Checked Access failed Expected Mem Value: 0x%x, Actual Mem Value : 0x%x TME_MTE: PE was expected to complete transaction but it Failed with cause = 0x%x TME_MTE: PE was expected to FAIL transaction with cause = 0x%x, but it Succeded! TME_MTE: Tag Check Fail Asynchronous status not captured! TME_ENABLE_CONTROL: UNDEFINED Exception not generated !! TME_ENABLE_CONTROL: TME Undefined Exception: Expected ID_AA64ISAR0_EL1.TME = 0x0, Actual Value 0x%x !! TME_ENABLE_CONTROL: TME TRAP Exception: Expected EC Value = 0x1b, Actual EC Value 0x%x !! TME_ENABLE_CONTROL: Transaction Succeeded but was expected to fail with cause = 0x%x TME_BTI: Skipping part because BTI is not implemented TME_MEM_CONFLICT: Transaction Succeeded but was expected to fail with cause = 0x%x TME_MEM_CONFLICT: Transaction was expected to Fail with cause = 0x%x TME_MEM_CONFLICT: Transaction failure cause mismatch, Expected cause = 0x%x, Actual cause = 0x%x TME_RESET: Resume after Reset O+O_O)2"} bO__@cT)(@)+0A)A=!@ 0) (((TB @H T)(( ((HT)D@ D(@8B8T__CT@ T @8*8?@T)@9@ 9`T(@9! B 9 B !B*r@T R( _) KT @JqS M@%k ! * D *TB@)}S _qKT(@99T(@9_ q9kT(@99_֥*`68!(cT`6$x(T!? DTA6$xA69_(T!7A7_!? DT!6$x69_(T!7A7_!? DT!6$x69_{DDKw[WW[AS'R HS **R/??A)= S *?A*RI!i  *}yG}y[A=R!RbR)kkAySgkA5 ScgAcA *_K@H@qa2TWA qKT_AqT~6Gv~ N) G@WA q+T_AqT[A(4WAqT_A+5A!((R*r*kk[ARcR@}!yG@?y?@ y@@J 4hR*;@;;@S@t@@S@t@@@)M*R r)  *kk@@@@R *@@*kk[AR*RkR * * *okg®[Ao@k@g@kE9)7(Rkk[ARiR* *c_[ARS@O@CggAMSgkA qTgAh4*kk[AR!RcRQ*kk[AR(RiR* *KGD[A=RK@G@kkAiSkkAqaT*kk[AR!RcR/[ARC@?@դkkA rkkA 4*kk[AR)RjR * *;73;@kk[AR7@3@٭[A>R!RbRkkA= SkkAh4*kk[AR!RcRĭ(Rkk[ARcR* WA qT_Aq T~* WAWA qT_AqKT~* ~J6 @ N) @KWA q+T_AqT[A(4WAqT_Ah5A!( Rߧ*k@ ) T@ ) Tk@@ Rߗ,Hk@@k[AR!RcRXi WA qT_Aq T~* WA@@A!)(R * @@@kk @@@@ @@ @*JT*yHRy*3y3Ay qT3Ay*I *(93Ay3y}yG"RY@y]D{_+'G'@'Rq HS *'*R##@)= S *#@*RI!i  *'@@) 4hR*@@@@ R * @@@ R *@G@ *+@_ 39@ @_C@ f tC_A_ƢR*_`R*_*@@ kBT*@#ih8A!<)*R *@@@_C#9@@9)qT@9@(9@(R * @*(9@! @@ @;y;@y5qT@;@y * * 9;@y;y@ R@3@*! kL@#@C_+hR*R*< S*O@,S*K'RHS*G*R@= S*@*RH!h *@K@4@ ThR*O@4@(R*hR*G@@) 4hR*@@O@4@h@@ `R *@H@@R*@K@H4@h@@ `R *+@_ 39*#9#@93@9 kJT @#@9 * ij8@@ 9@ @J #@9#9_CC?;9''R HS *G*RoCC@)= S */C@*RI!i  *+G@+@) 4hR*+@@+* *3iAiA9 )iA(9;@'/?@ A9?@!A(R *'A9?@(E9?@!E@'@?@*(I9?@!I@'@#?@#@(M9?@!M@'@/@+@&/@+@ ;@(k*?@#?@!QR@q/@+@.?@ ?@!aR@f?@!BR@a#@{y{@y5qT?@{@y * * 9{@y{y?@R Hc@R)RjR * * ?@c@R@ @?@?@iBR r * !Ru?@%dRq?@)eRm?@-fRi?@1?@R @?@R @*sys@ymqT?@s@y * * 9s@ysy?@R/@+@R */@+@(7'@s@*! k/@+@?@@;@C@C_ `R * uuA_ R!R**JA_X@h"_ X@!h"_րX@ha_{ҿaT{_{<N$<NTP<N$<NTP{_{ҿaTp p{_Register Check fail for X register. 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