// Copyright 2019 Google LLC
//
// This source code is licensed under the BSD-style license found in the
// LICENSE file in the root directory of this source tree.

$assert BATCH_TILE % 4 == 0
$assert BATCH_TILE >= 4
$assert RR_STEPS in [1, 2]
$assert DIV_ALGO in ["div", "nr2fma", "nr2recps", "nr1recps1fma"]
$ABC = "0123456789ABCDEFGHIJKLMNOPQRSTUVWXYZ"
$VMULADDQ_F32 = "vfmaq_f32" if FMA else "vmlaq_f32"
#include <assert.h>

#include <arm_neon.h>

#include <xnnpack/common.h>
#include <xnnpack/vunary.h>


void xnn_f32_sigmoid_ukernel__${"neonfma" if FMA else "neon"}_rr${RR_STEPS}_p5_${DIV_ALGO}_x${BATCH_TILE}(
    size_t n,
    const float* x,
    float* y,
    const void* params) XNN_DISABLE_TSAN
{
  assert(n % sizeof(float) == 0);

  const float32x4_t vmagic_bias = vmovq_n_f32(0x1.8000FEp23f);
  const float32x4_t vminus_log2e = vmovq_n_f32(-0x1.715476p+0f);
  $if RR_STEPS == 1:
    const float32x4_t vln2 = vmovq_n_f32(0x1.62E43p-1f);
  $else:
    $if FMA:
      const float32x4_t vln2_hi = vmovq_n_f32(0x1.62E43p-1f);
      const float32x4_t vln2_lo = vmovq_n_f32(-0x1.05C61p-29f);
    $else:
      const float32x4_t vln2_hi = vmovq_n_f32(0x1.62E400p-1f);
      const float32x4_t vln2_lo = vmovq_n_f32(0x1.7F7D1Cp-20f);
  const float32x4_t vc5 = vmovq_n_f32(-0x1.0F9F9Cp-7f);
  const float32x4_t vc4 = vmovq_n_f32(0x1.573A1Ap-5f);
  const float32x4_t vc3 = vmovq_n_f32(-0x1.555A80p-3f);
  const float32x4_t vc2 = vmovq_n_f32(0x1.FFFDC6p-2f);
  const float32x4_t vc1 = vmovq_n_f32(-0x1.FFFFF6p-1f);
  const float32x4_t vone = vmovq_n_f32(1.0f);
  const float32x4_t vdenorm_cutoff = vmovq_n_f32(-0x1.5D589Ep+6f);

  $if BATCH_TILE > 4:
    for (; n >= ${BATCH_TILE} * sizeof(float); n -= ${BATCH_TILE} * sizeof(float)) {
      $for N in range(0, BATCH_TILE, 4):
        const float32x4_t vx${ABC[N:N+4]} = vld1q_f32(x); x += 4;

      $for N in range(0, BATCH_TILE, 4):
        const float32x4_t vz${ABC[N:N+4]} = vabsq_f32(vx${ABC[N:N+4]});

      $for N in range(0, BATCH_TILE, 4):
        float32x4_t vn${ABC[N:N+4]} = ${VMULADDQ_F32}(vmagic_bias, vz${ABC[N:N+4]}, vminus_log2e);

      $for N in range(0, BATCH_TILE, 4):
        const float32x4_t vs${ABC[N:N+4]} = vreinterpretq_f32_s32(vshlq_n_s32(vreinterpretq_s32_f32(vn${ABC[N:N+4]}), 23));

      $for N in range(0, BATCH_TILE, 4):
        vn${ABC[N:N+4]} = vsubq_f32(vn${ABC[N:N+4]}, vmagic_bias);

      $if RR_STEPS == 1:
        $for N in range(0, BATCH_TILE, 4):
          float32x4_t vt${ABC[N:N+4]} = ${VMULADDQ_F32}(vz${ABC[N:N+4]}, vn${ABC[N:N+4]}, vln2);
      $else:
        $for N in range(0, BATCH_TILE, 4):
          float32x4_t vt${ABC[N:N+4]} = ${VMULADDQ_F32}(vz${ABC[N:N+4]}, vn${ABC[N:N+4]}, vln2_hi);

        $for N in range(0, BATCH_TILE, 4):
          vt${ABC[N:N+4]} = ${VMULADDQ_F32}(vt${ABC[N:N+4]}, vn${ABC[N:N+4]}, vln2_lo);

      $for N in range(0, BATCH_TILE, 4):
        float32x4_t vp${ABC[N:N+4]} = ${VMULADDQ_F32}(vc4, vc5, vt${ABC[N:N+4]});

      $for N in range(0, BATCH_TILE, 4):
        vp${ABC[N:N+4]} = ${VMULADDQ_F32}(vc3, vp${ABC[N:N+4]}, vt${ABC[N:N+4]});

      $for N in range(0, BATCH_TILE, 4):
        vp${ABC[N:N+4]} = ${VMULADDQ_F32}(vc2, vp${ABC[N:N+4]}, vt${ABC[N:N+4]});

      $for N in range(0, BATCH_TILE, 4):
        vp${ABC[N:N+4]} = ${VMULADDQ_F32}(vc1, vp${ABC[N:N+4]}, vt${ABC[N:N+4]});

      $for N in range(0, BATCH_TILE, 4):
        vt${ABC[N:N+4]} = vmulq_f32(vt${ABC[N:N+4]}, vs${ABC[N:N+4]});

      $for N in range(0, BATCH_TILE, 4):
        const float32x4_t ve${ABC[N:N+4]} = ${VMULADDQ_F32}(vs${ABC[N:N+4]}, vp${ABC[N:N+4]}, vt${ABC[N:N+4]});

      $for N in range(0, BATCH_TILE, 4):
        const float32x4_t vd${ABC[N:N+4]} = vaddq_f32(ve${ABC[N:N+4]}, vone);

      $if DIV_ALGO == "div":
        $for N in range(0, BATCH_TILE, 4):
          float32x4_t vf${ABC[N:N+4]} = vdivq_f32(ve${ABC[N:N+4]}, vd${ABC[N:N+4]});
      $else:
        $for N in range(0, BATCH_TILE, 4):
          float32x4_t vr${ABC[N:N+4]} = vrecpeq_f32(vd${ABC[N:N+4]});

        $if DIV_ALGO == "nr2fma":
          $for N in range(0, BATCH_TILE, 4):
            vr${ABC[N:N+4]} = vfmaq_f32(vr${ABC[N:N+4]}, vr${ABC[N:N+4]}, vfmsq_f32(vone, vr${ABC[N:N+4]}, vd${ABC[N:N+4]}));
        $else:
          $for N in range(0, BATCH_TILE, 4):
            vr${ABC[N:N+4]} = vmulq_f32(vr${ABC[N:N+4]}, vrecpsq_f32(vr${ABC[N:N+4]}, vd${ABC[N:N+4]}));

        $if DIV_ALGO == "nr2recps":
          $for N in range(0, BATCH_TILE, 4):
            vr${ABC[N:N+4]} = vmulq_f32(vr${ABC[N:N+4]}, vrecpsq_f32(vr${ABC[N:N+4]}, vd${ABC[N:N+4]}));
        $else:
          $for N in range(0, BATCH_TILE, 4):
            vr${ABC[N:N+4]} = vfmaq_f32(vr${ABC[N:N+4]}, vr${ABC[N:N+4]}, vfmsq_f32(vone, vr${ABC[N:N+4]}, vd${ABC[N:N+4]}));

        $for N in range(0, BATCH_TILE, 4):
          float32x4_t vf${ABC[N:N+4]} = vmulq_f32(ve${ABC[N:N+4]}, vr${ABC[N:N+4]});

      $for N in range(0, BATCH_TILE, 4):
        vf${ABC[N:N+4]} = vreinterpretq_f32_u32(vbicq_u32(vreinterpretq_u32_f32(vf${ABC[N:N+4]}), vcagtq_f32(vx${ABC[N:N+4]}, vdenorm_cutoff)));

      $for N in range(0, BATCH_TILE, 4):
        const uint32x4_t vm${ABC[N:N+4]} = vcltq_f32(vx${ABC[N:N+4]}, vmovq_n_f32(0.0f));

      $for N in range(0, BATCH_TILE, 4):
        vf${ABC[N:N+4]} = vbslq_f32(vm${ABC[N:N+4]}, vf${ABC[N:N+4]}, vsubq_f32(vone, vf${ABC[N:N+4]}));

      $for N in range(0, BATCH_TILE, 4):
        vst1q_f32(y, vf${ABC[N:N+4]}); y += 4;
    }
  for (; n >= 4 * sizeof(float); n -= 4 * sizeof(float)) {
    const float32x4_t vx = vld1q_f32(x); x += 4;

    const float32x4_t vz = vabsq_f32(vx);

    float32x4_t vn = ${VMULADDQ_F32}(vmagic_bias, vz, vminus_log2e);
    const float32x4_t vs = vreinterpretq_f32_s32(vshlq_n_s32(vreinterpretq_s32_f32(vn), 23));
    vn = vsubq_f32(vn, vmagic_bias);
    $if RR_STEPS == 1:
      float32x4_t vt = ${VMULADDQ_F32}(vz, vn, vln2);
    $else:
      float32x4_t vt = ${VMULADDQ_F32}(vz, vn, vln2_hi);
      vt = ${VMULADDQ_F32}(vt, vn, vln2_lo);

    float32x4_t vp = ${VMULADDQ_F32}(vc4, vc5, vt);
    vp = ${VMULADDQ_F32}(vc3, vp, vt);
    vp = ${VMULADDQ_F32}(vc2, vp, vt);
    vp = ${VMULADDQ_F32}(vc1, vp, vt);

    vt = vmulq_f32(vt, vs);
    const float32x4_t ve = ${VMULADDQ_F32}(vs, vp, vt);
    const float32x4_t vd = vaddq_f32(ve, vone);

    $if DIV_ALGO == "div":
      float32x4_t vf = vdivq_f32(ve, vd);
    $else:
      float32x4_t vr = vrecpeq_f32(vd);
      $if DIV_ALGO == "nr2fma":
        vr = vfmaq_f32(vr, vr, vfmsq_f32(vone, vr, vd));
      $else:
        vr = vmulq_f32(vr, vrecpsq_f32(vr, vd));
      $if DIV_ALGO == "nr2recps":
        vr = vmulq_f32(vr, vrecpsq_f32(vr, vd));
      $else:
        vr = vfmaq_f32(vr, vr, vfmsq_f32(vone, vr, vd));

      float32x4_t vf = vmulq_f32(ve, vr);
    vf = vreinterpretq_f32_u32(vbicq_u32(vreinterpretq_u32_f32(vf), vcagtq_f32(vx, vdenorm_cutoff)));
    const uint32x4_t vm = vcltq_f32(vx, vmovq_n_f32(0.0f));
    vf = vbslq_f32(vm, vf, vsubq_f32(vone, vf));

    vst1q_f32(y, vf); y += 4;
  }
  if XNN_UNLIKELY(n != 0) {
    const float32x4_t vx = vld1q_f32(x);

    const float32x4_t vz = vabsq_f32(vx);

    float32x4_t vn = ${VMULADDQ_F32}(vmagic_bias, vz, vminus_log2e);
    const float32x4_t vs = vreinterpretq_f32_s32(vshlq_n_s32(vreinterpretq_s32_f32(vn), 23));
    vn = vsubq_f32(vn, vmagic_bias);
    $if RR_STEPS == 1:
      float32x4_t vt = ${VMULADDQ_F32}(vz, vn, vln2);
    $else:
      float32x4_t vt = ${VMULADDQ_F32}(vz, vn, vln2_hi);
      vt = ${VMULADDQ_F32}(vt, vn, vln2_lo);

    float32x4_t vp = ${VMULADDQ_F32}(vc4, vc5, vt);
    vp = ${VMULADDQ_F32}(vc3, vp, vt);
    vp = ${VMULADDQ_F32}(vc2, vp, vt);
    vp = ${VMULADDQ_F32}(vc1, vp, vt);

    vt = vmulq_f32(vt, vs);
    const float32x4_t ve = ${VMULADDQ_F32}(vs, vp, vt);
    const float32x4_t vd = vaddq_f32(ve, vone);

    $if DIV_ALGO == "div":
      float32x4_t vf = vdivq_f32(ve, vd);
    $else:
      float32x4_t vr = vrecpeq_f32(vd);
      $if DIV_ALGO == "nr2fma":
        vr = vfmaq_f32(vr, vr, vfmsq_f32(vone, vr, vd));
      $else:
        vr = vmulq_f32(vr, vrecpsq_f32(vr, vd));
      $if DIV_ALGO == "nr2recps":
        vr = vmulq_f32(vr, vrecpsq_f32(vr, vd));
      $else:
        vr = vfmaq_f32(vr, vr, vfmsq_f32(vone, vr, vd));

      float32x4_t vf = vmulq_f32(ve, vr);
    vf = vreinterpretq_f32_u32(vbicq_u32(vreinterpretq_u32_f32(vf), vcagtq_f32(vx, vdenorm_cutoff)));
    const uint32x4_t vm = vcltq_f32(vx, vmovq_n_f32(0.0f));
    vf = vbslq_f32(vm, vf, vsubq_f32(vone, vf));

    float32x2_t vf_lo = vget_low_f32(vf);
    if (n & (2 * sizeof(float))) {
      vst1_f32(y, vf_lo); y += 2;
      vf_lo = vget_high_f32(vf);
    }
    if (n & (1 * sizeof(float))) {
      vst1_lane_f32(y, vf_lo, 0);
    }
  }
}