# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -march=amdgcn -mcpu=hawaii -run-pass=instruction-select -verify-machineinstrs -global-isel-abort=0 -o - %s | FileCheck -check-prefix=GFX7 %s
# RUN: llc -march=amdgcn -mcpu=gfx900 -run-pass=instruction-select -verify-machineinstrs -global-isel-abort=0 -o - %s | FileCheck -check-prefix=GFX9 %s

---

name: load_atomic_flat_s32_seq_cst
legalized:       true
regBankSelected: true
tracksRegLiveness: true

body: |
  bb.0:
    liveins:  $vgpr0_vgpr1

    ; GFX7-LABEL: name: load_atomic_flat_s32_seq_cst
    ; GFX7: liveins: $vgpr0_vgpr1
    ; GFX7: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1
    ; GFX7: [[FLAT_LOAD_DWORD:%[0-9]+]]:vgpr_32 = FLAT_LOAD_DWORD [[COPY]], 0, 0, 0, 0, implicit $exec, implicit $flat_scr :: (load seq_cst 4)
    ; GFX7: $vgpr0 = COPY [[FLAT_LOAD_DWORD]]
    ; GFX9-LABEL: name: load_atomic_flat_s32_seq_cst
    ; GFX9: liveins: $vgpr0_vgpr1
    ; GFX9: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1
    ; GFX9: [[FLAT_LOAD_DWORD:%[0-9]+]]:vgpr_32 = FLAT_LOAD_DWORD [[COPY]], 0, 0, 0, 0, implicit $exec, implicit $flat_scr :: (load seq_cst 4)
    ; GFX9: $vgpr0 = COPY [[FLAT_LOAD_DWORD]]
    %0:vgpr(p0) = COPY $vgpr0_vgpr1
    %1:vgpr(s32) = G_LOAD %0 :: (load seq_cst 4, align 4, addrspace 0)
    $vgpr0 = COPY %1

...

---

name: load_atomic_flat_v2s16_seq_cst
legalized:       true
regBankSelected: true
tracksRegLiveness: true

body: |
  bb.0:
    liveins:  $vgpr0_vgpr1

    ; GFX7-LABEL: name: load_atomic_flat_v2s16_seq_cst
    ; GFX7: liveins: $vgpr0_vgpr1
    ; GFX7: [[COPY:%[0-9]+]]:vgpr(p0) = COPY $vgpr0_vgpr1
    ; GFX7: [[LOAD:%[0-9]+]]:vgpr_32(<2 x s16>) = G_LOAD [[COPY]](p0) :: (load seq_cst 4)
    ; GFX7: $vgpr0 = COPY [[LOAD]](<2 x s16>)
    ; GFX9-LABEL: name: load_atomic_flat_v2s16_seq_cst
    ; GFX9: liveins: $vgpr0_vgpr1
    ; GFX9: [[COPY:%[0-9]+]]:vgpr(p0) = COPY $vgpr0_vgpr1
    ; GFX9: [[LOAD:%[0-9]+]]:vgpr_32(<2 x s16>) = G_LOAD [[COPY]](p0) :: (load seq_cst 4)
    ; GFX9: $vgpr0 = COPY [[LOAD]](<2 x s16>)
    %0:vgpr(p0) = COPY $vgpr0_vgpr1
    %1:vgpr(<2 x s16>) = G_LOAD %0 :: (load seq_cst 4, align 4, addrspace 0)
    $vgpr0 = COPY %1

...

---

name: load_atomic_flat_p3_seq_cst
legalized:       true
regBankSelected: true
tracksRegLiveness: true

body: |
  bb.0:
    liveins:  $vgpr0_vgpr1

    ; GFX7-LABEL: name: load_atomic_flat_p3_seq_cst
    ; GFX7: liveins: $vgpr0_vgpr1
    ; GFX7: [[COPY:%[0-9]+]]:vgpr(p0) = COPY $vgpr0_vgpr1
    ; GFX7: [[LOAD:%[0-9]+]]:vgpr_32(p3) = G_LOAD [[COPY]](p0) :: (load seq_cst 4)
    ; GFX7: $vgpr0 = COPY [[LOAD]](p3)
    ; GFX9-LABEL: name: load_atomic_flat_p3_seq_cst
    ; GFX9: liveins: $vgpr0_vgpr1
    ; GFX9: [[COPY:%[0-9]+]]:vgpr(p0) = COPY $vgpr0_vgpr1
    ; GFX9: [[LOAD:%[0-9]+]]:vgpr_32(p3) = G_LOAD [[COPY]](p0) :: (load seq_cst 4)
    ; GFX9: $vgpr0 = COPY [[LOAD]](p3)
    %0:vgpr(p0) = COPY $vgpr0_vgpr1
    %1:vgpr(p3) = G_LOAD %0 :: (load seq_cst 4, align 4, addrspace 0)
    $vgpr0 = COPY %1

...

---

name: load_atomic_flat_s64_seq_cst
legalized:       true
regBankSelected: true
tracksRegLiveness: true

body: |
  bb.0:
    liveins:  $vgpr0_vgpr1

    ; GFX7-LABEL: name: load_atomic_flat_s64_seq_cst
    ; GFX7: liveins: $vgpr0_vgpr1
    ; GFX7: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1
    ; GFX7: [[FLAT_LOAD_DWORDX2_:%[0-9]+]]:vreg_64 = FLAT_LOAD_DWORDX2 [[COPY]], 0, 0, 0, 0, implicit $exec, implicit $flat_scr :: (load seq_cst 8)
    ; GFX7: $vgpr0_vgpr1 = COPY [[FLAT_LOAD_DWORDX2_]]
    ; GFX9-LABEL: name: load_atomic_flat_s64_seq_cst
    ; GFX9: liveins: $vgpr0_vgpr1
    ; GFX9: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1
    ; GFX9: [[FLAT_LOAD_DWORDX2_:%[0-9]+]]:vreg_64 = FLAT_LOAD_DWORDX2 [[COPY]], 0, 0, 0, 0, implicit $exec, implicit $flat_scr :: (load seq_cst 8)
    ; GFX9: $vgpr0_vgpr1 = COPY [[FLAT_LOAD_DWORDX2_]]
    %0:vgpr(p0) = COPY $vgpr0_vgpr1
    %1:vgpr(s64) = G_LOAD %0 :: (load seq_cst 8, align 8, addrspace 0)
    $vgpr0_vgpr1 = COPY %1

...

---

name: load_atomic_flat_v2s32_seq_cst
legalized:       true
regBankSelected: true
tracksRegLiveness: true

body: |
  bb.0:
    liveins:  $vgpr0_vgpr1

    ; GFX7-LABEL: name: load_atomic_flat_v2s32_seq_cst
    ; GFX7: liveins: $vgpr0_vgpr1
    ; GFX7: [[COPY:%[0-9]+]]:vgpr(p0) = COPY $vgpr0_vgpr1
    ; GFX7: [[LOAD:%[0-9]+]]:vreg_64(<2 x s32>) = G_LOAD [[COPY]](p0) :: (load seq_cst 8)
    ; GFX7: $vgpr0_vgpr1 = COPY [[LOAD]](<2 x s32>)
    ; GFX9-LABEL: name: load_atomic_flat_v2s32_seq_cst
    ; GFX9: liveins: $vgpr0_vgpr1
    ; GFX9: [[COPY:%[0-9]+]]:vgpr(p0) = COPY $vgpr0_vgpr1
    ; GFX9: [[LOAD:%[0-9]+]]:vreg_64(<2 x s32>) = G_LOAD [[COPY]](p0) :: (load seq_cst 8)
    ; GFX9: $vgpr0_vgpr1 = COPY [[LOAD]](<2 x s32>)
    %0:vgpr(p0) = COPY $vgpr0_vgpr1
    %1:vgpr(<2 x s32>) = G_LOAD %0 :: (load seq_cst 8, align 8, addrspace 0)
    $vgpr0_vgpr1 = COPY %1

...

---

name: load_atomic_flat_v4s16_seq_cst
legalized:       true
regBankSelected: true
tracksRegLiveness: true

body: |
  bb.0:
    liveins:  $vgpr0_vgpr1

    ; GFX7-LABEL: name: load_atomic_flat_v4s16_seq_cst
    ; GFX7: liveins: $vgpr0_vgpr1
    ; GFX7: [[COPY:%[0-9]+]]:vgpr(p0) = COPY $vgpr0_vgpr1
    ; GFX7: [[LOAD:%[0-9]+]]:vreg_64(<4 x s16>) = G_LOAD [[COPY]](p0) :: (load seq_cst 8)
    ; GFX7: $vgpr0_vgpr1 = COPY [[LOAD]](<4 x s16>)
    ; GFX9-LABEL: name: load_atomic_flat_v4s16_seq_cst
    ; GFX9: liveins: $vgpr0_vgpr1
    ; GFX9: [[COPY:%[0-9]+]]:vgpr(p0) = COPY $vgpr0_vgpr1
    ; GFX9: [[LOAD:%[0-9]+]]:vreg_64(<4 x s16>) = G_LOAD [[COPY]](p0) :: (load seq_cst 8)
    ; GFX9: $vgpr0_vgpr1 = COPY [[LOAD]](<4 x s16>)
    %0:vgpr(p0) = COPY $vgpr0_vgpr1
    %1:vgpr(<4 x s16>) = G_LOAD %0 :: (load seq_cst 8, align 8, addrspace 0)
    $vgpr0_vgpr1 = COPY %1

...

---

name: load_atomic_flat_p1_seq_cst
legalized:       true
regBankSelected: true
tracksRegLiveness: true

body: |
  bb.0:
    liveins:  $vgpr0_vgpr1

    ; GFX7-LABEL: name: load_atomic_flat_p1_seq_cst
    ; GFX7: liveins: $vgpr0_vgpr1
    ; GFX7: [[COPY:%[0-9]+]]:vgpr(p0) = COPY $vgpr0_vgpr1
    ; GFX7: [[LOAD:%[0-9]+]]:vreg_64(p1) = G_LOAD [[COPY]](p0) :: (load seq_cst 8)
    ; GFX7: $vgpr0_vgpr1 = COPY [[LOAD]](p1)
    ; GFX9-LABEL: name: load_atomic_flat_p1_seq_cst
    ; GFX9: liveins: $vgpr0_vgpr1
    ; GFX9: [[COPY:%[0-9]+]]:vgpr(p0) = COPY $vgpr0_vgpr1
    ; GFX9: [[LOAD:%[0-9]+]]:vreg_64(p1) = G_LOAD [[COPY]](p0) :: (load seq_cst 8)
    ; GFX9: $vgpr0_vgpr1 = COPY [[LOAD]](p1)
    %0:vgpr(p0) = COPY $vgpr0_vgpr1
    %1:vgpr(p1) = G_LOAD %0 :: (load seq_cst 8, align 8, addrspace 0)
    $vgpr0_vgpr1 = COPY %1

...

---

name: load_atomic_flat_p0_seq_cst
legalized:       true
regBankSelected: true
tracksRegLiveness: true

body: |
  bb.0:
    liveins:  $vgpr0_vgpr1

    ; GFX7-LABEL: name: load_atomic_flat_p0_seq_cst
    ; GFX7: liveins: $vgpr0_vgpr1
    ; GFX7: [[COPY:%[0-9]+]]:vgpr(p0) = COPY $vgpr0_vgpr1
    ; GFX7: [[LOAD:%[0-9]+]]:vreg_64(p0) = G_LOAD [[COPY]](p0) :: (load seq_cst 8)
    ; GFX7: $vgpr0_vgpr1 = COPY [[LOAD]](p0)
    ; GFX9-LABEL: name: load_atomic_flat_p0_seq_cst
    ; GFX9: liveins: $vgpr0_vgpr1
    ; GFX9: [[COPY:%[0-9]+]]:vgpr(p0) = COPY $vgpr0_vgpr1
    ; GFX9: [[LOAD:%[0-9]+]]:vreg_64(p0) = G_LOAD [[COPY]](p0) :: (load seq_cst 8)
    ; GFX9: $vgpr0_vgpr1 = COPY [[LOAD]](p0)
    %0:vgpr(p0) = COPY $vgpr0_vgpr1
    %1:vgpr(p0) = G_LOAD %0 :: (load seq_cst 8, align 8, addrspace 0)
    $vgpr0_vgpr1 = COPY %1

...

---

name: load_atomic_flat_s32_seq_cst_gep_m2048
legalized:       true
regBankSelected: true
tracksRegLiveness: true

body: |
  bb.0:
    liveins:  $vgpr0_vgpr1

    ; GFX7-LABEL: name: load_atomic_flat_s32_seq_cst_gep_m2048
    ; GFX7: liveins: $vgpr0_vgpr1
    ; GFX7: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1
    ; GFX7: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 4294965248, implicit $exec
    ; GFX7: [[V_MOV_B32_e32_1:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 -1, implicit $exec
    ; GFX7: [[REG_SEQUENCE:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[V_MOV_B32_e32_]], %subreg.sub0, [[V_MOV_B32_e32_1]], %subreg.sub1
    ; GFX7: [[COPY1:%[0-9]+]]:vgpr_32 = COPY [[COPY]].sub0
    ; GFX7: [[COPY2:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE]].sub0
    ; GFX7: [[COPY3:%[0-9]+]]:vgpr_32 = COPY [[COPY]].sub1
    ; GFX7: [[COPY4:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE]].sub1
    ; GFX7: [[V_ADD_CO_U32_e64_:%[0-9]+]]:vgpr_32, [[V_ADD_CO_U32_e64_1:%[0-9]+]]:sreg_64_xexec = V_ADD_CO_U32_e64 [[COPY1]], [[COPY2]], 0, implicit $exec
    ; GFX7: %9:vgpr_32, dead %11:sreg_64_xexec = V_ADDC_U32_e64 [[COPY3]], [[COPY4]], killed [[V_ADD_CO_U32_e64_1]], 0, implicit $exec
    ; GFX7: [[REG_SEQUENCE1:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[V_ADD_CO_U32_e64_]], %subreg.sub0, %9, %subreg.sub1
    ; GFX7: [[FLAT_LOAD_DWORD:%[0-9]+]]:vgpr_32 = FLAT_LOAD_DWORD [[REG_SEQUENCE1]], 0, 0, 0, 0, implicit $exec, implicit $flat_scr :: (load seq_cst 4)
    ; GFX7: $vgpr0 = COPY [[FLAT_LOAD_DWORD]]
    ; GFX9-LABEL: name: load_atomic_flat_s32_seq_cst_gep_m2048
    ; GFX9: liveins: $vgpr0_vgpr1
    ; GFX9: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1
    ; GFX9: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 4294965248, implicit $exec
    ; GFX9: [[V_MOV_B32_e32_1:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 -1, implicit $exec
    ; GFX9: [[REG_SEQUENCE:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[V_MOV_B32_e32_]], %subreg.sub0, [[V_MOV_B32_e32_1]], %subreg.sub1
    ; GFX9: [[COPY1:%[0-9]+]]:vgpr_32 = COPY [[COPY]].sub0
    ; GFX9: [[COPY2:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE]].sub0
    ; GFX9: [[COPY3:%[0-9]+]]:vgpr_32 = COPY [[COPY]].sub1
    ; GFX9: [[COPY4:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE]].sub1
    ; GFX9: [[V_ADD_CO_U32_e64_:%[0-9]+]]:vgpr_32, [[V_ADD_CO_U32_e64_1:%[0-9]+]]:sreg_64_xexec = V_ADD_CO_U32_e64 [[COPY1]], [[COPY2]], 0, implicit $exec
    ; GFX9: %9:vgpr_32, dead %11:sreg_64_xexec = V_ADDC_U32_e64 [[COPY3]], [[COPY4]], killed [[V_ADD_CO_U32_e64_1]], 0, implicit $exec
    ; GFX9: [[REG_SEQUENCE1:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[V_ADD_CO_U32_e64_]], %subreg.sub0, %9, %subreg.sub1
    ; GFX9: [[FLAT_LOAD_DWORD:%[0-9]+]]:vgpr_32 = FLAT_LOAD_DWORD [[REG_SEQUENCE1]], 0, 0, 0, 0, implicit $exec, implicit $flat_scr :: (load seq_cst 4)
    ; GFX9: $vgpr0 = COPY [[FLAT_LOAD_DWORD]]
    %0:vgpr(p0) = COPY $vgpr0_vgpr1
    %1:vgpr(s64) = G_CONSTANT i64 -2048
    %2:vgpr(p0) = G_PTR_ADD %0, %1
    %3:vgpr(s32) = G_LOAD %2 :: (load seq_cst 4, align 4, addrspace 0)
    $vgpr0 = COPY %3

...

---

name: load_atomic_flat_s32_seq_cst_gep_4095
legalized:       true
regBankSelected: true
tracksRegLiveness: true

body: |
  bb.0:
    liveins:  $vgpr0_vgpr1

    ; GFX7-LABEL: name: load_atomic_flat_s32_seq_cst_gep_4095
    ; GFX7: liveins: $vgpr0_vgpr1
    ; GFX7: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1
    ; GFX7: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 4095, implicit $exec
    ; GFX7: [[V_MOV_B32_e32_1:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
    ; GFX7: [[REG_SEQUENCE:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[V_MOV_B32_e32_]], %subreg.sub0, [[V_MOV_B32_e32_1]], %subreg.sub1
    ; GFX7: [[COPY1:%[0-9]+]]:vgpr_32 = COPY [[COPY]].sub0
    ; GFX7: [[COPY2:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE]].sub0
    ; GFX7: [[COPY3:%[0-9]+]]:vgpr_32 = COPY [[COPY]].sub1
    ; GFX7: [[COPY4:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE]].sub1
    ; GFX7: [[V_ADD_CO_U32_e64_:%[0-9]+]]:vgpr_32, [[V_ADD_CO_U32_e64_1:%[0-9]+]]:sreg_64_xexec = V_ADD_CO_U32_e64 [[COPY1]], [[COPY2]], 0, implicit $exec
    ; GFX7: %9:vgpr_32, dead %11:sreg_64_xexec = V_ADDC_U32_e64 [[COPY3]], [[COPY4]], killed [[V_ADD_CO_U32_e64_1]], 0, implicit $exec
    ; GFX7: [[REG_SEQUENCE1:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[V_ADD_CO_U32_e64_]], %subreg.sub0, %9, %subreg.sub1
    ; GFX7: [[FLAT_LOAD_DWORD:%[0-9]+]]:vgpr_32 = FLAT_LOAD_DWORD [[REG_SEQUENCE1]], 0, 0, 0, 0, implicit $exec, implicit $flat_scr :: (load seq_cst 4)
    ; GFX7: $vgpr0 = COPY [[FLAT_LOAD_DWORD]]
    ; GFX9-LABEL: name: load_atomic_flat_s32_seq_cst_gep_4095
    ; GFX9: liveins: $vgpr0_vgpr1
    ; GFX9: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1
    ; GFX9: [[FLAT_LOAD_DWORD:%[0-9]+]]:vgpr_32 = FLAT_LOAD_DWORD [[COPY]], 4095, 0, 0, 0, implicit $exec, implicit $flat_scr :: (load seq_cst 4)
    ; GFX9: $vgpr0 = COPY [[FLAT_LOAD_DWORD]]
    %0:vgpr(p0) = COPY $vgpr0_vgpr1
    %1:vgpr(s64) = G_CONSTANT i64 4095
    %2:vgpr(p0) = G_PTR_ADD %0, %1
    %3:vgpr(s32) = G_LOAD %2 :: (load seq_cst 4, align 4, addrspace 0)
    $vgpr0 = COPY %3

...