# Copyright (C) 2016 Intel Corporation. All Rights Reserved. # # Permission is hereby granted, free of charge, to any person obtaining a # copy of this software and associated documentation files (the "Software"), # to deal in the Software without restriction, including without limitation # the rights to use, copy, modify, merge, publish, distribute, sublicense, # and/or sell copies of the Software, and to permit persons to whom the # Software is furnished to do so, subject to the following conditions: # # The above copyright notice and this permission notice (including the next # paragraph) shall be included in all copies or substantial portions of the # Software. # # THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR # IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, # FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL # THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER # LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING # FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS # IN THE SOFTWARE. # # Provides definitions for events. enum AR_DRAW_TYPE { Instanced = 0, IndexedInstanced = 1, InstancedSplit = 2, IndexedInstancedSplit = 3 }; event Framework::ThreadStartApiEvent { }; event Framework::ThreadStartWorkerEvent { }; ///@brief Used as a helper event to indicate end of frame. Does not gaurantee to capture end of frame on all APIs event ApiSwr::FrameEndEvent { uint32_t frameId; // current frame id uint32_t nextDrawId; // next draw id (always incremental - does not reset) }; ///@brief Synchonization event. event ApiSwr::SwrSyncEvent { uint32_t drawId; }; ///@brief Invalidate hot tiles (i.e. tile cache) event ApiSwr::SwrInvalidateTilesEvent { uint32_t drawId; }; ///@brief Invalidate and discard hot tiles within pixel region event ApiSwr::SwrDiscardRectEvent { uint32_t drawId; }; ///@brief Flush tiles out to memory that is typically owned by driver (e.g. Flush RT cache) event ApiSwr::SwrStoreTilesEvent { uint32_t drawId; }; event PipelineStats::DrawInfoEvent { uint32_t drawId; AR_DRAW_TYPE type; // type of draw (indexed, instanced, etc) uint32_t topology; // topology of draw uint32_t numVertices; // number of vertices for draw uint32_t numIndices; // number of indices for draw int32_t indexOffset; // offset into index buffer int32_t baseVertex; // which vertex to start with uint32_t numInstances; // number of instances to draw uint32_t startInstance; // which instance to start fetching uint32_t tsEnable; // tesselation enabled uint32_t gsEnable; // geometry shader enabled uint32_t soEnable; // stream-out enabled uint32_t soTopology; // topology of stream-out uint32_t splitId; // split draw count or id }; event PipelineStats::DispatchEvent { uint32_t drawId; uint32_t threadGroupCountX; // num thread groups in X dimension uint32_t threadGroupCountY; // num thread groups in Y dimension uint32_t threadGroupCountZ; // num thread groups in Z dimension }; event PipelineStats::FrontendStatsEvent { uint32_t drawId; uint64_t IaVertices; uint64_t IaPrimitives; uint64_t VsInvocations; uint64_t HsInvocations; uint64_t DsInvocations; uint64_t GsInvocations; uint64_t GsPrimitives; uint64_t CInvocations; uint64_t CPrimitives; uint64_t SoPrimStorageNeeded0; uint64_t SoPrimStorageNeeded1; uint64_t SoPrimStorageNeeded2; uint64_t SoPrimStorageNeeded3; uint64_t SoNumPrimsWritten0; uint64_t SoNumPrimsWritten1; uint64_t SoNumPrimsWritten2; uint64_t SoNumPrimsWritten3; }; event PipelineStats::BackendStatsEvent { uint32_t drawId; uint64_t DepthPassCount; uint64_t PsInvocations; uint64_t CsInvocations; }; event PipelineStats::EarlyZSingleSample { uint32_t drawId; uint64_t passCount; uint64_t failCount; }; event PipelineStats::LateZSingleSample { uint32_t drawId; uint64_t passCount; uint64_t failCount; }; event PipelineStats::EarlyStencilSingleSample { uint32_t drawId; uint64_t passCount; uint64_t failCount; }; event PipelineStats::LateStencilSingleSample { uint32_t drawId; uint64_t passCount; uint64_t failCount; }; event PipelineStats::EarlyZSampleRate { uint32_t drawId; uint64_t passCount; uint64_t failCount; }; event PipelineStats::LateZSampleRate { uint32_t drawId; uint64_t passCount; uint64_t failCount; }; event PipelineStats::EarlyStencilSampleRate { uint32_t drawId; uint64_t passCount; uint64_t failCount; }; event PipelineStats::LateStencilSampleRate { uint32_t drawId; uint64_t passCount; uint64_t failCount; }; // Total Early-Z counts, SingleSample and SampleRate event PipelineStats::EarlyZ { uint32_t drawId; uint64_t passCount; uint64_t failCount; }; // Total LateZ counts, SingleSample and SampleRate event PipelineStats::LateZ { uint32_t drawId; uint64_t passCount; uint64_t failCount; }; // Total EarlyStencil counts, SingleSample and SampleRate event PipelineStats::EarlyStencil { uint32_t drawId; uint64_t passCount; uint64_t failCount; }; // Total LateStencil counts, SingleSample and SampleRate event PipelineStats::LateStencil { uint32_t drawId; uint64_t passCount; uint64_t failCount; }; event PipelineStats::EarlyZNullPS { uint32_t drawId; uint64_t passCount; uint64_t failCount; }; event PipelineStats::EarlyStencilNullPS { uint32_t drawId; uint64_t passCount; uint64_t failCount; }; event PipelineStats::EarlyZPixelRate { uint32_t drawId; uint64_t passCount; uint64_t failCount; }; event PipelineStats::LateZPixelRate { uint32_t drawId; uint64_t passCount; uint64_t failCount; }; event PipelineStats::EarlyOmZ { uint32_t drawId; uint64_t passCount; uint64_t failCount; }; event PipelineStats::EarlyOmStencil { uint32_t drawId; uint64_t passCount; uint64_t failCount; }; event PipelineStats::LateOmZ { uint32_t drawId; uint64_t passCount; uint64_t failCount; }; event PipelineStats::LateOmStencil { uint32_t drawId; uint64_t passCount; uint64_t failCount; }; event PipelineStats::GSInputPrims { uint32_t drawId; uint64_t inputPrimCount; }; event PipelineStats::GSPrimsGen { uint32_t drawId; uint64_t primGeneratedCount; }; event PipelineStats::GSVertsInput { uint32_t drawId; uint64_t vertsInput; }; event PipelineStats::TessPrims { uint32_t drawId; uint64_t primCount; }; event PipelineStats::RasterTiles { uint32_t drawId; uint32_t rastTileCount; }; event PipelineStats::ClipperEvent { uint32_t drawId; uint32_t trivialRejectCount; uint32_t trivialAcceptCount; uint32_t mustClipCount; }; event PipelineStats::CullEvent { uint32_t drawId; uint64_t backfacePrimCount; uint64_t degeneratePrimCount; }; event PipelineStats::AlphaEvent { uint32_t drawId; uint32_t alphaTestCount; uint32_t alphaBlendCount; }; event ShaderStats::VSInfo { uint32_t drawId; uint32_t numInstExecuted; uint32_t numSampleExecuted; uint32_t numSampleLExecuted; uint32_t numSampleBExecuted; uint32_t numSampleCExecuted; uint32_t numSampleCLZExecuted; uint32_t numSampleCDExecuted; uint32_t numGather4Executed; uint32_t numGather4CExecuted; uint32_t numGather4CPOExecuted; uint32_t numGather4CPOCExecuted; uint32_t numLodExecuted; }; event ShaderStats::HSInfo { uint32_t drawId; uint32_t numInstExecuted; uint32_t numSampleExecuted; uint32_t numSampleLExecuted; uint32_t numSampleBExecuted; uint32_t numSampleCExecuted; uint32_t numSampleCLZExecuted; uint32_t numSampleCDExecuted; uint32_t numGather4Executed; uint32_t numGather4CExecuted; uint32_t numGather4CPOExecuted; uint32_t numGather4CPOCExecuted; uint32_t numLodExecuted; }; event ShaderStats::DSInfo { uint32_t drawId; uint32_t numInstExecuted; uint32_t numSampleExecuted; uint32_t numSampleLExecuted; uint32_t numSampleBExecuted; uint32_t numSampleCExecuted; uint32_t numSampleCLZExecuted; uint32_t numSampleCDExecuted; uint32_t numGather4Executed; uint32_t numGather4CExecuted; uint32_t numGather4CPOExecuted; uint32_t numGather4CPOCExecuted; uint32_t numLodExecuted; }; event ShaderStats::GSInfo { uint32_t drawId; uint32_t numInstExecuted; uint32_t numSampleExecuted; uint32_t numSampleLExecuted; uint32_t numSampleBExecuted; uint32_t numSampleCExecuted; uint32_t numSampleCLZExecuted; uint32_t numSampleCDExecuted; uint32_t numGather4Executed; uint32_t numGather4CExecuted; uint32_t numGather4CPOExecuted; uint32_t numGather4CPOCExecuted; uint32_t numLodExecuted; }; event ShaderStats::PSInfo { uint32_t drawId; uint32_t numInstExecuted; uint32_t numSampleExecuted; uint32_t numSampleLExecuted; uint32_t numSampleBExecuted; uint32_t numSampleCExecuted; uint32_t numSampleCLZExecuted; uint32_t numSampleCDExecuted; uint32_t numGather4Executed; uint32_t numGather4CExecuted; uint32_t numGather4CPOExecuted; uint32_t numGather4CPOCExecuted; uint32_t numLodExecuted; }; event ShaderStats::CSInfo { uint32_t drawId; uint32_t numInstExecuted; uint32_t numSampleExecuted; uint32_t numSampleLExecuted; uint32_t numSampleBExecuted; uint32_t numSampleCExecuted; uint32_t numSampleCLZExecuted; uint32_t numSampleCDExecuted; uint32_t numGather4Executed; uint32_t numGather4CExecuted; uint32_t numGather4CPOExecuted; uint32_t numGather4CPOCExecuted; uint32_t numLodExecuted; };