1 /* Capstone Disassembly Engine */
2 /* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2015 */
3
4 #ifdef CAPSTONE_HAS_ARM
5
6 #include <stdio.h> // debug
7 #include <string.h>
8
9 #include "../../cs_priv.h"
10
11 #include "ARMMapping.h"
12
13 #define GET_INSTRINFO_ENUM
14 #include "ARMGenInstrInfo.inc"
15
16 #ifndef CAPSTONE_DIET
17 static const name_map reg_name_maps[] = {
18 { ARM_REG_INVALID, NULL },
19 { ARM_REG_APSR, "apsr"},
20 { ARM_REG_APSR_NZCV, "apsr_nzcv"},
21 { ARM_REG_CPSR, "cpsr"},
22 { ARM_REG_FPEXC, "fpexc"},
23 { ARM_REG_FPINST, "fpinst"},
24 { ARM_REG_FPSCR, "fpscr"},
25 { ARM_REG_FPSCR_NZCV, "fpscr_nzcv"},
26 { ARM_REG_FPSID, "fpsid"},
27 { ARM_REG_ITSTATE, "itstate"},
28 { ARM_REG_LR, "lr"},
29 { ARM_REG_PC, "pc"},
30 { ARM_REG_SP, "sp"},
31 { ARM_REG_SPSR, "spsr"},
32 { ARM_REG_D0, "d0"},
33 { ARM_REG_D1, "d1"},
34 { ARM_REG_D2, "d2"},
35 { ARM_REG_D3, "d3"},
36 { ARM_REG_D4, "d4"},
37 { ARM_REG_D5, "d5"},
38 { ARM_REG_D6, "d6"},
39 { ARM_REG_D7, "d7"},
40 { ARM_REG_D8, "d8"},
41 { ARM_REG_D9, "d9"},
42 { ARM_REG_D10, "d10"},
43 { ARM_REG_D11, "d11"},
44 { ARM_REG_D12, "d12"},
45 { ARM_REG_D13, "d13"},
46 { ARM_REG_D14, "d14"},
47 { ARM_REG_D15, "d15"},
48 { ARM_REG_D16, "d16"},
49 { ARM_REG_D17, "d17"},
50 { ARM_REG_D18, "d18"},
51 { ARM_REG_D19, "d19"},
52 { ARM_REG_D20, "d20"},
53 { ARM_REG_D21, "d21"},
54 { ARM_REG_D22, "d22"},
55 { ARM_REG_D23, "d23"},
56 { ARM_REG_D24, "d24"},
57 { ARM_REG_D25, "d25"},
58 { ARM_REG_D26, "d26"},
59 { ARM_REG_D27, "d27"},
60 { ARM_REG_D28, "d28"},
61 { ARM_REG_D29, "d29"},
62 { ARM_REG_D30, "d30"},
63 { ARM_REG_D31, "d31"},
64 { ARM_REG_FPINST2, "fpinst2"},
65 { ARM_REG_MVFR0, "mvfr0"},
66 { ARM_REG_MVFR1, "mvfr1"},
67 { ARM_REG_MVFR2, "mvfr2"},
68 { ARM_REG_Q0, "q0"},
69 { ARM_REG_Q1, "q1"},
70 { ARM_REG_Q2, "q2"},
71 { ARM_REG_Q3, "q3"},
72 { ARM_REG_Q4, "q4"},
73 { ARM_REG_Q5, "q5"},
74 { ARM_REG_Q6, "q6"},
75 { ARM_REG_Q7, "q7"},
76 { ARM_REG_Q8, "q8"},
77 { ARM_REG_Q9, "q9"},
78 { ARM_REG_Q10, "q10"},
79 { ARM_REG_Q11, "q11"},
80 { ARM_REG_Q12, "q12"},
81 { ARM_REG_Q13, "q13"},
82 { ARM_REG_Q14, "q14"},
83 { ARM_REG_Q15, "q15"},
84 { ARM_REG_R0, "r0"},
85 { ARM_REG_R1, "r1"},
86 { ARM_REG_R2, "r2"},
87 { ARM_REG_R3, "r3"},
88 { ARM_REG_R4, "r4"},
89 { ARM_REG_R5, "r5"},
90 { ARM_REG_R6, "r6"},
91 { ARM_REG_R7, "r7"},
92 { ARM_REG_R8, "r8"},
93 { ARM_REG_R9, "sb"},
94 { ARM_REG_R10, "sl"},
95 { ARM_REG_R11, "fp"},
96 { ARM_REG_R12, "ip"},
97 { ARM_REG_S0, "s0"},
98 { ARM_REG_S1, "s1"},
99 { ARM_REG_S2, "s2"},
100 { ARM_REG_S3, "s3"},
101 { ARM_REG_S4, "s4"},
102 { ARM_REG_S5, "s5"},
103 { ARM_REG_S6, "s6"},
104 { ARM_REG_S7, "s7"},
105 { ARM_REG_S8, "s8"},
106 { ARM_REG_S9, "s9"},
107 { ARM_REG_S10, "s10"},
108 { ARM_REG_S11, "s11"},
109 { ARM_REG_S12, "s12"},
110 { ARM_REG_S13, "s13"},
111 { ARM_REG_S14, "s14"},
112 { ARM_REG_S15, "s15"},
113 { ARM_REG_S16, "s16"},
114 { ARM_REG_S17, "s17"},
115 { ARM_REG_S18, "s18"},
116 { ARM_REG_S19, "s19"},
117 { ARM_REG_S20, "s20"},
118 { ARM_REG_S21, "s21"},
119 { ARM_REG_S22, "s22"},
120 { ARM_REG_S23, "s23"},
121 { ARM_REG_S24, "s24"},
122 { ARM_REG_S25, "s25"},
123 { ARM_REG_S26, "s26"},
124 { ARM_REG_S27, "s27"},
125 { ARM_REG_S28, "s28"},
126 { ARM_REG_S29, "s29"},
127 { ARM_REG_S30, "s30"},
128 { ARM_REG_S31, "s31"},
129 };
130 static const name_map reg_name_maps2[] = {
131 { ARM_REG_INVALID, NULL },
132 { ARM_REG_APSR, "apsr"},
133 { ARM_REG_APSR_NZCV, "apsr_nzcv"},
134 { ARM_REG_CPSR, "cpsr"},
135 { ARM_REG_FPEXC, "fpexc"},
136 { ARM_REG_FPINST, "fpinst"},
137 { ARM_REG_FPSCR, "fpscr"},
138 { ARM_REG_FPSCR_NZCV, "fpscr_nzcv"},
139 { ARM_REG_FPSID, "fpsid"},
140 { ARM_REG_ITSTATE, "itstate"},
141 { ARM_REG_LR, "lr"},
142 { ARM_REG_PC, "pc"},
143 { ARM_REG_SP, "sp"},
144 { ARM_REG_SPSR, "spsr"},
145 { ARM_REG_D0, "d0"},
146 { ARM_REG_D1, "d1"},
147 { ARM_REG_D2, "d2"},
148 { ARM_REG_D3, "d3"},
149 { ARM_REG_D4, "d4"},
150 { ARM_REG_D5, "d5"},
151 { ARM_REG_D6, "d6"},
152 { ARM_REG_D7, "d7"},
153 { ARM_REG_D8, "d8"},
154 { ARM_REG_D9, "d9"},
155 { ARM_REG_D10, "d10"},
156 { ARM_REG_D11, "d11"},
157 { ARM_REG_D12, "d12"},
158 { ARM_REG_D13, "d13"},
159 { ARM_REG_D14, "d14"},
160 { ARM_REG_D15, "d15"},
161 { ARM_REG_D16, "d16"},
162 { ARM_REG_D17, "d17"},
163 { ARM_REG_D18, "d18"},
164 { ARM_REG_D19, "d19"},
165 { ARM_REG_D20, "d20"},
166 { ARM_REG_D21, "d21"},
167 { ARM_REG_D22, "d22"},
168 { ARM_REG_D23, "d23"},
169 { ARM_REG_D24, "d24"},
170 { ARM_REG_D25, "d25"},
171 { ARM_REG_D26, "d26"},
172 { ARM_REG_D27, "d27"},
173 { ARM_REG_D28, "d28"},
174 { ARM_REG_D29, "d29"},
175 { ARM_REG_D30, "d30"},
176 { ARM_REG_D31, "d31"},
177 { ARM_REG_FPINST2, "fpinst2"},
178 { ARM_REG_MVFR0, "mvfr0"},
179 { ARM_REG_MVFR1, "mvfr1"},
180 { ARM_REG_MVFR2, "mvfr2"},
181 { ARM_REG_Q0, "q0"},
182 { ARM_REG_Q1, "q1"},
183 { ARM_REG_Q2, "q2"},
184 { ARM_REG_Q3, "q3"},
185 { ARM_REG_Q4, "q4"},
186 { ARM_REG_Q5, "q5"},
187 { ARM_REG_Q6, "q6"},
188 { ARM_REG_Q7, "q7"},
189 { ARM_REG_Q8, "q8"},
190 { ARM_REG_Q9, "q9"},
191 { ARM_REG_Q10, "q10"},
192 { ARM_REG_Q11, "q11"},
193 { ARM_REG_Q12, "q12"},
194 { ARM_REG_Q13, "q13"},
195 { ARM_REG_Q14, "q14"},
196 { ARM_REG_Q15, "q15"},
197 { ARM_REG_R0, "r0"},
198 { ARM_REG_R1, "r1"},
199 { ARM_REG_R2, "r2"},
200 { ARM_REG_R3, "r3"},
201 { ARM_REG_R4, "r4"},
202 { ARM_REG_R5, "r5"},
203 { ARM_REG_R6, "r6"},
204 { ARM_REG_R7, "r7"},
205 { ARM_REG_R8, "r8"},
206 { ARM_REG_R9, "r9"},
207 { ARM_REG_R10, "r10"},
208 { ARM_REG_R11, "r11"},
209 { ARM_REG_R12, "r12"},
210 { ARM_REG_S0, "s0"},
211 { ARM_REG_S1, "s1"},
212 { ARM_REG_S2, "s2"},
213 { ARM_REG_S3, "s3"},
214 { ARM_REG_S4, "s4"},
215 { ARM_REG_S5, "s5"},
216 { ARM_REG_S6, "s6"},
217 { ARM_REG_S7, "s7"},
218 { ARM_REG_S8, "s8"},
219 { ARM_REG_S9, "s9"},
220 { ARM_REG_S10, "s10"},
221 { ARM_REG_S11, "s11"},
222 { ARM_REG_S12, "s12"},
223 { ARM_REG_S13, "s13"},
224 { ARM_REG_S14, "s14"},
225 { ARM_REG_S15, "s15"},
226 { ARM_REG_S16, "s16"},
227 { ARM_REG_S17, "s17"},
228 { ARM_REG_S18, "s18"},
229 { ARM_REG_S19, "s19"},
230 { ARM_REG_S20, "s20"},
231 { ARM_REG_S21, "s21"},
232 { ARM_REG_S22, "s22"},
233 { ARM_REG_S23, "s23"},
234 { ARM_REG_S24, "s24"},
235 { ARM_REG_S25, "s25"},
236 { ARM_REG_S26, "s26"},
237 { ARM_REG_S27, "s27"},
238 { ARM_REG_S28, "s28"},
239 { ARM_REG_S29, "s29"},
240 { ARM_REG_S30, "s30"},
241 { ARM_REG_S31, "s31"},
242 };
243 #endif
244
ARM_reg_name(csh handle,unsigned int reg)245 const char *ARM_reg_name(csh handle, unsigned int reg)
246 {
247 #ifndef CAPSTONE_DIET
248 if (reg >= ARR_SIZE(reg_name_maps))
249 return NULL;
250
251 return reg_name_maps[reg].name;
252 #else
253 return NULL;
254 #endif
255 }
256
ARM_reg_name2(csh handle,unsigned int reg)257 const char *ARM_reg_name2(csh handle, unsigned int reg)
258 {
259 #ifndef CAPSTONE_DIET
260 if (reg >= ARR_SIZE(reg_name_maps2))
261 return NULL;
262
263 return reg_name_maps2[reg].name;
264 #else
265 return NULL;
266 #endif
267 }
268
269 static const insn_map insns[] = {
270 // dummy item
271 {
272 0, 0,
273 #ifndef CAPSTONE_DIET
274 { 0 }, { 0 }, { 0 }, 0, 0
275 #endif
276 },
277
278 #include "ARMMappingInsn.inc"
279 };
280
ARM_get_insn_id(cs_struct * h,cs_insn * insn,unsigned int id)281 void ARM_get_insn_id(cs_struct *h, cs_insn *insn, unsigned int id)
282 {
283 int i = insn_find(insns, ARR_SIZE(insns), id, &h->insn_cache);
284 //printf(">> id = %u\n", id);
285 if (i != 0) {
286 insn->id = insns[i].mapid;
287
288 if (h->detail) {
289 #ifndef CAPSTONE_DIET
290 cs_struct handle;
291 handle.detail = h->detail;
292
293 memcpy(insn->detail->regs_read, insns[i].regs_use, sizeof(insns[i].regs_use));
294 insn->detail->regs_read_count = (uint8_t)count_positive(insns[i].regs_use);
295
296 memcpy(insn->detail->regs_write, insns[i].regs_mod, sizeof(insns[i].regs_mod));
297 insn->detail->regs_write_count = (uint8_t)count_positive(insns[i].regs_mod);
298
299 memcpy(insn->detail->groups, insns[i].groups, sizeof(insns[i].groups));
300 insn->detail->groups_count = (uint8_t)count_positive8(insns[i].groups);
301
302 insn->detail->arm.update_flags = cs_reg_write((csh)&handle, insn, ARM_REG_CPSR);
303
304 if (insns[i].branch || insns[i].indirect_branch) {
305 // this insn also belongs to JUMP group. add JUMP group
306 insn->detail->groups[insn->detail->groups_count] = ARM_GRP_JUMP;
307 insn->detail->groups_count++;
308 }
309 #endif
310 }
311 }
312 }
313
314 #ifndef CAPSTONE_DIET
315 static const name_map insn_name_maps[] = {
316 { ARM_INS_INVALID, NULL },
317
318 { ARM_INS_ADC, "adc" },
319 { ARM_INS_ADD, "add" },
320 { ARM_INS_ADR, "adr" },
321 { ARM_INS_AESD, "aesd" },
322 { ARM_INS_AESE, "aese" },
323 { ARM_INS_AESIMC, "aesimc" },
324 { ARM_INS_AESMC, "aesmc" },
325 { ARM_INS_AND, "and" },
326 { ARM_INS_BFC, "bfc" },
327 { ARM_INS_BFI, "bfi" },
328 { ARM_INS_BIC, "bic" },
329 { ARM_INS_BKPT, "bkpt" },
330 { ARM_INS_BL, "bl" },
331 { ARM_INS_BLX, "blx" },
332 { ARM_INS_BX, "bx" },
333 { ARM_INS_BXJ, "bxj" },
334 { ARM_INS_B, "b" },
335 { ARM_INS_CDP, "cdp" },
336 { ARM_INS_CDP2, "cdp2" },
337 { ARM_INS_CLREX, "clrex" },
338 { ARM_INS_CLZ, "clz" },
339 { ARM_INS_CMN, "cmn" },
340 { ARM_INS_CMP, "cmp" },
341 { ARM_INS_CPS, "cps" },
342 { ARM_INS_CRC32B, "crc32b" },
343 { ARM_INS_CRC32CB, "crc32cb" },
344 { ARM_INS_CRC32CH, "crc32ch" },
345 { ARM_INS_CRC32CW, "crc32cw" },
346 { ARM_INS_CRC32H, "crc32h" },
347 { ARM_INS_CRC32W, "crc32w" },
348 { ARM_INS_DBG, "dbg" },
349 { ARM_INS_DMB, "dmb" },
350 { ARM_INS_DSB, "dsb" },
351 { ARM_INS_EOR, "eor" },
352 { ARM_INS_ERET, "eret" },
353 { ARM_INS_VMOV, "vmov" },
354 { ARM_INS_FLDMDBX, "fldmdbx" },
355 { ARM_INS_FLDMIAX, "fldmiax" },
356 { ARM_INS_VMRS, "vmrs" },
357 { ARM_INS_FSTMDBX, "fstmdbx" },
358 { ARM_INS_FSTMIAX, "fstmiax" },
359 { ARM_INS_HINT, "hint" },
360 { ARM_INS_HLT, "hlt" },
361 { ARM_INS_HVC, "hvc" },
362 { ARM_INS_ISB, "isb" },
363 { ARM_INS_LDA, "lda" },
364 { ARM_INS_LDAB, "ldab" },
365 { ARM_INS_LDAEX, "ldaex" },
366 { ARM_INS_LDAEXB, "ldaexb" },
367 { ARM_INS_LDAEXD, "ldaexd" },
368 { ARM_INS_LDAEXH, "ldaexh" },
369 { ARM_INS_LDAH, "ldah" },
370 { ARM_INS_LDC2L, "ldc2l" },
371 { ARM_INS_LDC2, "ldc2" },
372 { ARM_INS_LDCL, "ldcl" },
373 { ARM_INS_LDC, "ldc" },
374 { ARM_INS_LDMDA, "ldmda" },
375 { ARM_INS_LDMDB, "ldmdb" },
376 { ARM_INS_LDM, "ldm" },
377 { ARM_INS_LDMIB, "ldmib" },
378 { ARM_INS_LDRBT, "ldrbt" },
379 { ARM_INS_LDRB, "ldrb" },
380 { ARM_INS_LDRD, "ldrd" },
381 { ARM_INS_LDREX, "ldrex" },
382 { ARM_INS_LDREXB, "ldrexb" },
383 { ARM_INS_LDREXD, "ldrexd" },
384 { ARM_INS_LDREXH, "ldrexh" },
385 { ARM_INS_LDRH, "ldrh" },
386 { ARM_INS_LDRHT, "ldrht" },
387 { ARM_INS_LDRSB, "ldrsb" },
388 { ARM_INS_LDRSBT, "ldrsbt" },
389 { ARM_INS_LDRSH, "ldrsh" },
390 { ARM_INS_LDRSHT, "ldrsht" },
391 { ARM_INS_LDRT, "ldrt" },
392 { ARM_INS_LDR, "ldr" },
393 { ARM_INS_MCR, "mcr" },
394 { ARM_INS_MCR2, "mcr2" },
395 { ARM_INS_MCRR, "mcrr" },
396 { ARM_INS_MCRR2, "mcrr2" },
397 { ARM_INS_MLA, "mla" },
398 { ARM_INS_MLS, "mls" },
399 { ARM_INS_MOV, "mov" },
400 { ARM_INS_MOVT, "movt" },
401 { ARM_INS_MOVW, "movw" },
402 { ARM_INS_MRC, "mrc" },
403 { ARM_INS_MRC2, "mrc2" },
404 { ARM_INS_MRRC, "mrrc" },
405 { ARM_INS_MRRC2, "mrrc2" },
406 { ARM_INS_MRS, "mrs" },
407 { ARM_INS_MSR, "msr" },
408 { ARM_INS_MUL, "mul" },
409 { ARM_INS_MVN, "mvn" },
410 { ARM_INS_ORR, "orr" },
411 { ARM_INS_PKHBT, "pkhbt" },
412 { ARM_INS_PKHTB, "pkhtb" },
413 { ARM_INS_PLDW, "pldw" },
414 { ARM_INS_PLD, "pld" },
415 { ARM_INS_PLI, "pli" },
416 { ARM_INS_QADD, "qadd" },
417 { ARM_INS_QADD16, "qadd16" },
418 { ARM_INS_QADD8, "qadd8" },
419 { ARM_INS_QASX, "qasx" },
420 { ARM_INS_QDADD, "qdadd" },
421 { ARM_INS_QDSUB, "qdsub" },
422 { ARM_INS_QSAX, "qsax" },
423 { ARM_INS_QSUB, "qsub" },
424 { ARM_INS_QSUB16, "qsub16" },
425 { ARM_INS_QSUB8, "qsub8" },
426 { ARM_INS_RBIT, "rbit" },
427 { ARM_INS_REV, "rev" },
428 { ARM_INS_REV16, "rev16" },
429 { ARM_INS_REVSH, "revsh" },
430 { ARM_INS_RFEDA, "rfeda" },
431 { ARM_INS_RFEDB, "rfedb" },
432 { ARM_INS_RFEIA, "rfeia" },
433 { ARM_INS_RFEIB, "rfeib" },
434 { ARM_INS_RSB, "rsb" },
435 { ARM_INS_RSC, "rsc" },
436 { ARM_INS_SADD16, "sadd16" },
437 { ARM_INS_SADD8, "sadd8" },
438 { ARM_INS_SASX, "sasx" },
439 { ARM_INS_SBC, "sbc" },
440 { ARM_INS_SBFX, "sbfx" },
441 { ARM_INS_SDIV, "sdiv" },
442 { ARM_INS_SEL, "sel" },
443 { ARM_INS_SETEND, "setend" },
444 { ARM_INS_SHA1C, "sha1c" },
445 { ARM_INS_SHA1H, "sha1h" },
446 { ARM_INS_SHA1M, "sha1m" },
447 { ARM_INS_SHA1P, "sha1p" },
448 { ARM_INS_SHA1SU0, "sha1su0" },
449 { ARM_INS_SHA1SU1, "sha1su1" },
450 { ARM_INS_SHA256H, "sha256h" },
451 { ARM_INS_SHA256H2, "sha256h2" },
452 { ARM_INS_SHA256SU0, "sha256su0" },
453 { ARM_INS_SHA256SU1, "sha256su1" },
454 { ARM_INS_SHADD16, "shadd16" },
455 { ARM_INS_SHADD8, "shadd8" },
456 { ARM_INS_SHASX, "shasx" },
457 { ARM_INS_SHSAX, "shsax" },
458 { ARM_INS_SHSUB16, "shsub16" },
459 { ARM_INS_SHSUB8, "shsub8" },
460 { ARM_INS_SMC, "smc" },
461 { ARM_INS_SMLABB, "smlabb" },
462 { ARM_INS_SMLABT, "smlabt" },
463 { ARM_INS_SMLAD, "smlad" },
464 { ARM_INS_SMLADX, "smladx" },
465 { ARM_INS_SMLAL, "smlal" },
466 { ARM_INS_SMLALBB, "smlalbb" },
467 { ARM_INS_SMLALBT, "smlalbt" },
468 { ARM_INS_SMLALD, "smlald" },
469 { ARM_INS_SMLALDX, "smlaldx" },
470 { ARM_INS_SMLALTB, "smlaltb" },
471 { ARM_INS_SMLALTT, "smlaltt" },
472 { ARM_INS_SMLATB, "smlatb" },
473 { ARM_INS_SMLATT, "smlatt" },
474 { ARM_INS_SMLAWB, "smlawb" },
475 { ARM_INS_SMLAWT, "smlawt" },
476 { ARM_INS_SMLSD, "smlsd" },
477 { ARM_INS_SMLSDX, "smlsdx" },
478 { ARM_INS_SMLSLD, "smlsld" },
479 { ARM_INS_SMLSLDX, "smlsldx" },
480 { ARM_INS_SMMLA, "smmla" },
481 { ARM_INS_SMMLAR, "smmlar" },
482 { ARM_INS_SMMLS, "smmls" },
483 { ARM_INS_SMMLSR, "smmlsr" },
484 { ARM_INS_SMMUL, "smmul" },
485 { ARM_INS_SMMULR, "smmulr" },
486 { ARM_INS_SMUAD, "smuad" },
487 { ARM_INS_SMUADX, "smuadx" },
488 { ARM_INS_SMULBB, "smulbb" },
489 { ARM_INS_SMULBT, "smulbt" },
490 { ARM_INS_SMULL, "smull" },
491 { ARM_INS_SMULTB, "smultb" },
492 { ARM_INS_SMULTT, "smultt" },
493 { ARM_INS_SMULWB, "smulwb" },
494 { ARM_INS_SMULWT, "smulwt" },
495 { ARM_INS_SMUSD, "smusd" },
496 { ARM_INS_SMUSDX, "smusdx" },
497 { ARM_INS_SRSDA, "srsda" },
498 { ARM_INS_SRSDB, "srsdb" },
499 { ARM_INS_SRSIA, "srsia" },
500 { ARM_INS_SRSIB, "srsib" },
501 { ARM_INS_SSAT, "ssat" },
502 { ARM_INS_SSAT16, "ssat16" },
503 { ARM_INS_SSAX, "ssax" },
504 { ARM_INS_SSUB16, "ssub16" },
505 { ARM_INS_SSUB8, "ssub8" },
506 { ARM_INS_STC2L, "stc2l" },
507 { ARM_INS_STC2, "stc2" },
508 { ARM_INS_STCL, "stcl" },
509 { ARM_INS_STC, "stc" },
510 { ARM_INS_STL, "stl" },
511 { ARM_INS_STLB, "stlb" },
512 { ARM_INS_STLEX, "stlex" },
513 { ARM_INS_STLEXB, "stlexb" },
514 { ARM_INS_STLEXD, "stlexd" },
515 { ARM_INS_STLEXH, "stlexh" },
516 { ARM_INS_STLH, "stlh" },
517 { ARM_INS_STMDA, "stmda" },
518 { ARM_INS_STMDB, "stmdb" },
519 { ARM_INS_STM, "stm" },
520 { ARM_INS_STMIB, "stmib" },
521 { ARM_INS_STRBT, "strbt" },
522 { ARM_INS_STRB, "strb" },
523 { ARM_INS_STRD, "strd" },
524 { ARM_INS_STREX, "strex" },
525 { ARM_INS_STREXB, "strexb" },
526 { ARM_INS_STREXD, "strexd" },
527 { ARM_INS_STREXH, "strexh" },
528 { ARM_INS_STRH, "strh" },
529 { ARM_INS_STRHT, "strht" },
530 { ARM_INS_STRT, "strt" },
531 { ARM_INS_STR, "str" },
532 { ARM_INS_SUB, "sub" },
533 { ARM_INS_SVC, "svc" },
534 { ARM_INS_SWP, "swp" },
535 { ARM_INS_SWPB, "swpb" },
536 { ARM_INS_SXTAB, "sxtab" },
537 { ARM_INS_SXTAB16, "sxtab16" },
538 { ARM_INS_SXTAH, "sxtah" },
539 { ARM_INS_SXTB, "sxtb" },
540 { ARM_INS_SXTB16, "sxtb16" },
541 { ARM_INS_SXTH, "sxth" },
542 { ARM_INS_TEQ, "teq" },
543 { ARM_INS_TRAP, "trap" },
544 { ARM_INS_TST, "tst" },
545 { ARM_INS_UADD16, "uadd16" },
546 { ARM_INS_UADD8, "uadd8" },
547 { ARM_INS_UASX, "uasx" },
548 { ARM_INS_UBFX, "ubfx" },
549 { ARM_INS_UDF, "udf" },
550 { ARM_INS_UDIV, "udiv" },
551 { ARM_INS_UHADD16, "uhadd16" },
552 { ARM_INS_UHADD8, "uhadd8" },
553 { ARM_INS_UHASX, "uhasx" },
554 { ARM_INS_UHSAX, "uhsax" },
555 { ARM_INS_UHSUB16, "uhsub16" },
556 { ARM_INS_UHSUB8, "uhsub8" },
557 { ARM_INS_UMAAL, "umaal" },
558 { ARM_INS_UMLAL, "umlal" },
559 { ARM_INS_UMULL, "umull" },
560 { ARM_INS_UQADD16, "uqadd16" },
561 { ARM_INS_UQADD8, "uqadd8" },
562 { ARM_INS_UQASX, "uqasx" },
563 { ARM_INS_UQSAX, "uqsax" },
564 { ARM_INS_UQSUB16, "uqsub16" },
565 { ARM_INS_UQSUB8, "uqsub8" },
566 { ARM_INS_USAD8, "usad8" },
567 { ARM_INS_USADA8, "usada8" },
568 { ARM_INS_USAT, "usat" },
569 { ARM_INS_USAT16, "usat16" },
570 { ARM_INS_USAX, "usax" },
571 { ARM_INS_USUB16, "usub16" },
572 { ARM_INS_USUB8, "usub8" },
573 { ARM_INS_UXTAB, "uxtab" },
574 { ARM_INS_UXTAB16, "uxtab16" },
575 { ARM_INS_UXTAH, "uxtah" },
576 { ARM_INS_UXTB, "uxtb" },
577 { ARM_INS_UXTB16, "uxtb16" },
578 { ARM_INS_UXTH, "uxth" },
579 { ARM_INS_VABAL, "vabal" },
580 { ARM_INS_VABA, "vaba" },
581 { ARM_INS_VABDL, "vabdl" },
582 { ARM_INS_VABD, "vabd" },
583 { ARM_INS_VABS, "vabs" },
584 { ARM_INS_VACGE, "vacge" },
585 { ARM_INS_VACGT, "vacgt" },
586 { ARM_INS_VADD, "vadd" },
587 { ARM_INS_VADDHN, "vaddhn" },
588 { ARM_INS_VADDL, "vaddl" },
589 { ARM_INS_VADDW, "vaddw" },
590 { ARM_INS_VAND, "vand" },
591 { ARM_INS_VBIC, "vbic" },
592 { ARM_INS_VBIF, "vbif" },
593 { ARM_INS_VBIT, "vbit" },
594 { ARM_INS_VBSL, "vbsl" },
595 { ARM_INS_VCEQ, "vceq" },
596 { ARM_INS_VCGE, "vcge" },
597 { ARM_INS_VCGT, "vcgt" },
598 { ARM_INS_VCLE, "vcle" },
599 { ARM_INS_VCLS, "vcls" },
600 { ARM_INS_VCLT, "vclt" },
601 { ARM_INS_VCLZ, "vclz" },
602 { ARM_INS_VCMP, "vcmp" },
603 { ARM_INS_VCMPE, "vcmpe" },
604 { ARM_INS_VCNT, "vcnt" },
605 { ARM_INS_VCVTA, "vcvta" },
606 { ARM_INS_VCVTB, "vcvtb" },
607 { ARM_INS_VCVT, "vcvt" },
608 { ARM_INS_VCVTM, "vcvtm" },
609 { ARM_INS_VCVTN, "vcvtn" },
610 { ARM_INS_VCVTP, "vcvtp" },
611 { ARM_INS_VCVTT, "vcvtt" },
612 { ARM_INS_VDIV, "vdiv" },
613 { ARM_INS_VDUP, "vdup" },
614 { ARM_INS_VEOR, "veor" },
615 { ARM_INS_VEXT, "vext" },
616 { ARM_INS_VFMA, "vfma" },
617 { ARM_INS_VFMS, "vfms" },
618 { ARM_INS_VFNMA, "vfnma" },
619 { ARM_INS_VFNMS, "vfnms" },
620 { ARM_INS_VHADD, "vhadd" },
621 { ARM_INS_VHSUB, "vhsub" },
622 { ARM_INS_VLD1, "vld1" },
623 { ARM_INS_VLD2, "vld2" },
624 { ARM_INS_VLD3, "vld3" },
625 { ARM_INS_VLD4, "vld4" },
626 { ARM_INS_VLDMDB, "vldmdb" },
627 { ARM_INS_VLDMIA, "vldmia" },
628 { ARM_INS_VLDR, "vldr" },
629 { ARM_INS_VMAXNM, "vmaxnm" },
630 { ARM_INS_VMAX, "vmax" },
631 { ARM_INS_VMINNM, "vminnm" },
632 { ARM_INS_VMIN, "vmin" },
633 { ARM_INS_VMLA, "vmla" },
634 { ARM_INS_VMLAL, "vmlal" },
635 { ARM_INS_VMLS, "vmls" },
636 { ARM_INS_VMLSL, "vmlsl" },
637 { ARM_INS_VMOVL, "vmovl" },
638 { ARM_INS_VMOVN, "vmovn" },
639 { ARM_INS_VMSR, "vmsr" },
640 { ARM_INS_VMUL, "vmul" },
641 { ARM_INS_VMULL, "vmull" },
642 { ARM_INS_VMVN, "vmvn" },
643 { ARM_INS_VNEG, "vneg" },
644 { ARM_INS_VNMLA, "vnmla" },
645 { ARM_INS_VNMLS, "vnmls" },
646 { ARM_INS_VNMUL, "vnmul" },
647 { ARM_INS_VORN, "vorn" },
648 { ARM_INS_VORR, "vorr" },
649 { ARM_INS_VPADAL, "vpadal" },
650 { ARM_INS_VPADDL, "vpaddl" },
651 { ARM_INS_VPADD, "vpadd" },
652 { ARM_INS_VPMAX, "vpmax" },
653 { ARM_INS_VPMIN, "vpmin" },
654 { ARM_INS_VQABS, "vqabs" },
655 { ARM_INS_VQADD, "vqadd" },
656 { ARM_INS_VQDMLAL, "vqdmlal" },
657 { ARM_INS_VQDMLSL, "vqdmlsl" },
658 { ARM_INS_VQDMULH, "vqdmulh" },
659 { ARM_INS_VQDMULL, "vqdmull" },
660 { ARM_INS_VQMOVUN, "vqmovun" },
661 { ARM_INS_VQMOVN, "vqmovn" },
662 { ARM_INS_VQNEG, "vqneg" },
663 { ARM_INS_VQRDMULH, "vqrdmulh" },
664 { ARM_INS_VQRSHL, "vqrshl" },
665 { ARM_INS_VQRSHRN, "vqrshrn" },
666 { ARM_INS_VQRSHRUN, "vqrshrun" },
667 { ARM_INS_VQSHL, "vqshl" },
668 { ARM_INS_VQSHLU, "vqshlu" },
669 { ARM_INS_VQSHRN, "vqshrn" },
670 { ARM_INS_VQSHRUN, "vqshrun" },
671 { ARM_INS_VQSUB, "vqsub" },
672 { ARM_INS_VRADDHN, "vraddhn" },
673 { ARM_INS_VRECPE, "vrecpe" },
674 { ARM_INS_VRECPS, "vrecps" },
675 { ARM_INS_VREV16, "vrev16" },
676 { ARM_INS_VREV32, "vrev32" },
677 { ARM_INS_VREV64, "vrev64" },
678 { ARM_INS_VRHADD, "vrhadd" },
679 { ARM_INS_VRINTA, "vrinta" },
680 { ARM_INS_VRINTM, "vrintm" },
681 { ARM_INS_VRINTN, "vrintn" },
682 { ARM_INS_VRINTP, "vrintp" },
683 { ARM_INS_VRINTR, "vrintr" },
684 { ARM_INS_VRINTX, "vrintx" },
685 { ARM_INS_VRINTZ, "vrintz" },
686 { ARM_INS_VRSHL, "vrshl" },
687 { ARM_INS_VRSHRN, "vrshrn" },
688 { ARM_INS_VRSHR, "vrshr" },
689 { ARM_INS_VRSQRTE, "vrsqrte" },
690 { ARM_INS_VRSQRTS, "vrsqrts" },
691 { ARM_INS_VRSRA, "vrsra" },
692 { ARM_INS_VRSUBHN, "vrsubhn" },
693 { ARM_INS_VSELEQ, "vseleq" },
694 { ARM_INS_VSELGE, "vselge" },
695 { ARM_INS_VSELGT, "vselgt" },
696 { ARM_INS_VSELVS, "vselvs" },
697 { ARM_INS_VSHLL, "vshll" },
698 { ARM_INS_VSHL, "vshl" },
699 { ARM_INS_VSHRN, "vshrn" },
700 { ARM_INS_VSHR, "vshr" },
701 { ARM_INS_VSLI, "vsli" },
702 { ARM_INS_VSQRT, "vsqrt" },
703 { ARM_INS_VSRA, "vsra" },
704 { ARM_INS_VSRI, "vsri" },
705 { ARM_INS_VST1, "vst1" },
706 { ARM_INS_VST2, "vst2" },
707 { ARM_INS_VST3, "vst3" },
708 { ARM_INS_VST4, "vst4" },
709 { ARM_INS_VSTMDB, "vstmdb" },
710 { ARM_INS_VSTMIA, "vstmia" },
711 { ARM_INS_VSTR, "vstr" },
712 { ARM_INS_VSUB, "vsub" },
713 { ARM_INS_VSUBHN, "vsubhn" },
714 { ARM_INS_VSUBL, "vsubl" },
715 { ARM_INS_VSUBW, "vsubw" },
716 { ARM_INS_VSWP, "vswp" },
717 { ARM_INS_VTBL, "vtbl" },
718 { ARM_INS_VTBX, "vtbx" },
719 { ARM_INS_VCVTR, "vcvtr" },
720 { ARM_INS_VTRN, "vtrn" },
721 { ARM_INS_VTST, "vtst" },
722 { ARM_INS_VUZP, "vuzp" },
723 { ARM_INS_VZIP, "vzip" },
724 { ARM_INS_ADDW, "addw" },
725 { ARM_INS_ASR, "asr" },
726 { ARM_INS_DCPS1, "dcps1" },
727 { ARM_INS_DCPS2, "dcps2" },
728 { ARM_INS_DCPS3, "dcps3" },
729 { ARM_INS_IT, "it" },
730 { ARM_INS_LSL, "lsl" },
731 { ARM_INS_LSR, "lsr" },
732 { ARM_INS_ORN, "orn" },
733 { ARM_INS_ROR, "ror" },
734 { ARM_INS_RRX, "rrx" },
735 { ARM_INS_SUBW, "subw" },
736 { ARM_INS_TBB, "tbb" },
737 { ARM_INS_TBH, "tbh" },
738 { ARM_INS_CBNZ, "cbnz" },
739 { ARM_INS_CBZ, "cbz" },
740 { ARM_INS_POP, "pop" },
741 { ARM_INS_PUSH, "push" },
742
743 // special instructions
744 { ARM_INS_NOP, "nop" },
745 { ARM_INS_YIELD, "yield" },
746 { ARM_INS_WFE, "wfe" },
747 { ARM_INS_WFI, "wfi" },
748 { ARM_INS_SEV, "sev" },
749 { ARM_INS_SEVL, "sevl" },
750 { ARM_INS_VPUSH, "vpush" },
751 { ARM_INS_VPOP, "vpop" },
752 };
753 #endif
754
ARM_insn_name(csh handle,unsigned int id)755 const char *ARM_insn_name(csh handle, unsigned int id)
756 {
757 #ifndef CAPSTONE_DIET
758 if (id >= ARM_INS_ENDING)
759 return NULL;
760
761 return insn_name_maps[id].name;
762 #else
763 return NULL;
764 #endif
765 }
766
767 #ifndef CAPSTONE_DIET
768 static const name_map group_name_maps[] = {
769 // generic groups
770 { ARM_GRP_INVALID, NULL },
771 { ARM_GRP_JUMP, "jump" },
772 { ARM_GRP_CALL, "call" },
773 { ARM_GRP_INT, "int" },
774 { ARM_GRP_PRIVILEGE, "privilege" },
775 { ARM_GRP_BRANCH_RELATIVE, "branch_relative" },
776
777 // architecture-specific groups
778 { ARM_GRP_CRYPTO, "crypto" },
779 { ARM_GRP_DATABARRIER, "databarrier" },
780 { ARM_GRP_DIVIDE, "divide" },
781 { ARM_GRP_FPARMV8, "fparmv8" },
782 { ARM_GRP_MULTPRO, "multpro" },
783 { ARM_GRP_NEON, "neon" },
784 { ARM_GRP_T2EXTRACTPACK, "T2EXTRACTPACK" },
785 { ARM_GRP_THUMB2DSP, "THUMB2DSP" },
786 { ARM_GRP_TRUSTZONE, "TRUSTZONE" },
787 { ARM_GRP_V4T, "v4t" },
788 { ARM_GRP_V5T, "v5t" },
789 { ARM_GRP_V5TE, "v5te" },
790 { ARM_GRP_V6, "v6" },
791 { ARM_GRP_V6T2, "v6t2" },
792 { ARM_GRP_V7, "v7" },
793 { ARM_GRP_V8, "v8" },
794 { ARM_GRP_VFP2, "vfp2" },
795 { ARM_GRP_VFP3, "vfp3" },
796 { ARM_GRP_VFP4, "vfp4" },
797 { ARM_GRP_ARM, "arm" },
798 { ARM_GRP_MCLASS, "mclass" },
799 { ARM_GRP_NOTMCLASS, "notmclass" },
800 { ARM_GRP_THUMB, "thumb" },
801 { ARM_GRP_THUMB1ONLY, "thumb1only" },
802 { ARM_GRP_THUMB2, "thumb2" },
803 { ARM_GRP_PREV8, "prev8" },
804 { ARM_GRP_FPVMLX, "fpvmlx" },
805 { ARM_GRP_MULOPS, "mulops" },
806 { ARM_GRP_CRC, "crc" },
807 { ARM_GRP_DPVFP, "dpvfp" },
808 { ARM_GRP_V6M, "v6m" },
809 { ARM_GRP_VIRTUALIZATION, "virtualization" },
810 };
811 #endif
812
ARM_group_name(csh handle,unsigned int id)813 const char *ARM_group_name(csh handle, unsigned int id)
814 {
815 #ifndef CAPSTONE_DIET
816 return id2name(group_name_maps, ARR_SIZE(group_name_maps), id);
817 #else
818 return NULL;
819 #endif
820 }
821
822 // list all relative branch instructions
823 // ie: insns[i].branch && !insns[i].indirect_branch
824 static const unsigned int insn_rel[] = {
825 ARM_BL,
826 ARM_BLX_pred,
827 ARM_Bcc,
828 ARM_t2B,
829 ARM_t2Bcc,
830 ARM_tB,
831 ARM_tBcc,
832 ARM_tCBNZ,
833 ARM_tCBZ,
834 ARM_BL_pred,
835 ARM_BLXi,
836 ARM_tBL,
837 ARM_tBLXi,
838 0
839 };
840
841 static const unsigned int insn_blx_rel_to_arm[] = {
842 ARM_tBLXi,
843 0
844 };
845
846 // check if this insn is relative branch
ARM_rel_branch(cs_struct * h,unsigned int id)847 bool ARM_rel_branch(cs_struct *h, unsigned int id)
848 {
849 int i;
850
851 for (i = 0; insn_rel[i]; i++) {
852 if (id == insn_rel[i]) {
853 return true;
854 }
855 }
856
857 // not found
858 return false;
859 }
860
ARM_blx_to_arm_mode(cs_struct * h,unsigned int id)861 bool ARM_blx_to_arm_mode(cs_struct *h, unsigned int id) {
862 int i;
863
864 for (i = 0; insn_blx_rel_to_arm[i]; i++)
865 if (id == insn_blx_rel_to_arm[i])
866 return true;
867
868 // not found
869 return false;
870
871 }
872
873 #ifndef CAPSTONE_DIET
874 // map instruction to its characteristics
875 typedef struct insn_op {
876 uint8_t access[7];
877 } insn_op;
878
879 static insn_op insn_ops[] = {
880 {
881 // NULL item
882 { 0 }
883 },
884
885 #include "ARMMappingInsnOp.inc"
886 };
887
888 // given internal insn id, return operand access info
ARM_get_op_access(cs_struct * h,unsigned int id)889 uint8_t *ARM_get_op_access(cs_struct *h, unsigned int id)
890 {
891 int i = insn_find(insns, ARR_SIZE(insns), id, &h->insn_cache);
892 if (i != 0) {
893 return insn_ops[i].access;
894 }
895
896 return NULL;
897 }
898
ARM_reg_access(const cs_insn * insn,cs_regs regs_read,uint8_t * regs_read_count,cs_regs regs_write,uint8_t * regs_write_count)899 void ARM_reg_access(const cs_insn *insn,
900 cs_regs regs_read, uint8_t *regs_read_count,
901 cs_regs regs_write, uint8_t *regs_write_count)
902 {
903 uint8_t i;
904 uint8_t read_count, write_count;
905 cs_arm *arm = &(insn->detail->arm);
906
907 read_count = insn->detail->regs_read_count;
908 write_count = insn->detail->regs_write_count;
909
910 // implicit registers
911 memcpy(regs_read, insn->detail->regs_read, read_count * sizeof(insn->detail->regs_read[0]));
912 memcpy(regs_write, insn->detail->regs_write, write_count * sizeof(insn->detail->regs_write[0]));
913
914 // explicit registers
915 for (i = 0; i < arm->op_count; i++) {
916 cs_arm_op *op = &(arm->operands[i]);
917 switch((int)op->type) {
918 case ARM_OP_REG:
919 if ((op->access & CS_AC_READ) && !arr_exist(regs_read, read_count, op->reg)) {
920 regs_read[read_count] = (uint16_t)op->reg;
921 read_count++;
922 }
923 if ((op->access & CS_AC_WRITE) && !arr_exist(regs_write, write_count, op->reg)) {
924 regs_write[write_count] = (uint16_t)op->reg;
925 write_count++;
926 }
927 break;
928 case ARM_OP_MEM:
929 // registers appeared in memory references always being read
930 if ((op->mem.base != ARM_REG_INVALID) && !arr_exist(regs_read, read_count, op->mem.base)) {
931 regs_read[read_count] = (uint16_t)op->mem.base;
932 read_count++;
933 }
934 if ((op->mem.index != ARM_REG_INVALID) && !arr_exist(regs_read, read_count, op->mem.index)) {
935 regs_read[read_count] = (uint16_t)op->mem.index;
936 read_count++;
937 }
938 if ((arm->writeback) && (op->mem.base != ARM_REG_INVALID) && !arr_exist(regs_write, write_count, op->mem.base)) {
939 regs_write[write_count] = (uint16_t)op->mem.base;
940 write_count++;
941 }
942 default:
943 break;
944 }
945 }
946
947 *regs_read_count = read_count;
948 *regs_write_count = write_count;
949 }
950 #endif
951
952 #endif
953