1 /*
2 * Copyright © 2007 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 *
26 */
27
28 #ifndef _INTEL_CHIPSET_H
29 #define _INTEL_CHIPSET_H
30
31 #include <pciaccess.h>
32 #include <stdbool.h>
33
34 #define BIT(x) (1ul <<(x))
35
36 struct pci_device *intel_get_pci_device(void);
37
38 struct intel_device_info {
39 unsigned gen;
40 unsigned gt; /* 0 if unknown */
41 bool is_mobile : 1;
42 bool is_whitney : 1;
43 bool is_almador : 1;
44 bool is_brookdale : 1;
45 bool is_montara : 1;
46 bool is_springdale : 1;
47 bool is_grantsdale : 1;
48 bool is_alviso : 1;
49 bool is_lakeport : 1;
50 bool is_calistoga : 1;
51 bool is_bearlake : 1;
52 bool is_pineview : 1;
53 bool is_broadwater : 1;
54 bool is_crestline : 1;
55 bool is_eaglelake : 1;
56 bool is_cantiga : 1;
57 bool is_ironlake : 1;
58 bool is_arrandale : 1;
59 bool is_sandybridge : 1;
60 bool is_ivybridge : 1;
61 bool is_valleyview : 1;
62 bool is_haswell : 1;
63 bool is_broadwell : 1;
64 bool is_cherryview : 1;
65 bool is_skylake : 1;
66 bool is_broxton : 1;
67 bool is_kabylake : 1;
68 bool is_geminilake : 1;
69 bool is_coffeelake : 1;
70 bool is_cometlake : 1;
71 bool is_cannonlake : 1;
72 bool is_icelake : 1;
73 bool is_tigerlake : 1;
74 const char *codename;
75 };
76
77 const struct intel_device_info *intel_get_device_info(uint16_t devid) __attribute__((pure));
78
79 #ifdef ANDROID
intel_get_drm_devid(int fd)80 static inline uint32_t intel_get_drm_devid(int __attribute__((unused)) fd) { return 0U; }
intel_gen(uint16_t devid)81 static inline unsigned intel_gen(uint16_t __attribute__((unused)) devid) { return false; }
82 #else
83 uint32_t intel_get_drm_devid(int fd);
84 unsigned intel_gen(uint16_t devid) __attribute__((pure));
85 #endif
86
87 unsigned intel_gt(uint16_t devid) __attribute__((pure));
88
89 extern enum pch_type intel_pch;
90
91 enum pch_type {
92 PCH_NONE,
93 PCH_IBX,
94 PCH_CPT,
95 PCH_LPT,
96 };
97
98 void intel_check_pch(void);
99
100 #define HAS_IBX (intel_pch == PCH_IBX)
101 #define HAS_CPT (intel_pch == PCH_CPT)
102 #define HAS_LPT (intel_pch == PCH_LPT)
103
104 /* Exclude chipset #defines, they just add noise */
105 #ifndef __GTK_DOC_IGNORE__
106
107 #define PCI_CHIP_I810 0x7121
108 #define PCI_CHIP_I810_DC100 0x7123
109 #define PCI_CHIP_I810_E 0x7125
110 #define PCI_CHIP_I815 0x1132
111
112 #define PCI_CHIP_I830_M 0x3577
113 #define PCI_CHIP_845_G 0x2562
114 #define PCI_CHIP_I854_G 0x358e
115 #define PCI_CHIP_I855_GM 0x3582
116 #define PCI_CHIP_I865_G 0x2572
117
118 #define PCI_CHIP_I915_G 0x2582
119 #define PCI_CHIP_E7221_G 0x258A
120 #define PCI_CHIP_I915_GM 0x2592
121 #define PCI_CHIP_I945_G 0x2772
122 #define PCI_CHIP_I945_GM 0x27A2
123 #define PCI_CHIP_I945_GME 0x27AE
124
125 #define PCI_CHIP_I965_G 0x29A2
126 #define PCI_CHIP_I965_Q 0x2992
127 #define PCI_CHIP_I965_G_1 0x2982
128 #define PCI_CHIP_I946_GZ 0x2972
129 #define PCI_CHIP_I965_GM 0x2A02
130 #define PCI_CHIP_I965_GME 0x2A12
131
132 #define PCI_CHIP_GM45_GM 0x2A42
133
134 #define PCI_CHIP_Q45_G 0x2E12
135 #define PCI_CHIP_G45_G 0x2E22
136 #define PCI_CHIP_G41_G 0x2E32
137
138 #endif /* __GTK_DOC_IGNORE__ */
139
140 #define IS_915G(devid) (intel_get_device_info(devid)->is_grantsdale)
141 #define IS_915GM(devid) (intel_get_device_info(devid)->is_alviso)
142
143 #define IS_915(devid) (IS_915G(devid) || IS_915GM(devid))
144
145 #define IS_945G(devid) (intel_get_device_info(devid)->is_lakeport)
146 #define IS_945GM(devid) (intel_get_device_info(devid)->is_calistoga)
147
148 #define IS_945(devid) (IS_945G(devid) || \
149 IS_945GM(devid) || \
150 IS_G33(devid))
151
152 #define IS_PINEVIEW(devid) (intel_get_device_info(devid)->is_pineview)
153 #define IS_G33(devid) (intel_get_device_info(devid)->is_bearlake || \
154 intel_get_device_info(devid)->is_pineview)
155
156 #define IS_BROADWATER(devid) (intel_get_device_info(devid)->is_broadwater)
157 #define IS_CRESTLINE(devid) (intel_get_device_info(devid)->is_crestline)
158
159 #define IS_GM45(devid) (intel_get_device_info(devid)->is_cantiga)
160 #define IS_G45(devid) (intel_get_device_info(devid)->is_eaglelake)
161 #define IS_G4X(devid) (IS_G45(devid) || IS_GM45(devid))
162
163 #define IS_IRONLAKE(devid) (intel_get_device_info(devid)->is_ironlake)
164 #define IS_ARRANDALE(devid) (intel_get_device_info(devid)->is_arrandale)
165 #define IS_SANDYBRIDGE(devid) (intel_get_device_info(devid)->is_sandybridge)
166 #define IS_IVYBRIDGE(devid) (intel_get_device_info(devid)->is_ivybridge)
167 #define IS_VALLEYVIEW(devid) (intel_get_device_info(devid)->is_valleyview)
168 #define IS_HASWELL(devid) (intel_get_device_info(devid)->is_haswell)
169 #define IS_BROADWELL(devid) (intel_get_device_info(devid)->is_broadwell)
170 #define IS_CHERRYVIEW(devid) (intel_get_device_info(devid)->is_cherryview)
171 #define IS_SKYLAKE(devid) (intel_get_device_info(devid)->is_skylake)
172 #define IS_BROXTON(devid) (intel_get_device_info(devid)->is_broxton)
173 #define IS_KABYLAKE(devid) (intel_get_device_info(devid)->is_kabylake)
174 #define IS_GEMINILAKE(devid) (intel_get_device_info(devid)->is_geminilake)
175 #define IS_COFFEELAKE(devid) (intel_get_device_info(devid)->is_coffeelake)
176 #define IS_COMETLAKE(devid) (intel_get_device_info(devid)->is_cometlake)
177 #define IS_CANNONLAKE(devid) (intel_get_device_info(devid)->is_cannonlake)
178 #define IS_ICELAKE(devid) (intel_get_device_info(devid)->is_icelake)
179 #define IS_TIGERLAKE(devid) (intel_get_device_info(devid)->is_tigerlake)
180
181 #define IS_GEN(devid, x) (intel_get_device_info(devid)->gen & (1u << ((x)-1)))
182 #define AT_LEAST_GEN(devid, x) (intel_get_device_info(devid)->gen & -(1u << ((x)-1)))
183
184 #define IS_GEN2(devid) IS_GEN(devid, 2)
185 #define IS_GEN3(devid) IS_GEN(devid, 3)
186 #define IS_GEN4(devid) IS_GEN(devid, 4)
187 #define IS_GEN5(devid) IS_GEN(devid, 5)
188 #define IS_GEN6(devid) IS_GEN(devid, 6)
189 #define IS_GEN7(devid) IS_GEN(devid, 7)
190 #define IS_GEN8(devid) IS_GEN(devid, 8)
191 #define IS_GEN9(devid) IS_GEN(devid, 9)
192 #define IS_GEN10(devid) IS_GEN(devid, 10)
193 #define IS_GEN11(devid) IS_GEN(devid, 11)
194 #define IS_GEN12(devid) IS_GEN(devid, 12)
195
196 #define IS_MOBILE(devid) (intel_get_device_info(devid)->is_mobile)
197 #define IS_965(devid) AT_LEAST_GEN(devid, 4)
198
199 #define HAS_BSD_RING(devid) AT_LEAST_GEN(devid, 5)
200 #define HAS_BLT_RING(devid) AT_LEAST_GEN(devid, 6)
201
202 #define HAS_PCH_SPLIT(devid) (AT_LEAST_GEN(devid, 5) && \
203 !(IS_VALLEYVIEW(devid) || \
204 IS_CHERRYVIEW(devid) || \
205 IS_BROXTON(devid)))
206
207 #endif /* _INTEL_CHIPSET_H */
208