/art/compiler/utils/arm/ |
D | assembler_arm_vixl.cc | 154 ___ Add(temp, base, add_to_base); in AdjustLoadStoreOffset() local 158 ___ Add(temp, temp, base); in AdjustLoadStoreOffset() local 323 ___ Add(dest, dest, (dest.Is(base)) ? temp : base); in LoadFromOffset() local 393 ___ Add(base, sp, Operand::From(stack_offset)); in StoreRegisterList() local 413 ___ Add(base, sp, Operand::From(stack_offset)); in LoadRegisterList() local 441 ___ Add(rd, rn, value); in AddConstant() local
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D | assembler_arm_vixl.h | 134 void Add(vixl32::Register rd, vixl32::Register rn, const vixl32::Operand& operand) { in Add() function
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/art/runtime/gc/collector/ |
D | object_byte_pair.h | 29 void Add(const ObjectBytePair& other) { in Add() function
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/art/runtime/interpreter/ |
D | safe_math_test.cc | 26 TEST(SafeMath, Add) { in TEST() argument
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/art/libartbase/base/metrics/ |
D | metrics.h | 265 void Add(value_t value) { value_.fetch_add(value, std::memory_order::memory_order_relaxed); } in Add() function 305 void Add(value_t value) { in Add() function 349 void Add(int64_t value) { in Add() function 404 void Add(T value) { in Add() function
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/art/runtime/ |
D | signal_set.h | 42 void Add(int signal) { in Add() function
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D | indirect_reference_table-inl.h | 102 inline void IrtEntry::Add(ObjPtr<mirror::Object> obj) { in Add() function
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D | indirect_reference_table.cc | 248 IndirectRef IndirectReferenceTable::Add(IRTSegmentState previous_state, in Add() function in art::IndirectReferenceTable
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D | reference_table.cc | 49 void ReferenceTable::Add(ObjPtr<mirror::Object> obj) { in Add() function in art::ReferenceTable
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/art/libprofile/profile/ |
D | profile_boot_info.cc | 29 void ProfileBootInfo::Add(const DexFile* dex_file, uint32_t method_index) { in Add() function in art::ProfileBootInfo
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/art/compiler/optimizing/ |
D | intrinsics_arm_vixl.cc | 90 __ Add(base, array, element_size * constant + data_offset); in GenSystemArrayCopyBaseAddress() local 92 __ Add(base, array, Operand(RegisterFrom(pos), vixl32::LSL, element_size_shift)); in GenSystemArrayCopyBaseAddress() local 93 __ Add(base, base, data_offset); in GenSystemArrayCopyBaseAddress() local 112 __ Add(end, base, element_size * constant); in GenSystemArrayCopyEndAddress() local 114 __ Add(end, base, Operand(RegisterFrom(copy_length), vixl32::LSL, element_size_shift)); in GenSystemArrayCopyEndAddress() local 320 __ Add(out, out, 32); in GenNumberOfLeadingZeros() local 364 __ Add(out, out, 32); in GenNumberOfTrailingZeros() local 743 __ Add(temp1, temp1, char_size * 2); in GenerateStringCompareToLoop() local 749 __ Add(temp1, temp1, char_size * 2); in GenerateStringCompareToLoop() local 825 __ Add(temp0, temp0, temp0); // Unlike LSL, this ADD is always 16-bit. in GenerateStringCompareToLoop() local [all …]
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D | intrinsics_arm64.cc | 719 __ Add(temp, base, offset.W()); // Offset should not exceed 32 bits. in GenUnsafeGet() local 1216 __ Add(tmp_ptr, base_.X(), Operand(offset_)); in EmitNativeCode() local 1326 __ Add(tmp_ptr, base.X(), Operand(offset)); in GenUnsafeCas() local 1455 __ Add(new_value, old_value_reg, arg.IsX() ? arg.X() : arg.W()); in GenerateGetAndUpdate() local 1591 __ Add(temp1, temp1, char_size * 4); in VisitStringCompareTo() local 1658 __ Add(temp1, temp1, Operand(value_offset)); in VisitStringCompareTo() local 1659 __ Add(temp2, temp2, Operand(value_offset)); in VisitStringCompareTo() local 1876 __ Add(temp1, temp1, Operand(sizeof(uint64_t))); in VisitStringEquals() local 2277 __ Add(dst_ptr, dstObj, Operand(data_offset)); in VisitStringGetCharsNoCheck() local 2278 __ Add(dst_ptr, dst_ptr, Operand(dstBegin, LSL, 1)); in VisitStringGetCharsNoCheck() local [all …]
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D | code_generator_arm_vixl.cc | 208 __ Add(base, sp, Operand::From(stack_offset)); in SaveContiguousSRegisterList() local 256 __ Add(base, sp, Operand::From(stack_offset)); in RestoreContiguousSRegisterList() local 832 __ Add(index_reg, index_reg, offset_); in EmitNativeCode() local 1099 __ Add(out, first, second); in GenerateDataProcInstruction() local 2123 __ Add(temp, temp, 1); in MaybeIncrementHotness() local 2148 __ Add(ip, ip, 1); in MaybeIncrementHotness() local 4080 __ Add(OutputRegister(add), InputRegisterAt(add, 0), InputOperandAt(add, 1)); in VisitAdd() local 4232 __ Add(out_hi, out_hi, temp); in VisitMul() local 4338 __ Add(out, dividend, Operand(add_right_input, vixl32::LSR, 32 - ctz_imm)); in DivRemByPowerOfTwo() local 4392 __ Add(temp1, temp1, dividend); in GenerateDivRemWithAnyConstant() local [all …]
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D | code_generator_arm64.cc | 672 __ Add(index_reg, index_reg, Operand(offset_)); in EmitNativeCode() local 1122 __ Add(counter, counter, 1); in MaybeIncrementHotness() local 1140 __ Add(counter, counter, 1); in MaybeIncrementHotness() local 1630 __ Add(temp_base, src.GetBaseRegister(), OperandFromMemOperand(src)); in LoadAcquire() local 1740 __ Add(temp_base, dst.GetBaseRegister(), op); in StoreRelease() local 2147 __ Add(dst, lhs, rhs); in HandleBinaryOp() local 2348 __ Add(out, left, right_operand); in VisitDataProcWithShifterOp() local 2381 __ Add(OutputRegister(instruction), in VisitIntermediateAddress() local 2411 __ Add(OutputRegister(instruction), index_reg, offset); in VisitIntermediateAddressIndex() local 2414 __ Add(OutputRegister(instruction), offset_reg, Operand(index_reg, LSL, shift)); in VisitIntermediateAddressIndex() local [all …]
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D | code_generator_vector_arm64_neon.cc | 449 __ Add(dst.V16B(), lhs.V16B(), rhs.V16B()); in VisitVecAdd() local 454 __ Add(dst.V8H(), lhs.V8H(), rhs.V8H()); in VisitVecAdd() local 458 __ Add(dst.V4S(), lhs.V4S(), rhs.V4S()); in VisitVecAdd() local 462 __ Add(dst.V2D(), lhs.V2D(), rhs.V2D()); in VisitVecAdd() local 1285 __ Add(acc.V4S(), acc.V4S(), tmp.V4S()); in VisitVecSADAccumulate() local 1306 __ Add(acc.V2D(), acc.V2D(), tmp.V2D()); in VisitVecSADAccumulate() local
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D | code_generator_vector_arm_vixl.cc | 920 __ Add(*scratch, base, Operand(RegisterFrom(index), ShiftType::LSL, shift)); in VecAddress() local 943 __ Add(*scratch, base, offset); in VecAddressUnaligned() local 946 __ Add(*scratch, base, offset); in VecAddressUnaligned() local 947 __ Add(*scratch, *scratch, Operand(RegisterFrom(index), ShiftType::LSL, shift)); in VecAddressUnaligned() local
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D | code_generator_vector_arm64_sve.cc | 449 __ Add(dst.VnB(), p_reg, lhs.VnB(), rhs.VnB()); in VisitVecAdd() local 453 __ Add(dst.VnH(), p_reg, lhs.VnH(), rhs.VnH()); in VisitVecAdd() local 456 __ Add(dst.VnS(), p_reg, lhs.VnS(), rhs.VnS()); in VisitVecAdd() local 459 __ Add(dst.VnD(), p_reg, lhs.VnD(), rhs.VnD()); in VisitVecAdd() local
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D | gvn.cc | 84 void Add(HInstruction* instruction) { in Add() function in art::ValueSet
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/art/libelffile/elf/ |
D | elf_builder.h | 238 Elf_Word Add(const void* data, size_t length) { in Add() function 281 Elf_Word Add(const std::string& name) { in Add() function 359 void Add(Elf_Word name, in Add() function 375 void Add(Elf_Sym sym, const Section* section) { in Add() function
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/art/runtime/base/ |
D | timing_logger.h | 53 void Add(uint64_t time) { time_ += time; } in Add() function
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/art/compiler/utils/arm64/ |
D | jni_macro_assembler_arm64.cc | 90 ___ Add(reg_x(rd), reg_x(rn), value); in AddConstant() local 97 ___ Add(temp, reg_x(rn), value); in AddConstant() local 175 ___ Add(scratch, reg_x(SP), fr_offs.Int32Value()); in StoreStackOffsetToThread() local 689 ___ Add(scratch, reg_x(SP), spilled_reference_offset.Int32Value()); in CreateJObject() local 696 ___ Add(scratch, reg_x(SP), spilled_reference_offset.Int32Value()); in CreateJObject() local
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/art/test/660-clinit/src/ |
D | Main.java | 199 class Add { class
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/art/libartbase/base/ |
D | bit_table.h | 301 void Add(Entry value) { in Add() function
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/art/tools/dexanalyze/ |
D | dexanalyze_bytecode.cc | 525 void NewRegisterInstructions::Add(Instruction::Code opcode, const Instruction& inst) { in Add() function in art::dexanalyze::NewRegisterInstructions
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/art/tools/signal_dumper/ |
D | signal_dumper.cc | 62 void Add(int signal) { in Add() function in art::__anon744022730111::timeout_signal::SignalSet
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