1 //===-- X86InstrInfo.cpp - X86 Instruction Information --------------------===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file contains the X86 implementation of the TargetInstrInfo class.
11 //
12 //===----------------------------------------------------------------------===//
13
14 #include "X86InstrInfo.h"
15 #include "X86.h"
16 #include "X86InstrBuilder.h"
17 #include "X86MachineFunctionInfo.h"
18 #include "X86Subtarget.h"
19 #include "X86TargetMachine.h"
20 #include "llvm/ADT/STLExtras.h"
21 #include "llvm/CodeGen/LivePhysRegs.h"
22 #include "llvm/CodeGen/LiveVariables.h"
23 #include "llvm/CodeGen/MachineConstantPool.h"
24 #include "llvm/CodeGen/MachineDominators.h"
25 #include "llvm/CodeGen/MachineFrameInfo.h"
26 #include "llvm/CodeGen/MachineInstrBuilder.h"
27 #include "llvm/CodeGen/MachineModuleInfo.h"
28 #include "llvm/CodeGen/MachineRegisterInfo.h"
29 #include "llvm/CodeGen/StackMaps.h"
30 #include "llvm/IR/DerivedTypes.h"
31 #include "llvm/IR/Function.h"
32 #include "llvm/IR/LLVMContext.h"
33 #include "llvm/MC/MCAsmInfo.h"
34 #include "llvm/MC/MCExpr.h"
35 #include "llvm/MC/MCInst.h"
36 #include "llvm/Support/CommandLine.h"
37 #include "llvm/Support/Debug.h"
38 #include "llvm/Support/ErrorHandling.h"
39 #include "llvm/Support/raw_ostream.h"
40 #include "llvm/Target/TargetOptions.h"
41
42 using namespace llvm;
43
44 #define DEBUG_TYPE "x86-instr-info"
45
46 #define GET_INSTRINFO_CTOR_DTOR
47 #include "X86GenInstrInfo.inc"
48
49 static cl::opt<bool>
50 NoFusing("disable-spill-fusing",
51 cl::desc("Disable fusing of spill code into instructions"));
52 static cl::opt<bool>
53 PrintFailedFusing("print-failed-fuse-candidates",
54 cl::desc("Print instructions that the allocator wants to"
55 " fuse, but the X86 backend currently can't"),
56 cl::Hidden);
57 static cl::opt<bool>
58 ReMatPICStubLoad("remat-pic-stub-load",
59 cl::desc("Re-materialize load from stub in PIC mode"),
60 cl::init(false), cl::Hidden);
61 static cl::opt<unsigned>
62 PartialRegUpdateClearance("partial-reg-update-clearance",
63 cl::desc("Clearance between two register writes "
64 "for inserting XOR to avoid partial "
65 "register update"),
66 cl::init(64), cl::Hidden);
67 static cl::opt<unsigned>
68 UndefRegClearance("undef-reg-clearance",
69 cl::desc("How many idle instructions we would like before "
70 "certain undef register reads"),
71 cl::init(64), cl::Hidden);
72
73 enum {
74 // Select which memory operand is being unfolded.
75 // (stored in bits 0 - 3)
76 TB_INDEX_0 = 0,
77 TB_INDEX_1 = 1,
78 TB_INDEX_2 = 2,
79 TB_INDEX_3 = 3,
80 TB_INDEX_4 = 4,
81 TB_INDEX_MASK = 0xf,
82
83 // Do not insert the reverse map (MemOp -> RegOp) into the table.
84 // This may be needed because there is a many -> one mapping.
85 TB_NO_REVERSE = 1 << 4,
86
87 // Do not insert the forward map (RegOp -> MemOp) into the table.
88 // This is needed for Native Client, which prohibits branch
89 // instructions from using a memory operand.
90 TB_NO_FORWARD = 1 << 5,
91
92 TB_FOLDED_LOAD = 1 << 6,
93 TB_FOLDED_STORE = 1 << 7,
94
95 // Minimum alignment required for load/store.
96 // Used for RegOp->MemOp conversion.
97 // (stored in bits 8 - 15)
98 TB_ALIGN_SHIFT = 8,
99 TB_ALIGN_NONE = 0 << TB_ALIGN_SHIFT,
100 TB_ALIGN_16 = 16 << TB_ALIGN_SHIFT,
101 TB_ALIGN_32 = 32 << TB_ALIGN_SHIFT,
102 TB_ALIGN_64 = 64 << TB_ALIGN_SHIFT,
103 TB_ALIGN_MASK = 0xff << TB_ALIGN_SHIFT
104 };
105
106 struct X86MemoryFoldTableEntry {
107 uint16_t RegOp;
108 uint16_t MemOp;
109 uint16_t Flags;
110 };
111
112 // Pin the vtable to this file.
anchor()113 void X86InstrInfo::anchor() {}
114
X86InstrInfo(X86Subtarget & STI)115 X86InstrInfo::X86InstrInfo(X86Subtarget &STI)
116 : X86GenInstrInfo((STI.isTarget64BitLP64() ? X86::ADJCALLSTACKDOWN64
117 : X86::ADJCALLSTACKDOWN32),
118 (STI.isTarget64BitLP64() ? X86::ADJCALLSTACKUP64
119 : X86::ADJCALLSTACKUP32),
120 X86::CATCHRET,
121 (STI.is64Bit() ? X86::RETQ : X86::RETL)),
122 Subtarget(STI), RI(STI.getTargetTriple()) {
123
124 static const X86MemoryFoldTableEntry MemoryFoldTable2Addr[] = {
125 { X86::ADC32ri, X86::ADC32mi, 0 },
126 { X86::ADC32ri8, X86::ADC32mi8, 0 },
127 { X86::ADC32rr, X86::ADC32mr, 0 },
128 { X86::ADC64ri32, X86::ADC64mi32, 0 },
129 { X86::ADC64ri8, X86::ADC64mi8, 0 },
130 { X86::ADC64rr, X86::ADC64mr, 0 },
131 { X86::ADD16ri, X86::ADD16mi, 0 },
132 { X86::ADD16ri8, X86::ADD16mi8, 0 },
133 { X86::ADD16ri_DB, X86::ADD16mi, TB_NO_REVERSE },
134 { X86::ADD16ri8_DB, X86::ADD16mi8, TB_NO_REVERSE },
135 { X86::ADD16rr, X86::ADD16mr, 0 },
136 { X86::ADD16rr_DB, X86::ADD16mr, TB_NO_REVERSE },
137 { X86::ADD32ri, X86::ADD32mi, 0 },
138 { X86::ADD32ri8, X86::ADD32mi8, 0 },
139 { X86::ADD32ri_DB, X86::ADD32mi, TB_NO_REVERSE },
140 { X86::ADD32ri8_DB, X86::ADD32mi8, TB_NO_REVERSE },
141 { X86::ADD32rr, X86::ADD32mr, 0 },
142 { X86::ADD32rr_DB, X86::ADD32mr, TB_NO_REVERSE },
143 { X86::ADD64ri32, X86::ADD64mi32, 0 },
144 { X86::ADD64ri8, X86::ADD64mi8, 0 },
145 { X86::ADD64ri32_DB,X86::ADD64mi32, TB_NO_REVERSE },
146 { X86::ADD64ri8_DB, X86::ADD64mi8, TB_NO_REVERSE },
147 { X86::ADD64rr, X86::ADD64mr, 0 },
148 { X86::ADD64rr_DB, X86::ADD64mr, TB_NO_REVERSE },
149 { X86::ADD8ri, X86::ADD8mi, 0 },
150 { X86::ADD8rr, X86::ADD8mr, 0 },
151 { X86::AND16ri, X86::AND16mi, 0 },
152 { X86::AND16ri8, X86::AND16mi8, 0 },
153 { X86::AND16rr, X86::AND16mr, 0 },
154 { X86::AND32ri, X86::AND32mi, 0 },
155 { X86::AND32ri8, X86::AND32mi8, 0 },
156 { X86::AND32rr, X86::AND32mr, 0 },
157 { X86::AND64ri32, X86::AND64mi32, 0 },
158 { X86::AND64ri8, X86::AND64mi8, 0 },
159 { X86::AND64rr, X86::AND64mr, 0 },
160 { X86::AND8ri, X86::AND8mi, 0 },
161 { X86::AND8rr, X86::AND8mr, 0 },
162 { X86::DEC16r, X86::DEC16m, 0 },
163 { X86::DEC32r, X86::DEC32m, 0 },
164 { X86::DEC64r, X86::DEC64m, 0 },
165 { X86::DEC8r, X86::DEC8m, 0 },
166 { X86::INC16r, X86::INC16m, 0 },
167 { X86::INC32r, X86::INC32m, 0 },
168 { X86::INC64r, X86::INC64m, 0 },
169 { X86::INC8r, X86::INC8m, 0 },
170 { X86::NEG16r, X86::NEG16m, 0 },
171 { X86::NEG32r, X86::NEG32m, 0 },
172 { X86::NEG64r, X86::NEG64m, 0 },
173 { X86::NEG8r, X86::NEG8m, 0 },
174 { X86::NOT16r, X86::NOT16m, 0 },
175 { X86::NOT32r, X86::NOT32m, 0 },
176 { X86::NOT64r, X86::NOT64m, 0 },
177 { X86::NOT8r, X86::NOT8m, 0 },
178 { X86::OR16ri, X86::OR16mi, 0 },
179 { X86::OR16ri8, X86::OR16mi8, 0 },
180 { X86::OR16rr, X86::OR16mr, 0 },
181 { X86::OR32ri, X86::OR32mi, 0 },
182 { X86::OR32ri8, X86::OR32mi8, 0 },
183 { X86::OR32rr, X86::OR32mr, 0 },
184 { X86::OR64ri32, X86::OR64mi32, 0 },
185 { X86::OR64ri8, X86::OR64mi8, 0 },
186 { X86::OR64rr, X86::OR64mr, 0 },
187 { X86::OR8ri, X86::OR8mi, 0 },
188 { X86::OR8rr, X86::OR8mr, 0 },
189 { X86::ROL16r1, X86::ROL16m1, 0 },
190 { X86::ROL16rCL, X86::ROL16mCL, 0 },
191 { X86::ROL16ri, X86::ROL16mi, 0 },
192 { X86::ROL32r1, X86::ROL32m1, 0 },
193 { X86::ROL32rCL, X86::ROL32mCL, 0 },
194 { X86::ROL32ri, X86::ROL32mi, 0 },
195 { X86::ROL64r1, X86::ROL64m1, 0 },
196 { X86::ROL64rCL, X86::ROL64mCL, 0 },
197 { X86::ROL64ri, X86::ROL64mi, 0 },
198 { X86::ROL8r1, X86::ROL8m1, 0 },
199 { X86::ROL8rCL, X86::ROL8mCL, 0 },
200 { X86::ROL8ri, X86::ROL8mi, 0 },
201 { X86::ROR16r1, X86::ROR16m1, 0 },
202 { X86::ROR16rCL, X86::ROR16mCL, 0 },
203 { X86::ROR16ri, X86::ROR16mi, 0 },
204 { X86::ROR32r1, X86::ROR32m1, 0 },
205 { X86::ROR32rCL, X86::ROR32mCL, 0 },
206 { X86::ROR32ri, X86::ROR32mi, 0 },
207 { X86::ROR64r1, X86::ROR64m1, 0 },
208 { X86::ROR64rCL, X86::ROR64mCL, 0 },
209 { X86::ROR64ri, X86::ROR64mi, 0 },
210 { X86::ROR8r1, X86::ROR8m1, 0 },
211 { X86::ROR8rCL, X86::ROR8mCL, 0 },
212 { X86::ROR8ri, X86::ROR8mi, 0 },
213 { X86::SAR16r1, X86::SAR16m1, 0 },
214 { X86::SAR16rCL, X86::SAR16mCL, 0 },
215 { X86::SAR16ri, X86::SAR16mi, 0 },
216 { X86::SAR32r1, X86::SAR32m1, 0 },
217 { X86::SAR32rCL, X86::SAR32mCL, 0 },
218 { X86::SAR32ri, X86::SAR32mi, 0 },
219 { X86::SAR64r1, X86::SAR64m1, 0 },
220 { X86::SAR64rCL, X86::SAR64mCL, 0 },
221 { X86::SAR64ri, X86::SAR64mi, 0 },
222 { X86::SAR8r1, X86::SAR8m1, 0 },
223 { X86::SAR8rCL, X86::SAR8mCL, 0 },
224 { X86::SAR8ri, X86::SAR8mi, 0 },
225 { X86::SBB32ri, X86::SBB32mi, 0 },
226 { X86::SBB32ri8, X86::SBB32mi8, 0 },
227 { X86::SBB32rr, X86::SBB32mr, 0 },
228 { X86::SBB64ri32, X86::SBB64mi32, 0 },
229 { X86::SBB64ri8, X86::SBB64mi8, 0 },
230 { X86::SBB64rr, X86::SBB64mr, 0 },
231 { X86::SHL16rCL, X86::SHL16mCL, 0 },
232 { X86::SHL16ri, X86::SHL16mi, 0 },
233 { X86::SHL32rCL, X86::SHL32mCL, 0 },
234 { X86::SHL32ri, X86::SHL32mi, 0 },
235 { X86::SHL64rCL, X86::SHL64mCL, 0 },
236 { X86::SHL64ri, X86::SHL64mi, 0 },
237 { X86::SHL8rCL, X86::SHL8mCL, 0 },
238 { X86::SHL8ri, X86::SHL8mi, 0 },
239 { X86::SHLD16rrCL, X86::SHLD16mrCL, 0 },
240 { X86::SHLD16rri8, X86::SHLD16mri8, 0 },
241 { X86::SHLD32rrCL, X86::SHLD32mrCL, 0 },
242 { X86::SHLD32rri8, X86::SHLD32mri8, 0 },
243 { X86::SHLD64rrCL, X86::SHLD64mrCL, 0 },
244 { X86::SHLD64rri8, X86::SHLD64mri8, 0 },
245 { X86::SHR16r1, X86::SHR16m1, 0 },
246 { X86::SHR16rCL, X86::SHR16mCL, 0 },
247 { X86::SHR16ri, X86::SHR16mi, 0 },
248 { X86::SHR32r1, X86::SHR32m1, 0 },
249 { X86::SHR32rCL, X86::SHR32mCL, 0 },
250 { X86::SHR32ri, X86::SHR32mi, 0 },
251 { X86::SHR64r1, X86::SHR64m1, 0 },
252 { X86::SHR64rCL, X86::SHR64mCL, 0 },
253 { X86::SHR64ri, X86::SHR64mi, 0 },
254 { X86::SHR8r1, X86::SHR8m1, 0 },
255 { X86::SHR8rCL, X86::SHR8mCL, 0 },
256 { X86::SHR8ri, X86::SHR8mi, 0 },
257 { X86::SHRD16rrCL, X86::SHRD16mrCL, 0 },
258 { X86::SHRD16rri8, X86::SHRD16mri8, 0 },
259 { X86::SHRD32rrCL, X86::SHRD32mrCL, 0 },
260 { X86::SHRD32rri8, X86::SHRD32mri8, 0 },
261 { X86::SHRD64rrCL, X86::SHRD64mrCL, 0 },
262 { X86::SHRD64rri8, X86::SHRD64mri8, 0 },
263 { X86::SUB16ri, X86::SUB16mi, 0 },
264 { X86::SUB16ri8, X86::SUB16mi8, 0 },
265 { X86::SUB16rr, X86::SUB16mr, 0 },
266 { X86::SUB32ri, X86::SUB32mi, 0 },
267 { X86::SUB32ri8, X86::SUB32mi8, 0 },
268 { X86::SUB32rr, X86::SUB32mr, 0 },
269 { X86::SUB64ri32, X86::SUB64mi32, 0 },
270 { X86::SUB64ri8, X86::SUB64mi8, 0 },
271 { X86::SUB64rr, X86::SUB64mr, 0 },
272 { X86::SUB8ri, X86::SUB8mi, 0 },
273 { X86::SUB8rr, X86::SUB8mr, 0 },
274 { X86::XOR16ri, X86::XOR16mi, 0 },
275 { X86::XOR16ri8, X86::XOR16mi8, 0 },
276 { X86::XOR16rr, X86::XOR16mr, 0 },
277 { X86::XOR32ri, X86::XOR32mi, 0 },
278 { X86::XOR32ri8, X86::XOR32mi8, 0 },
279 { X86::XOR32rr, X86::XOR32mr, 0 },
280 { X86::XOR64ri32, X86::XOR64mi32, 0 },
281 { X86::XOR64ri8, X86::XOR64mi8, 0 },
282 { X86::XOR64rr, X86::XOR64mr, 0 },
283 { X86::XOR8ri, X86::XOR8mi, 0 },
284 { X86::XOR8rr, X86::XOR8mr, 0 }
285 };
286
287 for (X86MemoryFoldTableEntry Entry : MemoryFoldTable2Addr) {
288 AddTableEntry(RegOp2MemOpTable2Addr, MemOp2RegOpTable,
289 Entry.RegOp, Entry.MemOp,
290 // Index 0, folded load and store, no alignment requirement.
291 Entry.Flags | TB_INDEX_0 | TB_FOLDED_LOAD | TB_FOLDED_STORE);
292 }
293
294 static const X86MemoryFoldTableEntry MemoryFoldTable0[] = {
295 { X86::BT16ri8, X86::BT16mi8, TB_FOLDED_LOAD },
296 { X86::BT32ri8, X86::BT32mi8, TB_FOLDED_LOAD },
297 { X86::BT64ri8, X86::BT64mi8, TB_FOLDED_LOAD },
298 { X86::CALL32r, X86::CALL32m, TB_FOLDED_LOAD },
299 { X86::CALL64r, X86::CALL64m, TB_FOLDED_LOAD },
300 { X86::CMP16ri, X86::CMP16mi, TB_FOLDED_LOAD },
301 { X86::CMP16ri8, X86::CMP16mi8, TB_FOLDED_LOAD },
302 { X86::CMP16rr, X86::CMP16mr, TB_FOLDED_LOAD },
303 { X86::CMP32ri, X86::CMP32mi, TB_FOLDED_LOAD },
304 { X86::CMP32ri8, X86::CMP32mi8, TB_FOLDED_LOAD },
305 { X86::CMP32rr, X86::CMP32mr, TB_FOLDED_LOAD },
306 { X86::CMP64ri32, X86::CMP64mi32, TB_FOLDED_LOAD },
307 { X86::CMP64ri8, X86::CMP64mi8, TB_FOLDED_LOAD },
308 { X86::CMP64rr, X86::CMP64mr, TB_FOLDED_LOAD },
309 { X86::CMP8ri, X86::CMP8mi, TB_FOLDED_LOAD },
310 { X86::CMP8rr, X86::CMP8mr, TB_FOLDED_LOAD },
311 { X86::DIV16r, X86::DIV16m, TB_FOLDED_LOAD },
312 { X86::DIV32r, X86::DIV32m, TB_FOLDED_LOAD },
313 { X86::DIV64r, X86::DIV64m, TB_FOLDED_LOAD },
314 { X86::DIV8r, X86::DIV8m, TB_FOLDED_LOAD },
315 { X86::EXTRACTPSrr, X86::EXTRACTPSmr, TB_FOLDED_STORE },
316 { X86::IDIV16r, X86::IDIV16m, TB_FOLDED_LOAD },
317 { X86::IDIV32r, X86::IDIV32m, TB_FOLDED_LOAD },
318 { X86::IDIV64r, X86::IDIV64m, TB_FOLDED_LOAD },
319 { X86::IDIV8r, X86::IDIV8m, TB_FOLDED_LOAD },
320 { X86::IMUL16r, X86::IMUL16m, TB_FOLDED_LOAD },
321 { X86::IMUL32r, X86::IMUL32m, TB_FOLDED_LOAD },
322 { X86::IMUL64r, X86::IMUL64m, TB_FOLDED_LOAD },
323 { X86::IMUL8r, X86::IMUL8m, TB_FOLDED_LOAD },
324 { X86::JMP32r, X86::JMP32m, TB_FOLDED_LOAD },
325 { X86::JMP64r, X86::JMP64m, TB_FOLDED_LOAD },
326 { X86::MOV16ri, X86::MOV16mi, TB_FOLDED_STORE },
327 { X86::MOV16rr, X86::MOV16mr, TB_FOLDED_STORE },
328 { X86::MOV32ri, X86::MOV32mi, TB_FOLDED_STORE },
329 { X86::MOV32rr, X86::MOV32mr, TB_FOLDED_STORE },
330 { X86::MOV64ri32, X86::MOV64mi32, TB_FOLDED_STORE },
331 { X86::MOV64rr, X86::MOV64mr, TB_FOLDED_STORE },
332 { X86::MOV8ri, X86::MOV8mi, TB_FOLDED_STORE },
333 { X86::MOV8rr, X86::MOV8mr, TB_FOLDED_STORE },
334 { X86::MOV8rr_NOREX, X86::MOV8mr_NOREX, TB_FOLDED_STORE },
335 { X86::MOVAPDrr, X86::MOVAPDmr, TB_FOLDED_STORE | TB_ALIGN_16 },
336 { X86::MOVAPSrr, X86::MOVAPSmr, TB_FOLDED_STORE | TB_ALIGN_16 },
337 { X86::MOVDQArr, X86::MOVDQAmr, TB_FOLDED_STORE | TB_ALIGN_16 },
338 { X86::MOVPDI2DIrr, X86::MOVPDI2DImr, TB_FOLDED_STORE },
339 { X86::MOVPQIto64rr,X86::MOVPQI2QImr, TB_FOLDED_STORE },
340 { X86::MOVSDto64rr, X86::MOVSDto64mr, TB_FOLDED_STORE },
341 { X86::MOVSS2DIrr, X86::MOVSS2DImr, TB_FOLDED_STORE },
342 { X86::MOVUPDrr, X86::MOVUPDmr, TB_FOLDED_STORE },
343 { X86::MOVUPSrr, X86::MOVUPSmr, TB_FOLDED_STORE },
344 { X86::MUL16r, X86::MUL16m, TB_FOLDED_LOAD },
345 { X86::MUL32r, X86::MUL32m, TB_FOLDED_LOAD },
346 { X86::MUL64r, X86::MUL64m, TB_FOLDED_LOAD },
347 { X86::MUL8r, X86::MUL8m, TB_FOLDED_LOAD },
348 { X86::PEXTRDrr, X86::PEXTRDmr, TB_FOLDED_STORE },
349 { X86::PEXTRQrr, X86::PEXTRQmr, TB_FOLDED_STORE },
350 { X86::PUSH16r, X86::PUSH16rmm, TB_FOLDED_LOAD },
351 { X86::PUSH32r, X86::PUSH32rmm, TB_FOLDED_LOAD },
352 { X86::PUSH64r, X86::PUSH64rmm, TB_FOLDED_LOAD },
353 { X86::SETAEr, X86::SETAEm, TB_FOLDED_STORE },
354 { X86::SETAr, X86::SETAm, TB_FOLDED_STORE },
355 { X86::SETBEr, X86::SETBEm, TB_FOLDED_STORE },
356 { X86::SETBr, X86::SETBm, TB_FOLDED_STORE },
357 { X86::SETEr, X86::SETEm, TB_FOLDED_STORE },
358 { X86::SETGEr, X86::SETGEm, TB_FOLDED_STORE },
359 { X86::SETGr, X86::SETGm, TB_FOLDED_STORE },
360 { X86::SETLEr, X86::SETLEm, TB_FOLDED_STORE },
361 { X86::SETLr, X86::SETLm, TB_FOLDED_STORE },
362 { X86::SETNEr, X86::SETNEm, TB_FOLDED_STORE },
363 { X86::SETNOr, X86::SETNOm, TB_FOLDED_STORE },
364 { X86::SETNPr, X86::SETNPm, TB_FOLDED_STORE },
365 { X86::SETNSr, X86::SETNSm, TB_FOLDED_STORE },
366 { X86::SETOr, X86::SETOm, TB_FOLDED_STORE },
367 { X86::SETPr, X86::SETPm, TB_FOLDED_STORE },
368 { X86::SETSr, X86::SETSm, TB_FOLDED_STORE },
369 { X86::TAILJMPr, X86::TAILJMPm, TB_FOLDED_LOAD },
370 { X86::TAILJMPr64, X86::TAILJMPm64, TB_FOLDED_LOAD },
371 { X86::TAILJMPr64_REX, X86::TAILJMPm64_REX, TB_FOLDED_LOAD },
372 { X86::TEST16ri, X86::TEST16mi, TB_FOLDED_LOAD },
373 { X86::TEST32ri, X86::TEST32mi, TB_FOLDED_LOAD },
374 { X86::TEST64ri32, X86::TEST64mi32, TB_FOLDED_LOAD },
375 { X86::TEST8ri, X86::TEST8mi, TB_FOLDED_LOAD },
376
377 // AVX 128-bit versions of foldable instructions
378 { X86::VEXTRACTPSrr,X86::VEXTRACTPSmr, TB_FOLDED_STORE },
379 { X86::VEXTRACTF128rr, X86::VEXTRACTF128mr, TB_FOLDED_STORE | TB_ALIGN_16 },
380 { X86::VMOVAPDrr, X86::VMOVAPDmr, TB_FOLDED_STORE | TB_ALIGN_16 },
381 { X86::VMOVAPSrr, X86::VMOVAPSmr, TB_FOLDED_STORE | TB_ALIGN_16 },
382 { X86::VMOVDQArr, X86::VMOVDQAmr, TB_FOLDED_STORE | TB_ALIGN_16 },
383 { X86::VMOVPDI2DIrr,X86::VMOVPDI2DImr, TB_FOLDED_STORE },
384 { X86::VMOVPQIto64rr, X86::VMOVPQI2QImr,TB_FOLDED_STORE },
385 { X86::VMOVSDto64rr,X86::VMOVSDto64mr, TB_FOLDED_STORE },
386 { X86::VMOVSS2DIrr, X86::VMOVSS2DImr, TB_FOLDED_STORE },
387 { X86::VMOVUPDrr, X86::VMOVUPDmr, TB_FOLDED_STORE },
388 { X86::VMOVUPSrr, X86::VMOVUPSmr, TB_FOLDED_STORE },
389 { X86::VPEXTRDrr, X86::VPEXTRDmr, TB_FOLDED_STORE },
390 { X86::VPEXTRQrr, X86::VPEXTRQmr, TB_FOLDED_STORE },
391
392 // AVX 256-bit foldable instructions
393 { X86::VEXTRACTI128rr, X86::VEXTRACTI128mr, TB_FOLDED_STORE | TB_ALIGN_16 },
394 { X86::VMOVAPDYrr, X86::VMOVAPDYmr, TB_FOLDED_STORE | TB_ALIGN_32 },
395 { X86::VMOVAPSYrr, X86::VMOVAPSYmr, TB_FOLDED_STORE | TB_ALIGN_32 },
396 { X86::VMOVDQAYrr, X86::VMOVDQAYmr, TB_FOLDED_STORE | TB_ALIGN_32 },
397 { X86::VMOVUPDYrr, X86::VMOVUPDYmr, TB_FOLDED_STORE },
398 { X86::VMOVUPSYrr, X86::VMOVUPSYmr, TB_FOLDED_STORE },
399
400 // AVX-512 foldable instructions
401 { X86::VMOVPDI2DIZrr, X86::VMOVPDI2DIZmr, TB_FOLDED_STORE },
402 { X86::VMOVAPDZrr, X86::VMOVAPDZmr, TB_FOLDED_STORE | TB_ALIGN_64 },
403 { X86::VMOVAPSZrr, X86::VMOVAPSZmr, TB_FOLDED_STORE | TB_ALIGN_64 },
404 { X86::VMOVDQA32Zrr, X86::VMOVDQA32Zmr, TB_FOLDED_STORE | TB_ALIGN_64 },
405 { X86::VMOVDQA64Zrr, X86::VMOVDQA64Zmr, TB_FOLDED_STORE | TB_ALIGN_64 },
406 { X86::VMOVUPDZrr, X86::VMOVUPDZmr, TB_FOLDED_STORE },
407 { X86::VMOVUPSZrr, X86::VMOVUPSZmr, TB_FOLDED_STORE },
408 { X86::VMOVDQU8Zrr, X86::VMOVDQU8Zmr, TB_FOLDED_STORE },
409 { X86::VMOVDQU16Zrr, X86::VMOVDQU16Zmr, TB_FOLDED_STORE },
410 { X86::VMOVDQU32Zrr, X86::VMOVDQU32Zmr, TB_FOLDED_STORE },
411 { X86::VMOVDQU64Zrr, X86::VMOVDQU64Zmr, TB_FOLDED_STORE },
412
413 // AVX-512 foldable instructions (256-bit versions)
414 { X86::VMOVAPDZ256rr, X86::VMOVAPDZ256mr, TB_FOLDED_STORE | TB_ALIGN_32 },
415 { X86::VMOVAPSZ256rr, X86::VMOVAPSZ256mr, TB_FOLDED_STORE | TB_ALIGN_32 },
416 { X86::VMOVDQA32Z256rr, X86::VMOVDQA32Z256mr, TB_FOLDED_STORE | TB_ALIGN_32 },
417 { X86::VMOVDQA64Z256rr, X86::VMOVDQA64Z256mr, TB_FOLDED_STORE | TB_ALIGN_32 },
418 { X86::VMOVUPDZ256rr, X86::VMOVUPDZ256mr, TB_FOLDED_STORE },
419 { X86::VMOVUPSZ256rr, X86::VMOVUPSZ256mr, TB_FOLDED_STORE },
420 { X86::VMOVDQU8Z256rr, X86::VMOVDQU8Z256mr, TB_FOLDED_STORE },
421 { X86::VMOVDQU16Z256rr, X86::VMOVDQU16Z256mr, TB_FOLDED_STORE },
422 { X86::VMOVDQU32Z256rr, X86::VMOVDQU32Z256mr, TB_FOLDED_STORE },
423 { X86::VMOVDQU64Z256rr, X86::VMOVDQU64Z256mr, TB_FOLDED_STORE },
424
425 // AVX-512 foldable instructions (128-bit versions)
426 { X86::VMOVAPDZ128rr, X86::VMOVAPDZ128mr, TB_FOLDED_STORE | TB_ALIGN_16 },
427 { X86::VMOVAPSZ128rr, X86::VMOVAPSZ128mr, TB_FOLDED_STORE | TB_ALIGN_16 },
428 { X86::VMOVDQA32Z128rr, X86::VMOVDQA32Z128mr, TB_FOLDED_STORE | TB_ALIGN_16 },
429 { X86::VMOVDQA64Z128rr, X86::VMOVDQA64Z128mr, TB_FOLDED_STORE | TB_ALIGN_16 },
430 { X86::VMOVUPDZ128rr, X86::VMOVUPDZ128mr, TB_FOLDED_STORE },
431 { X86::VMOVUPSZ128rr, X86::VMOVUPSZ128mr, TB_FOLDED_STORE },
432 { X86::VMOVDQU8Z128rr, X86::VMOVDQU8Z128mr, TB_FOLDED_STORE },
433 { X86::VMOVDQU16Z128rr, X86::VMOVDQU16Z128mr, TB_FOLDED_STORE },
434 { X86::VMOVDQU32Z128rr, X86::VMOVDQU32Z128mr, TB_FOLDED_STORE },
435 { X86::VMOVDQU64Z128rr, X86::VMOVDQU64Z128mr, TB_FOLDED_STORE },
436
437 // F16C foldable instructions
438 { X86::VCVTPS2PHrr, X86::VCVTPS2PHmr, TB_FOLDED_STORE },
439 { X86::VCVTPS2PHYrr, X86::VCVTPS2PHYmr, TB_FOLDED_STORE }
440 };
441
442 for (X86MemoryFoldTableEntry Entry : MemoryFoldTable0) {
443 AddTableEntry(RegOp2MemOpTable0, MemOp2RegOpTable,
444 Entry.RegOp, Entry.MemOp, TB_INDEX_0 | Entry.Flags);
445 }
446
447 static const X86MemoryFoldTableEntry MemoryFoldTable1[] = {
448 { X86::BSF16rr, X86::BSF16rm, 0 },
449 { X86::BSF32rr, X86::BSF32rm, 0 },
450 { X86::BSF64rr, X86::BSF64rm, 0 },
451 { X86::BSR16rr, X86::BSR16rm, 0 },
452 { X86::BSR32rr, X86::BSR32rm, 0 },
453 { X86::BSR64rr, X86::BSR64rm, 0 },
454 { X86::CMP16rr, X86::CMP16rm, 0 },
455 { X86::CMP32rr, X86::CMP32rm, 0 },
456 { X86::CMP64rr, X86::CMP64rm, 0 },
457 { X86::CMP8rr, X86::CMP8rm, 0 },
458 { X86::CVTSD2SSrr, X86::CVTSD2SSrm, 0 },
459 { X86::CVTSI2SD64rr, X86::CVTSI2SD64rm, 0 },
460 { X86::CVTSI2SDrr, X86::CVTSI2SDrm, 0 },
461 { X86::CVTSI2SS64rr, X86::CVTSI2SS64rm, 0 },
462 { X86::CVTSI2SSrr, X86::CVTSI2SSrm, 0 },
463 { X86::CVTSS2SDrr, X86::CVTSS2SDrm, 0 },
464 { X86::CVTTSD2SI64rr, X86::CVTTSD2SI64rm, 0 },
465 { X86::CVTTSD2SIrr, X86::CVTTSD2SIrm, 0 },
466 { X86::CVTTSS2SI64rr, X86::CVTTSS2SI64rm, 0 },
467 { X86::CVTTSS2SIrr, X86::CVTTSS2SIrm, 0 },
468 { X86::IMUL16rri, X86::IMUL16rmi, 0 },
469 { X86::IMUL16rri8, X86::IMUL16rmi8, 0 },
470 { X86::IMUL32rri, X86::IMUL32rmi, 0 },
471 { X86::IMUL32rri8, X86::IMUL32rmi8, 0 },
472 { X86::IMUL64rri32, X86::IMUL64rmi32, 0 },
473 { X86::IMUL64rri8, X86::IMUL64rmi8, 0 },
474 { X86::Int_COMISDrr, X86::Int_COMISDrm, 0 },
475 { X86::Int_COMISSrr, X86::Int_COMISSrm, 0 },
476 { X86::CVTSD2SI64rr, X86::CVTSD2SI64rm, 0 },
477 { X86::CVTSD2SIrr, X86::CVTSD2SIrm, 0 },
478 { X86::CVTSS2SI64rr, X86::CVTSS2SI64rm, 0 },
479 { X86::CVTSS2SIrr, X86::CVTSS2SIrm, 0 },
480 { X86::CVTDQ2PDrr, X86::CVTDQ2PDrm, TB_ALIGN_16 },
481 { X86::CVTDQ2PSrr, X86::CVTDQ2PSrm, TB_ALIGN_16 },
482 { X86::CVTPD2DQrr, X86::CVTPD2DQrm, TB_ALIGN_16 },
483 { X86::CVTPD2PSrr, X86::CVTPD2PSrm, TB_ALIGN_16 },
484 { X86::CVTPS2DQrr, X86::CVTPS2DQrm, TB_ALIGN_16 },
485 { X86::CVTPS2PDrr, X86::CVTPS2PDrm, TB_ALIGN_16 },
486 { X86::CVTTPD2DQrr, X86::CVTTPD2DQrm, TB_ALIGN_16 },
487 { X86::CVTTPS2DQrr, X86::CVTTPS2DQrm, TB_ALIGN_16 },
488 { X86::Int_CVTTSD2SI64rr,X86::Int_CVTTSD2SI64rm, 0 },
489 { X86::Int_CVTTSD2SIrr, X86::Int_CVTTSD2SIrm, 0 },
490 { X86::Int_CVTTSS2SI64rr,X86::Int_CVTTSS2SI64rm, 0 },
491 { X86::Int_CVTTSS2SIrr, X86::Int_CVTTSS2SIrm, 0 },
492 { X86::Int_UCOMISDrr, X86::Int_UCOMISDrm, 0 },
493 { X86::Int_UCOMISSrr, X86::Int_UCOMISSrm, 0 },
494 { X86::MOV16rr, X86::MOV16rm, 0 },
495 { X86::MOV32rr, X86::MOV32rm, 0 },
496 { X86::MOV64rr, X86::MOV64rm, 0 },
497 { X86::MOV64toPQIrr, X86::MOVQI2PQIrm, 0 },
498 { X86::MOV64toSDrr, X86::MOV64toSDrm, 0 },
499 { X86::MOV8rr, X86::MOV8rm, 0 },
500 { X86::MOVAPDrr, X86::MOVAPDrm, TB_ALIGN_16 },
501 { X86::MOVAPSrr, X86::MOVAPSrm, TB_ALIGN_16 },
502 { X86::MOVDDUPrr, X86::MOVDDUPrm, 0 },
503 { X86::MOVDI2PDIrr, X86::MOVDI2PDIrm, 0 },
504 { X86::MOVDI2SSrr, X86::MOVDI2SSrm, 0 },
505 { X86::MOVDQArr, X86::MOVDQArm, TB_ALIGN_16 },
506 { X86::MOVSHDUPrr, X86::MOVSHDUPrm, TB_ALIGN_16 },
507 { X86::MOVSLDUPrr, X86::MOVSLDUPrm, TB_ALIGN_16 },
508 { X86::MOVSX16rr8, X86::MOVSX16rm8, 0 },
509 { X86::MOVSX32rr16, X86::MOVSX32rm16, 0 },
510 { X86::MOVSX32rr8, X86::MOVSX32rm8, 0 },
511 { X86::MOVSX64rr16, X86::MOVSX64rm16, 0 },
512 { X86::MOVSX64rr32, X86::MOVSX64rm32, 0 },
513 { X86::MOVSX64rr8, X86::MOVSX64rm8, 0 },
514 { X86::MOVUPDrr, X86::MOVUPDrm, TB_ALIGN_16 },
515 { X86::MOVUPSrr, X86::MOVUPSrm, 0 },
516 { X86::MOVZPQILo2PQIrr, X86::MOVZPQILo2PQIrm, TB_ALIGN_16 },
517 { X86::MOVZX16rr8, X86::MOVZX16rm8, 0 },
518 { X86::MOVZX32rr16, X86::MOVZX32rm16, 0 },
519 { X86::MOVZX32_NOREXrr8, X86::MOVZX32_NOREXrm8, 0 },
520 { X86::MOVZX32rr8, X86::MOVZX32rm8, 0 },
521 { X86::PABSBrr128, X86::PABSBrm128, TB_ALIGN_16 },
522 { X86::PABSDrr128, X86::PABSDrm128, TB_ALIGN_16 },
523 { X86::PABSWrr128, X86::PABSWrm128, TB_ALIGN_16 },
524 { X86::PCMPESTRIrr, X86::PCMPESTRIrm, TB_ALIGN_16 },
525 { X86::PCMPESTRM128rr, X86::PCMPESTRM128rm, TB_ALIGN_16 },
526 { X86::PCMPISTRIrr, X86::PCMPISTRIrm, TB_ALIGN_16 },
527 { X86::PCMPISTRM128rr, X86::PCMPISTRM128rm, TB_ALIGN_16 },
528 { X86::PHMINPOSUWrr128, X86::PHMINPOSUWrm128, TB_ALIGN_16 },
529 { X86::PMOVSXBDrr, X86::PMOVSXBDrm, TB_ALIGN_16 },
530 { X86::PMOVSXBQrr, X86::PMOVSXBQrm, TB_ALIGN_16 },
531 { X86::PMOVSXBWrr, X86::PMOVSXBWrm, TB_ALIGN_16 },
532 { X86::PMOVSXDQrr, X86::PMOVSXDQrm, TB_ALIGN_16 },
533 { X86::PMOVSXWDrr, X86::PMOVSXWDrm, TB_ALIGN_16 },
534 { X86::PMOVSXWQrr, X86::PMOVSXWQrm, TB_ALIGN_16 },
535 { X86::PMOVZXBDrr, X86::PMOVZXBDrm, TB_ALIGN_16 },
536 { X86::PMOVZXBQrr, X86::PMOVZXBQrm, TB_ALIGN_16 },
537 { X86::PMOVZXBWrr, X86::PMOVZXBWrm, TB_ALIGN_16 },
538 { X86::PMOVZXDQrr, X86::PMOVZXDQrm, TB_ALIGN_16 },
539 { X86::PMOVZXWDrr, X86::PMOVZXWDrm, TB_ALIGN_16 },
540 { X86::PMOVZXWQrr, X86::PMOVZXWQrm, TB_ALIGN_16 },
541 { X86::PSHUFDri, X86::PSHUFDmi, TB_ALIGN_16 },
542 { X86::PSHUFHWri, X86::PSHUFHWmi, TB_ALIGN_16 },
543 { X86::PSHUFLWri, X86::PSHUFLWmi, TB_ALIGN_16 },
544 { X86::PTESTrr, X86::PTESTrm, TB_ALIGN_16 },
545 { X86::RCPPSr, X86::RCPPSm, TB_ALIGN_16 },
546 { X86::RCPSSr, X86::RCPSSm, 0 },
547 { X86::RCPSSr_Int, X86::RCPSSm_Int, 0 },
548 { X86::ROUNDPDr, X86::ROUNDPDm, TB_ALIGN_16 },
549 { X86::ROUNDPSr, X86::ROUNDPSm, TB_ALIGN_16 },
550 { X86::RSQRTPSr, X86::RSQRTPSm, TB_ALIGN_16 },
551 { X86::RSQRTSSr, X86::RSQRTSSm, 0 },
552 { X86::RSQRTSSr_Int, X86::RSQRTSSm_Int, 0 },
553 { X86::SQRTPDr, X86::SQRTPDm, TB_ALIGN_16 },
554 { X86::SQRTPSr, X86::SQRTPSm, TB_ALIGN_16 },
555 { X86::SQRTSDr, X86::SQRTSDm, 0 },
556 { X86::SQRTSDr_Int, X86::SQRTSDm_Int, 0 },
557 { X86::SQRTSSr, X86::SQRTSSm, 0 },
558 { X86::SQRTSSr_Int, X86::SQRTSSm_Int, 0 },
559 { X86::TEST16rr, X86::TEST16rm, 0 },
560 { X86::TEST32rr, X86::TEST32rm, 0 },
561 { X86::TEST64rr, X86::TEST64rm, 0 },
562 { X86::TEST8rr, X86::TEST8rm, 0 },
563 // FIXME: TEST*rr EAX,EAX ---> CMP [mem], 0
564 { X86::UCOMISDrr, X86::UCOMISDrm, 0 },
565 { X86::UCOMISSrr, X86::UCOMISSrm, 0 },
566
567 // MMX version of foldable instructions
568 { X86::MMX_CVTPD2PIirr, X86::MMX_CVTPD2PIirm, 0 },
569 { X86::MMX_CVTPI2PDirr, X86::MMX_CVTPI2PDirm, 0 },
570 { X86::MMX_CVTPS2PIirr, X86::MMX_CVTPS2PIirm, 0 },
571 { X86::MMX_CVTTPD2PIirr, X86::MMX_CVTTPD2PIirm, 0 },
572 { X86::MMX_CVTTPS2PIirr, X86::MMX_CVTTPS2PIirm, 0 },
573 { X86::MMX_MOVD64to64rr, X86::MMX_MOVQ64rm, 0 },
574 { X86::MMX_PABSBrr64, X86::MMX_PABSBrm64, 0 },
575 { X86::MMX_PABSDrr64, X86::MMX_PABSDrm64, 0 },
576 { X86::MMX_PABSWrr64, X86::MMX_PABSWrm64, 0 },
577 { X86::MMX_PSHUFWri, X86::MMX_PSHUFWmi, 0 },
578
579 // 3DNow! version of foldable instructions
580 { X86::PF2IDrr, X86::PF2IDrm, 0 },
581 { X86::PF2IWrr, X86::PF2IWrm, 0 },
582 { X86::PFRCPrr, X86::PFRCPrm, 0 },
583 { X86::PFRSQRTrr, X86::PFRSQRTrm, 0 },
584 { X86::PI2FDrr, X86::PI2FDrm, 0 },
585 { X86::PI2FWrr, X86::PI2FWrm, 0 },
586 { X86::PSWAPDrr, X86::PSWAPDrm, 0 },
587
588 // AVX 128-bit versions of foldable instructions
589 { X86::Int_VCOMISDrr, X86::Int_VCOMISDrm, 0 },
590 { X86::Int_VCOMISSrr, X86::Int_VCOMISSrm, 0 },
591 { X86::Int_VUCOMISDrr, X86::Int_VUCOMISDrm, 0 },
592 { X86::Int_VUCOMISSrr, X86::Int_VUCOMISSrm, 0 },
593 { X86::VCVTTSD2SI64rr, X86::VCVTTSD2SI64rm, 0 },
594 { X86::Int_VCVTTSD2SI64rr,X86::Int_VCVTTSD2SI64rm,0 },
595 { X86::VCVTTSD2SIrr, X86::VCVTTSD2SIrm, 0 },
596 { X86::Int_VCVTTSD2SIrr,X86::Int_VCVTTSD2SIrm, 0 },
597 { X86::VCVTTSS2SI64rr, X86::VCVTTSS2SI64rm, 0 },
598 { X86::Int_VCVTTSS2SI64rr,X86::Int_VCVTTSS2SI64rm,0 },
599 { X86::VCVTTSS2SIrr, X86::VCVTTSS2SIrm, 0 },
600 { X86::Int_VCVTTSS2SIrr,X86::Int_VCVTTSS2SIrm, 0 },
601 { X86::VCVTSD2SI64rr, X86::VCVTSD2SI64rm, 0 },
602 { X86::VCVTSD2SIrr, X86::VCVTSD2SIrm, 0 },
603 { X86::VCVTSS2SI64rr, X86::VCVTSS2SI64rm, 0 },
604 { X86::VCVTSS2SIrr, X86::VCVTSS2SIrm, 0 },
605 { X86::VCVTDQ2PDrr, X86::VCVTDQ2PDrm, 0 },
606 { X86::VCVTDQ2PSrr, X86::VCVTDQ2PSrm, 0 },
607 { X86::VCVTPD2DQrr, X86::VCVTPD2DQXrm, 0 },
608 { X86::VCVTPD2PSrr, X86::VCVTPD2PSXrm, 0 },
609 { X86::VCVTPS2DQrr, X86::VCVTPS2DQrm, 0 },
610 { X86::VCVTPS2PDrr, X86::VCVTPS2PDrm, 0 },
611 { X86::VCVTTPD2DQrr, X86::VCVTTPD2DQXrm, 0 },
612 { X86::VCVTTPS2DQrr, X86::VCVTTPS2DQrm, 0 },
613 { X86::VMOV64toPQIrr, X86::VMOVQI2PQIrm, 0 },
614 { X86::VMOV64toSDrr, X86::VMOV64toSDrm, 0 },
615 { X86::VMOVAPDrr, X86::VMOVAPDrm, TB_ALIGN_16 },
616 { X86::VMOVAPSrr, X86::VMOVAPSrm, TB_ALIGN_16 },
617 { X86::VMOVDDUPrr, X86::VMOVDDUPrm, 0 },
618 { X86::VMOVDI2PDIrr, X86::VMOVDI2PDIrm, 0 },
619 { X86::VMOVDI2SSrr, X86::VMOVDI2SSrm, 0 },
620 { X86::VMOVDQArr, X86::VMOVDQArm, TB_ALIGN_16 },
621 { X86::VMOVSLDUPrr, X86::VMOVSLDUPrm, 0 },
622 { X86::VMOVSHDUPrr, X86::VMOVSHDUPrm, 0 },
623 { X86::VMOVUPDrr, X86::VMOVUPDrm, 0 },
624 { X86::VMOVUPSrr, X86::VMOVUPSrm, 0 },
625 { X86::VMOVZPQILo2PQIrr,X86::VMOVZPQILo2PQIrm, TB_ALIGN_16 },
626 { X86::VPABSBrr128, X86::VPABSBrm128, 0 },
627 { X86::VPABSDrr128, X86::VPABSDrm128, 0 },
628 { X86::VPABSWrr128, X86::VPABSWrm128, 0 },
629 { X86::VPCMPESTRIrr, X86::VPCMPESTRIrm, 0 },
630 { X86::VPCMPESTRM128rr, X86::VPCMPESTRM128rm, 0 },
631 { X86::VPCMPISTRIrr, X86::VPCMPISTRIrm, 0 },
632 { X86::VPCMPISTRM128rr, X86::VPCMPISTRM128rm, 0 },
633 { X86::VPHMINPOSUWrr128, X86::VPHMINPOSUWrm128, 0 },
634 { X86::VPERMILPDri, X86::VPERMILPDmi, 0 },
635 { X86::VPERMILPSri, X86::VPERMILPSmi, 0 },
636 { X86::VPMOVSXBDrr, X86::VPMOVSXBDrm, 0 },
637 { X86::VPMOVSXBQrr, X86::VPMOVSXBQrm, 0 },
638 { X86::VPMOVSXBWrr, X86::VPMOVSXBWrm, 0 },
639 { X86::VPMOVSXDQrr, X86::VPMOVSXDQrm, 0 },
640 { X86::VPMOVSXWDrr, X86::VPMOVSXWDrm, 0 },
641 { X86::VPMOVSXWQrr, X86::VPMOVSXWQrm, 0 },
642 { X86::VPMOVZXBDrr, X86::VPMOVZXBDrm, 0 },
643 { X86::VPMOVZXBQrr, X86::VPMOVZXBQrm, 0 },
644 { X86::VPMOVZXBWrr, X86::VPMOVZXBWrm, 0 },
645 { X86::VPMOVZXDQrr, X86::VPMOVZXDQrm, 0 },
646 { X86::VPMOVZXWDrr, X86::VPMOVZXWDrm, 0 },
647 { X86::VPMOVZXWQrr, X86::VPMOVZXWQrm, 0 },
648 { X86::VPSHUFDri, X86::VPSHUFDmi, 0 },
649 { X86::VPSHUFHWri, X86::VPSHUFHWmi, 0 },
650 { X86::VPSHUFLWri, X86::VPSHUFLWmi, 0 },
651 { X86::VPTESTrr, X86::VPTESTrm, 0 },
652 { X86::VRCPPSr, X86::VRCPPSm, 0 },
653 { X86::VROUNDPDr, X86::VROUNDPDm, 0 },
654 { X86::VROUNDPSr, X86::VROUNDPSm, 0 },
655 { X86::VRSQRTPSr, X86::VRSQRTPSm, 0 },
656 { X86::VSQRTPDr, X86::VSQRTPDm, 0 },
657 { X86::VSQRTPSr, X86::VSQRTPSm, 0 },
658 { X86::VTESTPDrr, X86::VTESTPDrm, 0 },
659 { X86::VTESTPSrr, X86::VTESTPSrm, 0 },
660 { X86::VUCOMISDrr, X86::VUCOMISDrm, 0 },
661 { X86::VUCOMISSrr, X86::VUCOMISSrm, 0 },
662
663 // AVX 256-bit foldable instructions
664 { X86::VCVTDQ2PDYrr, X86::VCVTDQ2PDYrm, 0 },
665 { X86::VCVTDQ2PSYrr, X86::VCVTDQ2PSYrm, 0 },
666 { X86::VCVTPD2DQYrr, X86::VCVTPD2DQYrm, 0 },
667 { X86::VCVTPD2PSYrr, X86::VCVTPD2PSYrm, 0 },
668 { X86::VCVTPS2DQYrr, X86::VCVTPS2DQYrm, 0 },
669 { X86::VCVTPS2PDYrr, X86::VCVTPS2PDYrm, 0 },
670 { X86::VCVTTPD2DQYrr, X86::VCVTTPD2DQYrm, 0 },
671 { X86::VCVTTPS2DQYrr, X86::VCVTTPS2DQYrm, 0 },
672 { X86::VMOVAPDYrr, X86::VMOVAPDYrm, TB_ALIGN_32 },
673 { X86::VMOVAPSYrr, X86::VMOVAPSYrm, TB_ALIGN_32 },
674 { X86::VMOVDDUPYrr, X86::VMOVDDUPYrm, 0 },
675 { X86::VMOVDQAYrr, X86::VMOVDQAYrm, TB_ALIGN_32 },
676 { X86::VMOVSLDUPYrr, X86::VMOVSLDUPYrm, 0 },
677 { X86::VMOVSHDUPYrr, X86::VMOVSHDUPYrm, 0 },
678 { X86::VMOVUPDYrr, X86::VMOVUPDYrm, 0 },
679 { X86::VMOVUPSYrr, X86::VMOVUPSYrm, 0 },
680 { X86::VPERMILPDYri, X86::VPERMILPDYmi, 0 },
681 { X86::VPERMILPSYri, X86::VPERMILPSYmi, 0 },
682 { X86::VPTESTYrr, X86::VPTESTYrm, 0 },
683 { X86::VRCPPSYr, X86::VRCPPSYm, 0 },
684 { X86::VROUNDYPDr, X86::VROUNDYPDm, 0 },
685 { X86::VROUNDYPSr, X86::VROUNDYPSm, 0 },
686 { X86::VRSQRTPSYr, X86::VRSQRTPSYm, 0 },
687 { X86::VSQRTPDYr, X86::VSQRTPDYm, 0 },
688 { X86::VSQRTPSYr, X86::VSQRTPSYm, 0 },
689 { X86::VTESTPDYrr, X86::VTESTPDYrm, 0 },
690 { X86::VTESTPSYrr, X86::VTESTPSYrm, 0 },
691
692 // AVX2 foldable instructions
693
694 // VBROADCASTS{SD}rr register instructions were an AVX2 addition while the
695 // VBROADCASTS{SD}rm memory instructions were available from AVX1.
696 // TB_NO_REVERSE prevents unfolding from introducing an illegal instruction
697 // on AVX1 targets. The VPBROADCAST instructions are all AVX2 instructions
698 // so they don't need an equivalent limitation.
699 { X86::VBROADCASTSSrr, X86::VBROADCASTSSrm, TB_NO_REVERSE },
700 { X86::VBROADCASTSSYrr, X86::VBROADCASTSSYrm, TB_NO_REVERSE },
701 { X86::VBROADCASTSDYrr, X86::VBROADCASTSDYrm, TB_NO_REVERSE },
702 { X86::VPABSBrr256, X86::VPABSBrm256, 0 },
703 { X86::VPABSDrr256, X86::VPABSDrm256, 0 },
704 { X86::VPABSWrr256, X86::VPABSWrm256, 0 },
705 { X86::VPBROADCASTBrr, X86::VPBROADCASTBrm, 0 },
706 { X86::VPBROADCASTBYrr, X86::VPBROADCASTBYrm, 0 },
707 { X86::VPBROADCASTDrr, X86::VPBROADCASTDrm, 0 },
708 { X86::VPBROADCASTDYrr, X86::VPBROADCASTDYrm, 0 },
709 { X86::VPBROADCASTQrr, X86::VPBROADCASTQrm, 0 },
710 { X86::VPBROADCASTQYrr, X86::VPBROADCASTQYrm, 0 },
711 { X86::VPBROADCASTWrr, X86::VPBROADCASTWrm, 0 },
712 { X86::VPBROADCASTWYrr, X86::VPBROADCASTWYrm, 0 },
713 { X86::VPERMPDYri, X86::VPERMPDYmi, 0 },
714 { X86::VPERMQYri, X86::VPERMQYmi, 0 },
715 { X86::VPMOVSXBDYrr, X86::VPMOVSXBDYrm, 0 },
716 { X86::VPMOVSXBQYrr, X86::VPMOVSXBQYrm, 0 },
717 { X86::VPMOVSXBWYrr, X86::VPMOVSXBWYrm, 0 },
718 { X86::VPMOVSXDQYrr, X86::VPMOVSXDQYrm, 0 },
719 { X86::VPMOVSXWDYrr, X86::VPMOVSXWDYrm, 0 },
720 { X86::VPMOVSXWQYrr, X86::VPMOVSXWQYrm, 0 },
721 { X86::VPMOVZXBDYrr, X86::VPMOVZXBDYrm, 0 },
722 { X86::VPMOVZXBQYrr, X86::VPMOVZXBQYrm, 0 },
723 { X86::VPMOVZXBWYrr, X86::VPMOVZXBWYrm, 0 },
724 { X86::VPMOVZXDQYrr, X86::VPMOVZXDQYrm, 0 },
725 { X86::VPMOVZXWDYrr, X86::VPMOVZXWDYrm, 0 },
726 { X86::VPMOVZXWQYrr, X86::VPMOVZXWQYrm, 0 },
727 { X86::VPSHUFDYri, X86::VPSHUFDYmi, 0 },
728 { X86::VPSHUFHWYri, X86::VPSHUFHWYmi, 0 },
729 { X86::VPSHUFLWYri, X86::VPSHUFLWYmi, 0 },
730
731 // XOP foldable instructions
732 { X86::VFRCZPDrr, X86::VFRCZPDrm, 0 },
733 { X86::VFRCZPDrrY, X86::VFRCZPDrmY, 0 },
734 { X86::VFRCZPSrr, X86::VFRCZPSrm, 0 },
735 { X86::VFRCZPSrrY, X86::VFRCZPSrmY, 0 },
736 { X86::VFRCZSDrr, X86::VFRCZSDrm, 0 },
737 { X86::VFRCZSSrr, X86::VFRCZSSrm, 0 },
738 { X86::VPHADDBDrr, X86::VPHADDBDrm, 0 },
739 { X86::VPHADDBQrr, X86::VPHADDBQrm, 0 },
740 { X86::VPHADDBWrr, X86::VPHADDBWrm, 0 },
741 { X86::VPHADDDQrr, X86::VPHADDDQrm, 0 },
742 { X86::VPHADDWDrr, X86::VPHADDWDrm, 0 },
743 { X86::VPHADDWQrr, X86::VPHADDWQrm, 0 },
744 { X86::VPHADDUBDrr, X86::VPHADDUBDrm, 0 },
745 { X86::VPHADDUBQrr, X86::VPHADDUBQrm, 0 },
746 { X86::VPHADDUBWrr, X86::VPHADDUBWrm, 0 },
747 { X86::VPHADDUDQrr, X86::VPHADDUDQrm, 0 },
748 { X86::VPHADDUWDrr, X86::VPHADDUWDrm, 0 },
749 { X86::VPHADDUWQrr, X86::VPHADDUWQrm, 0 },
750 { X86::VPHSUBBWrr, X86::VPHSUBBWrm, 0 },
751 { X86::VPHSUBDQrr, X86::VPHSUBDQrm, 0 },
752 { X86::VPHSUBWDrr, X86::VPHSUBWDrm, 0 },
753 { X86::VPROTBri, X86::VPROTBmi, 0 },
754 { X86::VPROTBrr, X86::VPROTBmr, 0 },
755 { X86::VPROTDri, X86::VPROTDmi, 0 },
756 { X86::VPROTDrr, X86::VPROTDmr, 0 },
757 { X86::VPROTQri, X86::VPROTQmi, 0 },
758 { X86::VPROTQrr, X86::VPROTQmr, 0 },
759 { X86::VPROTWri, X86::VPROTWmi, 0 },
760 { X86::VPROTWrr, X86::VPROTWmr, 0 },
761 { X86::VPSHABrr, X86::VPSHABmr, 0 },
762 { X86::VPSHADrr, X86::VPSHADmr, 0 },
763 { X86::VPSHAQrr, X86::VPSHAQmr, 0 },
764 { X86::VPSHAWrr, X86::VPSHAWmr, 0 },
765 { X86::VPSHLBrr, X86::VPSHLBmr, 0 },
766 { X86::VPSHLDrr, X86::VPSHLDmr, 0 },
767 { X86::VPSHLQrr, X86::VPSHLQmr, 0 },
768 { X86::VPSHLWrr, X86::VPSHLWmr, 0 },
769
770 // BMI/BMI2/LZCNT/POPCNT/TBM foldable instructions
771 { X86::BEXTR32rr, X86::BEXTR32rm, 0 },
772 { X86::BEXTR64rr, X86::BEXTR64rm, 0 },
773 { X86::BEXTRI32ri, X86::BEXTRI32mi, 0 },
774 { X86::BEXTRI64ri, X86::BEXTRI64mi, 0 },
775 { X86::BLCFILL32rr, X86::BLCFILL32rm, 0 },
776 { X86::BLCFILL64rr, X86::BLCFILL64rm, 0 },
777 { X86::BLCI32rr, X86::BLCI32rm, 0 },
778 { X86::BLCI64rr, X86::BLCI64rm, 0 },
779 { X86::BLCIC32rr, X86::BLCIC32rm, 0 },
780 { X86::BLCIC64rr, X86::BLCIC64rm, 0 },
781 { X86::BLCMSK32rr, X86::BLCMSK32rm, 0 },
782 { X86::BLCMSK64rr, X86::BLCMSK64rm, 0 },
783 { X86::BLCS32rr, X86::BLCS32rm, 0 },
784 { X86::BLCS64rr, X86::BLCS64rm, 0 },
785 { X86::BLSFILL32rr, X86::BLSFILL32rm, 0 },
786 { X86::BLSFILL64rr, X86::BLSFILL64rm, 0 },
787 { X86::BLSI32rr, X86::BLSI32rm, 0 },
788 { X86::BLSI64rr, X86::BLSI64rm, 0 },
789 { X86::BLSIC32rr, X86::BLSIC32rm, 0 },
790 { X86::BLSIC64rr, X86::BLSIC64rm, 0 },
791 { X86::BLSMSK32rr, X86::BLSMSK32rm, 0 },
792 { X86::BLSMSK64rr, X86::BLSMSK64rm, 0 },
793 { X86::BLSR32rr, X86::BLSR32rm, 0 },
794 { X86::BLSR64rr, X86::BLSR64rm, 0 },
795 { X86::BZHI32rr, X86::BZHI32rm, 0 },
796 { X86::BZHI64rr, X86::BZHI64rm, 0 },
797 { X86::LZCNT16rr, X86::LZCNT16rm, 0 },
798 { X86::LZCNT32rr, X86::LZCNT32rm, 0 },
799 { X86::LZCNT64rr, X86::LZCNT64rm, 0 },
800 { X86::POPCNT16rr, X86::POPCNT16rm, 0 },
801 { X86::POPCNT32rr, X86::POPCNT32rm, 0 },
802 { X86::POPCNT64rr, X86::POPCNT64rm, 0 },
803 { X86::RORX32ri, X86::RORX32mi, 0 },
804 { X86::RORX64ri, X86::RORX64mi, 0 },
805 { X86::SARX32rr, X86::SARX32rm, 0 },
806 { X86::SARX64rr, X86::SARX64rm, 0 },
807 { X86::SHRX32rr, X86::SHRX32rm, 0 },
808 { X86::SHRX64rr, X86::SHRX64rm, 0 },
809 { X86::SHLX32rr, X86::SHLX32rm, 0 },
810 { X86::SHLX64rr, X86::SHLX64rm, 0 },
811 { X86::T1MSKC32rr, X86::T1MSKC32rm, 0 },
812 { X86::T1MSKC64rr, X86::T1MSKC64rm, 0 },
813 { X86::TZCNT16rr, X86::TZCNT16rm, 0 },
814 { X86::TZCNT32rr, X86::TZCNT32rm, 0 },
815 { X86::TZCNT64rr, X86::TZCNT64rm, 0 },
816 { X86::TZMSK32rr, X86::TZMSK32rm, 0 },
817 { X86::TZMSK64rr, X86::TZMSK64rm, 0 },
818
819 // AVX-512 foldable instructions
820 { X86::VMOV64toPQIZrr, X86::VMOVQI2PQIZrm, 0 },
821 { X86::VMOVDI2SSZrr, X86::VMOVDI2SSZrm, 0 },
822 { X86::VMOVAPDZrr, X86::VMOVAPDZrm, TB_ALIGN_64 },
823 { X86::VMOVAPSZrr, X86::VMOVAPSZrm, TB_ALIGN_64 },
824 { X86::VMOVDQA32Zrr, X86::VMOVDQA32Zrm, TB_ALIGN_64 },
825 { X86::VMOVDQA64Zrr, X86::VMOVDQA64Zrm, TB_ALIGN_64 },
826 { X86::VMOVDQU8Zrr, X86::VMOVDQU8Zrm, 0 },
827 { X86::VMOVDQU16Zrr, X86::VMOVDQU16Zrm, 0 },
828 { X86::VMOVDQU32Zrr, X86::VMOVDQU32Zrm, 0 },
829 { X86::VMOVDQU64Zrr, X86::VMOVDQU64Zrm, 0 },
830 { X86::VMOVUPDZrr, X86::VMOVUPDZrm, 0 },
831 { X86::VMOVUPSZrr, X86::VMOVUPSZrm, 0 },
832 { X86::VPABSDZrr, X86::VPABSDZrm, 0 },
833 { X86::VPABSQZrr, X86::VPABSQZrm, 0 },
834 { X86::VBROADCASTSSZr, X86::VBROADCASTSSZm, TB_NO_REVERSE },
835 { X86::VBROADCASTSSZr_s, X86::VBROADCASTSSZm, TB_NO_REVERSE },
836 { X86::VBROADCASTSDZr, X86::VBROADCASTSDZm, TB_NO_REVERSE },
837 { X86::VBROADCASTSDZr_s, X86::VBROADCASTSDZm, TB_NO_REVERSE },
838
839 // AVX-512 foldable instructions (256-bit versions)
840 { X86::VMOVAPDZ256rr, X86::VMOVAPDZ256rm, TB_ALIGN_32 },
841 { X86::VMOVAPSZ256rr, X86::VMOVAPSZ256rm, TB_ALIGN_32 },
842 { X86::VMOVDQA32Z256rr, X86::VMOVDQA32Z256rm, TB_ALIGN_32 },
843 { X86::VMOVDQA64Z256rr, X86::VMOVDQA64Z256rm, TB_ALIGN_32 },
844 { X86::VMOVDQU8Z256rr, X86::VMOVDQU8Z256rm, 0 },
845 { X86::VMOVDQU16Z256rr, X86::VMOVDQU16Z256rm, 0 },
846 { X86::VMOVDQU32Z256rr, X86::VMOVDQU32Z256rm, 0 },
847 { X86::VMOVDQU64Z256rr, X86::VMOVDQU64Z256rm, 0 },
848 { X86::VMOVUPDZ256rr, X86::VMOVUPDZ256rm, 0 },
849 { X86::VMOVUPSZ256rr, X86::VMOVUPSZ256rm, 0 },
850 { X86::VBROADCASTSSZ256r, X86::VBROADCASTSSZ256m, TB_NO_REVERSE },
851 { X86::VBROADCASTSSZ256r_s, X86::VBROADCASTSSZ256m, TB_NO_REVERSE },
852 { X86::VBROADCASTSDZ256r, X86::VBROADCASTSDZ256m, TB_NO_REVERSE },
853 { X86::VBROADCASTSDZ256r_s, X86::VBROADCASTSDZ256m, TB_NO_REVERSE },
854
855 // AVX-512 foldable instructions (128-bit versions)
856 { X86::VMOVAPDZ128rr, X86::VMOVAPDZ128rm, TB_ALIGN_16 },
857 { X86::VMOVAPSZ128rr, X86::VMOVAPSZ128rm, TB_ALIGN_16 },
858 { X86::VMOVDQA32Z128rr, X86::VMOVDQA32Z128rm, TB_ALIGN_16 },
859 { X86::VMOVDQA64Z128rr, X86::VMOVDQA64Z128rm, TB_ALIGN_16 },
860 { X86::VMOVDQU8Z128rr, X86::VMOVDQU8Z128rm, 0 },
861 { X86::VMOVDQU16Z128rr, X86::VMOVDQU16Z128rm, 0 },
862 { X86::VMOVDQU32Z128rr, X86::VMOVDQU32Z128rm, 0 },
863 { X86::VMOVDQU64Z128rr, X86::VMOVDQU64Z128rm, 0 },
864 { X86::VMOVUPDZ128rr, X86::VMOVUPDZ128rm, 0 },
865 { X86::VMOVUPSZ128rr, X86::VMOVUPSZ128rm, 0 },
866 { X86::VBROADCASTSSZ128r, X86::VBROADCASTSSZ128m, TB_NO_REVERSE },
867 { X86::VBROADCASTSSZ128r_s, X86::VBROADCASTSSZ128m, TB_NO_REVERSE },
868 // F16C foldable instructions
869 { X86::VCVTPH2PSrr, X86::VCVTPH2PSrm, 0 },
870 { X86::VCVTPH2PSYrr, X86::VCVTPH2PSYrm, 0 },
871
872 // AES foldable instructions
873 { X86::AESIMCrr, X86::AESIMCrm, TB_ALIGN_16 },
874 { X86::AESKEYGENASSIST128rr, X86::AESKEYGENASSIST128rm, TB_ALIGN_16 },
875 { X86::VAESIMCrr, X86::VAESIMCrm, 0 },
876 { X86::VAESKEYGENASSIST128rr, X86::VAESKEYGENASSIST128rm, 0 }
877 };
878
879 for (X86MemoryFoldTableEntry Entry : MemoryFoldTable1) {
880 AddTableEntry(RegOp2MemOpTable1, MemOp2RegOpTable,
881 Entry.RegOp, Entry.MemOp,
882 // Index 1, folded load
883 Entry.Flags | TB_INDEX_1 | TB_FOLDED_LOAD);
884 }
885
886 static const X86MemoryFoldTableEntry MemoryFoldTable2[] = {
887 { X86::ADC32rr, X86::ADC32rm, 0 },
888 { X86::ADC64rr, X86::ADC64rm, 0 },
889 { X86::ADD16rr, X86::ADD16rm, 0 },
890 { X86::ADD16rr_DB, X86::ADD16rm, TB_NO_REVERSE },
891 { X86::ADD32rr, X86::ADD32rm, 0 },
892 { X86::ADD32rr_DB, X86::ADD32rm, TB_NO_REVERSE },
893 { X86::ADD64rr, X86::ADD64rm, 0 },
894 { X86::ADD64rr_DB, X86::ADD64rm, TB_NO_REVERSE },
895 { X86::ADD8rr, X86::ADD8rm, 0 },
896 { X86::ADDPDrr, X86::ADDPDrm, TB_ALIGN_16 },
897 { X86::ADDPSrr, X86::ADDPSrm, TB_ALIGN_16 },
898 { X86::ADDSDrr, X86::ADDSDrm, 0 },
899 { X86::ADDSDrr_Int, X86::ADDSDrm_Int, 0 },
900 { X86::ADDSSrr, X86::ADDSSrm, 0 },
901 { X86::ADDSSrr_Int, X86::ADDSSrm_Int, 0 },
902 { X86::ADDSUBPDrr, X86::ADDSUBPDrm, TB_ALIGN_16 },
903 { X86::ADDSUBPSrr, X86::ADDSUBPSrm, TB_ALIGN_16 },
904 { X86::AND16rr, X86::AND16rm, 0 },
905 { X86::AND32rr, X86::AND32rm, 0 },
906 { X86::AND64rr, X86::AND64rm, 0 },
907 { X86::AND8rr, X86::AND8rm, 0 },
908 { X86::ANDNPDrr, X86::ANDNPDrm, TB_ALIGN_16 },
909 { X86::ANDNPSrr, X86::ANDNPSrm, TB_ALIGN_16 },
910 { X86::ANDPDrr, X86::ANDPDrm, TB_ALIGN_16 },
911 { X86::ANDPSrr, X86::ANDPSrm, TB_ALIGN_16 },
912 { X86::BLENDPDrri, X86::BLENDPDrmi, TB_ALIGN_16 },
913 { X86::BLENDPSrri, X86::BLENDPSrmi, TB_ALIGN_16 },
914 { X86::BLENDVPDrr0, X86::BLENDVPDrm0, TB_ALIGN_16 },
915 { X86::BLENDVPSrr0, X86::BLENDVPSrm0, TB_ALIGN_16 },
916 { X86::CMOVA16rr, X86::CMOVA16rm, 0 },
917 { X86::CMOVA32rr, X86::CMOVA32rm, 0 },
918 { X86::CMOVA64rr, X86::CMOVA64rm, 0 },
919 { X86::CMOVAE16rr, X86::CMOVAE16rm, 0 },
920 { X86::CMOVAE32rr, X86::CMOVAE32rm, 0 },
921 { X86::CMOVAE64rr, X86::CMOVAE64rm, 0 },
922 { X86::CMOVB16rr, X86::CMOVB16rm, 0 },
923 { X86::CMOVB32rr, X86::CMOVB32rm, 0 },
924 { X86::CMOVB64rr, X86::CMOVB64rm, 0 },
925 { X86::CMOVBE16rr, X86::CMOVBE16rm, 0 },
926 { X86::CMOVBE32rr, X86::CMOVBE32rm, 0 },
927 { X86::CMOVBE64rr, X86::CMOVBE64rm, 0 },
928 { X86::CMOVE16rr, X86::CMOVE16rm, 0 },
929 { X86::CMOVE32rr, X86::CMOVE32rm, 0 },
930 { X86::CMOVE64rr, X86::CMOVE64rm, 0 },
931 { X86::CMOVG16rr, X86::CMOVG16rm, 0 },
932 { X86::CMOVG32rr, X86::CMOVG32rm, 0 },
933 { X86::CMOVG64rr, X86::CMOVG64rm, 0 },
934 { X86::CMOVGE16rr, X86::CMOVGE16rm, 0 },
935 { X86::CMOVGE32rr, X86::CMOVGE32rm, 0 },
936 { X86::CMOVGE64rr, X86::CMOVGE64rm, 0 },
937 { X86::CMOVL16rr, X86::CMOVL16rm, 0 },
938 { X86::CMOVL32rr, X86::CMOVL32rm, 0 },
939 { X86::CMOVL64rr, X86::CMOVL64rm, 0 },
940 { X86::CMOVLE16rr, X86::CMOVLE16rm, 0 },
941 { X86::CMOVLE32rr, X86::CMOVLE32rm, 0 },
942 { X86::CMOVLE64rr, X86::CMOVLE64rm, 0 },
943 { X86::CMOVNE16rr, X86::CMOVNE16rm, 0 },
944 { X86::CMOVNE32rr, X86::CMOVNE32rm, 0 },
945 { X86::CMOVNE64rr, X86::CMOVNE64rm, 0 },
946 { X86::CMOVNO16rr, X86::CMOVNO16rm, 0 },
947 { X86::CMOVNO32rr, X86::CMOVNO32rm, 0 },
948 { X86::CMOVNO64rr, X86::CMOVNO64rm, 0 },
949 { X86::CMOVNP16rr, X86::CMOVNP16rm, 0 },
950 { X86::CMOVNP32rr, X86::CMOVNP32rm, 0 },
951 { X86::CMOVNP64rr, X86::CMOVNP64rm, 0 },
952 { X86::CMOVNS16rr, X86::CMOVNS16rm, 0 },
953 { X86::CMOVNS32rr, X86::CMOVNS32rm, 0 },
954 { X86::CMOVNS64rr, X86::CMOVNS64rm, 0 },
955 { X86::CMOVO16rr, X86::CMOVO16rm, 0 },
956 { X86::CMOVO32rr, X86::CMOVO32rm, 0 },
957 { X86::CMOVO64rr, X86::CMOVO64rm, 0 },
958 { X86::CMOVP16rr, X86::CMOVP16rm, 0 },
959 { X86::CMOVP32rr, X86::CMOVP32rm, 0 },
960 { X86::CMOVP64rr, X86::CMOVP64rm, 0 },
961 { X86::CMOVS16rr, X86::CMOVS16rm, 0 },
962 { X86::CMOVS32rr, X86::CMOVS32rm, 0 },
963 { X86::CMOVS64rr, X86::CMOVS64rm, 0 },
964 { X86::CMPPDrri, X86::CMPPDrmi, TB_ALIGN_16 },
965 { X86::CMPPSrri, X86::CMPPSrmi, TB_ALIGN_16 },
966 { X86::CMPSDrr, X86::CMPSDrm, 0 },
967 { X86::CMPSSrr, X86::CMPSSrm, 0 },
968 { X86::CRC32r32r32, X86::CRC32r32m32, 0 },
969 { X86::CRC32r64r64, X86::CRC32r64m64, 0 },
970 { X86::DIVPDrr, X86::DIVPDrm, TB_ALIGN_16 },
971 { X86::DIVPSrr, X86::DIVPSrm, TB_ALIGN_16 },
972 { X86::DIVSDrr, X86::DIVSDrm, 0 },
973 { X86::DIVSDrr_Int, X86::DIVSDrm_Int, 0 },
974 { X86::DIVSSrr, X86::DIVSSrm, 0 },
975 { X86::DIVSSrr_Int, X86::DIVSSrm_Int, 0 },
976 { X86::DPPDrri, X86::DPPDrmi, TB_ALIGN_16 },
977 { X86::DPPSrri, X86::DPPSrmi, TB_ALIGN_16 },
978
979 // Do not fold Fs* scalar logical op loads because there are no scalar
980 // load variants for these instructions. When folded, the load is required
981 // to be 128-bits, so the load size would not match.
982
983 { X86::FvANDNPDrr, X86::FvANDNPDrm, TB_ALIGN_16 },
984 { X86::FvANDNPSrr, X86::FvANDNPSrm, TB_ALIGN_16 },
985 { X86::FvANDPDrr, X86::FvANDPDrm, TB_ALIGN_16 },
986 { X86::FvANDPSrr, X86::FvANDPSrm, TB_ALIGN_16 },
987 { X86::FvORPDrr, X86::FvORPDrm, TB_ALIGN_16 },
988 { X86::FvORPSrr, X86::FvORPSrm, TB_ALIGN_16 },
989 { X86::FvXORPDrr, X86::FvXORPDrm, TB_ALIGN_16 },
990 { X86::FvXORPSrr, X86::FvXORPSrm, TB_ALIGN_16 },
991 { X86::HADDPDrr, X86::HADDPDrm, TB_ALIGN_16 },
992 { X86::HADDPSrr, X86::HADDPSrm, TB_ALIGN_16 },
993 { X86::HSUBPDrr, X86::HSUBPDrm, TB_ALIGN_16 },
994 { X86::HSUBPSrr, X86::HSUBPSrm, TB_ALIGN_16 },
995 { X86::IMUL16rr, X86::IMUL16rm, 0 },
996 { X86::IMUL32rr, X86::IMUL32rm, 0 },
997 { X86::IMUL64rr, X86::IMUL64rm, 0 },
998 { X86::Int_CMPSDrr, X86::Int_CMPSDrm, 0 },
999 { X86::Int_CMPSSrr, X86::Int_CMPSSrm, 0 },
1000 { X86::Int_CVTSD2SSrr, X86::Int_CVTSD2SSrm, 0 },
1001 { X86::Int_CVTSI2SD64rr,X86::Int_CVTSI2SD64rm, 0 },
1002 { X86::Int_CVTSI2SDrr, X86::Int_CVTSI2SDrm, 0 },
1003 { X86::Int_CVTSI2SS64rr,X86::Int_CVTSI2SS64rm, 0 },
1004 { X86::Int_CVTSI2SSrr, X86::Int_CVTSI2SSrm, 0 },
1005 { X86::Int_CVTSS2SDrr, X86::Int_CVTSS2SDrm, 0 },
1006 { X86::MAXPDrr, X86::MAXPDrm, TB_ALIGN_16 },
1007 { X86::MAXPSrr, X86::MAXPSrm, TB_ALIGN_16 },
1008 { X86::MAXSDrr, X86::MAXSDrm, 0 },
1009 { X86::MAXSDrr_Int, X86::MAXSDrm_Int, 0 },
1010 { X86::MAXSSrr, X86::MAXSSrm, 0 },
1011 { X86::MAXSSrr_Int, X86::MAXSSrm_Int, 0 },
1012 { X86::MINPDrr, X86::MINPDrm, TB_ALIGN_16 },
1013 { X86::MINPSrr, X86::MINPSrm, TB_ALIGN_16 },
1014 { X86::MINSDrr, X86::MINSDrm, 0 },
1015 { X86::MINSDrr_Int, X86::MINSDrm_Int, 0 },
1016 { X86::MINSSrr, X86::MINSSrm, 0 },
1017 { X86::MINSSrr_Int, X86::MINSSrm_Int, 0 },
1018 { X86::MOVLHPSrr, X86::MOVHPSrm, TB_NO_REVERSE },
1019 { X86::MPSADBWrri, X86::MPSADBWrmi, TB_ALIGN_16 },
1020 { X86::MULPDrr, X86::MULPDrm, TB_ALIGN_16 },
1021 { X86::MULPSrr, X86::MULPSrm, TB_ALIGN_16 },
1022 { X86::MULSDrr, X86::MULSDrm, 0 },
1023 { X86::MULSDrr_Int, X86::MULSDrm_Int, 0 },
1024 { X86::MULSSrr, X86::MULSSrm, 0 },
1025 { X86::MULSSrr_Int, X86::MULSSrm_Int, 0 },
1026 { X86::OR16rr, X86::OR16rm, 0 },
1027 { X86::OR32rr, X86::OR32rm, 0 },
1028 { X86::OR64rr, X86::OR64rm, 0 },
1029 { X86::OR8rr, X86::OR8rm, 0 },
1030 { X86::ORPDrr, X86::ORPDrm, TB_ALIGN_16 },
1031 { X86::ORPSrr, X86::ORPSrm, TB_ALIGN_16 },
1032 { X86::PACKSSDWrr, X86::PACKSSDWrm, TB_ALIGN_16 },
1033 { X86::PACKSSWBrr, X86::PACKSSWBrm, TB_ALIGN_16 },
1034 { X86::PACKUSDWrr, X86::PACKUSDWrm, TB_ALIGN_16 },
1035 { X86::PACKUSWBrr, X86::PACKUSWBrm, TB_ALIGN_16 },
1036 { X86::PADDBrr, X86::PADDBrm, TB_ALIGN_16 },
1037 { X86::PADDDrr, X86::PADDDrm, TB_ALIGN_16 },
1038 { X86::PADDQrr, X86::PADDQrm, TB_ALIGN_16 },
1039 { X86::PADDSBrr, X86::PADDSBrm, TB_ALIGN_16 },
1040 { X86::PADDSWrr, X86::PADDSWrm, TB_ALIGN_16 },
1041 { X86::PADDUSBrr, X86::PADDUSBrm, TB_ALIGN_16 },
1042 { X86::PADDUSWrr, X86::PADDUSWrm, TB_ALIGN_16 },
1043 { X86::PADDWrr, X86::PADDWrm, TB_ALIGN_16 },
1044 { X86::PALIGNRrri, X86::PALIGNRrmi, TB_ALIGN_16 },
1045 { X86::PANDNrr, X86::PANDNrm, TB_ALIGN_16 },
1046 { X86::PANDrr, X86::PANDrm, TB_ALIGN_16 },
1047 { X86::PAVGBrr, X86::PAVGBrm, TB_ALIGN_16 },
1048 { X86::PAVGWrr, X86::PAVGWrm, TB_ALIGN_16 },
1049 { X86::PBLENDVBrr0, X86::PBLENDVBrm0, TB_ALIGN_16 },
1050 { X86::PBLENDWrri, X86::PBLENDWrmi, TB_ALIGN_16 },
1051 { X86::PCLMULQDQrr, X86::PCLMULQDQrm, TB_ALIGN_16 },
1052 { X86::PCMPEQBrr, X86::PCMPEQBrm, TB_ALIGN_16 },
1053 { X86::PCMPEQDrr, X86::PCMPEQDrm, TB_ALIGN_16 },
1054 { X86::PCMPEQQrr, X86::PCMPEQQrm, TB_ALIGN_16 },
1055 { X86::PCMPEQWrr, X86::PCMPEQWrm, TB_ALIGN_16 },
1056 { X86::PCMPGTBrr, X86::PCMPGTBrm, TB_ALIGN_16 },
1057 { X86::PCMPGTDrr, X86::PCMPGTDrm, TB_ALIGN_16 },
1058 { X86::PCMPGTQrr, X86::PCMPGTQrm, TB_ALIGN_16 },
1059 { X86::PCMPGTWrr, X86::PCMPGTWrm, TB_ALIGN_16 },
1060 { X86::PHADDDrr, X86::PHADDDrm, TB_ALIGN_16 },
1061 { X86::PHADDWrr, X86::PHADDWrm, TB_ALIGN_16 },
1062 { X86::PHADDSWrr128, X86::PHADDSWrm128, TB_ALIGN_16 },
1063 { X86::PHSUBDrr, X86::PHSUBDrm, TB_ALIGN_16 },
1064 { X86::PHSUBSWrr128, X86::PHSUBSWrm128, TB_ALIGN_16 },
1065 { X86::PHSUBWrr, X86::PHSUBWrm, TB_ALIGN_16 },
1066 { X86::PINSRBrr, X86::PINSRBrm, 0 },
1067 { X86::PINSRDrr, X86::PINSRDrm, 0 },
1068 { X86::PINSRQrr, X86::PINSRQrm, 0 },
1069 { X86::PINSRWrri, X86::PINSRWrmi, 0 },
1070 { X86::PMADDUBSWrr128, X86::PMADDUBSWrm128, TB_ALIGN_16 },
1071 { X86::PMADDWDrr, X86::PMADDWDrm, TB_ALIGN_16 },
1072 { X86::PMAXSWrr, X86::PMAXSWrm, TB_ALIGN_16 },
1073 { X86::PMAXUBrr, X86::PMAXUBrm, TB_ALIGN_16 },
1074 { X86::PMINSWrr, X86::PMINSWrm, TB_ALIGN_16 },
1075 { X86::PMINUBrr, X86::PMINUBrm, TB_ALIGN_16 },
1076 { X86::PMINSBrr, X86::PMINSBrm, TB_ALIGN_16 },
1077 { X86::PMINSDrr, X86::PMINSDrm, TB_ALIGN_16 },
1078 { X86::PMINUDrr, X86::PMINUDrm, TB_ALIGN_16 },
1079 { X86::PMINUWrr, X86::PMINUWrm, TB_ALIGN_16 },
1080 { X86::PMAXSBrr, X86::PMAXSBrm, TB_ALIGN_16 },
1081 { X86::PMAXSDrr, X86::PMAXSDrm, TB_ALIGN_16 },
1082 { X86::PMAXUDrr, X86::PMAXUDrm, TB_ALIGN_16 },
1083 { X86::PMAXUWrr, X86::PMAXUWrm, TB_ALIGN_16 },
1084 { X86::PMULDQrr, X86::PMULDQrm, TB_ALIGN_16 },
1085 { X86::PMULHRSWrr128, X86::PMULHRSWrm128, TB_ALIGN_16 },
1086 { X86::PMULHUWrr, X86::PMULHUWrm, TB_ALIGN_16 },
1087 { X86::PMULHWrr, X86::PMULHWrm, TB_ALIGN_16 },
1088 { X86::PMULLDrr, X86::PMULLDrm, TB_ALIGN_16 },
1089 { X86::PMULLWrr, X86::PMULLWrm, TB_ALIGN_16 },
1090 { X86::PMULUDQrr, X86::PMULUDQrm, TB_ALIGN_16 },
1091 { X86::PORrr, X86::PORrm, TB_ALIGN_16 },
1092 { X86::PSADBWrr, X86::PSADBWrm, TB_ALIGN_16 },
1093 { X86::PSHUFBrr, X86::PSHUFBrm, TB_ALIGN_16 },
1094 { X86::PSIGNBrr128, X86::PSIGNBrm128, TB_ALIGN_16 },
1095 { X86::PSIGNWrr128, X86::PSIGNWrm128, TB_ALIGN_16 },
1096 { X86::PSIGNDrr128, X86::PSIGNDrm128, TB_ALIGN_16 },
1097 { X86::PSLLDrr, X86::PSLLDrm, TB_ALIGN_16 },
1098 { X86::PSLLQrr, X86::PSLLQrm, TB_ALIGN_16 },
1099 { X86::PSLLWrr, X86::PSLLWrm, TB_ALIGN_16 },
1100 { X86::PSRADrr, X86::PSRADrm, TB_ALIGN_16 },
1101 { X86::PSRAWrr, X86::PSRAWrm, TB_ALIGN_16 },
1102 { X86::PSRLDrr, X86::PSRLDrm, TB_ALIGN_16 },
1103 { X86::PSRLQrr, X86::PSRLQrm, TB_ALIGN_16 },
1104 { X86::PSRLWrr, X86::PSRLWrm, TB_ALIGN_16 },
1105 { X86::PSUBBrr, X86::PSUBBrm, TB_ALIGN_16 },
1106 { X86::PSUBDrr, X86::PSUBDrm, TB_ALIGN_16 },
1107 { X86::PSUBQrr, X86::PSUBQrm, TB_ALIGN_16 },
1108 { X86::PSUBSBrr, X86::PSUBSBrm, TB_ALIGN_16 },
1109 { X86::PSUBSWrr, X86::PSUBSWrm, TB_ALIGN_16 },
1110 { X86::PSUBUSBrr, X86::PSUBUSBrm, TB_ALIGN_16 },
1111 { X86::PSUBUSWrr, X86::PSUBUSWrm, TB_ALIGN_16 },
1112 { X86::PSUBWrr, X86::PSUBWrm, TB_ALIGN_16 },
1113 { X86::PUNPCKHBWrr, X86::PUNPCKHBWrm, TB_ALIGN_16 },
1114 { X86::PUNPCKHDQrr, X86::PUNPCKHDQrm, TB_ALIGN_16 },
1115 { X86::PUNPCKHQDQrr, X86::PUNPCKHQDQrm, TB_ALIGN_16 },
1116 { X86::PUNPCKHWDrr, X86::PUNPCKHWDrm, TB_ALIGN_16 },
1117 { X86::PUNPCKLBWrr, X86::PUNPCKLBWrm, TB_ALIGN_16 },
1118 { X86::PUNPCKLDQrr, X86::PUNPCKLDQrm, TB_ALIGN_16 },
1119 { X86::PUNPCKLQDQrr, X86::PUNPCKLQDQrm, TB_ALIGN_16 },
1120 { X86::PUNPCKLWDrr, X86::PUNPCKLWDrm, TB_ALIGN_16 },
1121 { X86::PXORrr, X86::PXORrm, TB_ALIGN_16 },
1122 { X86::ROUNDSDr, X86::ROUNDSDm, 0 },
1123 { X86::ROUNDSSr, X86::ROUNDSSm, 0 },
1124 { X86::SBB32rr, X86::SBB32rm, 0 },
1125 { X86::SBB64rr, X86::SBB64rm, 0 },
1126 { X86::SHUFPDrri, X86::SHUFPDrmi, TB_ALIGN_16 },
1127 { X86::SHUFPSrri, X86::SHUFPSrmi, TB_ALIGN_16 },
1128 { X86::SUB16rr, X86::SUB16rm, 0 },
1129 { X86::SUB32rr, X86::SUB32rm, 0 },
1130 { X86::SUB64rr, X86::SUB64rm, 0 },
1131 { X86::SUB8rr, X86::SUB8rm, 0 },
1132 { X86::SUBPDrr, X86::SUBPDrm, TB_ALIGN_16 },
1133 { X86::SUBPSrr, X86::SUBPSrm, TB_ALIGN_16 },
1134 { X86::SUBSDrr, X86::SUBSDrm, 0 },
1135 { X86::SUBSDrr_Int, X86::SUBSDrm_Int, 0 },
1136 { X86::SUBSSrr, X86::SUBSSrm, 0 },
1137 { X86::SUBSSrr_Int, X86::SUBSSrm_Int, 0 },
1138 // FIXME: TEST*rr -> swapped operand of TEST*mr.
1139 { X86::UNPCKHPDrr, X86::UNPCKHPDrm, TB_ALIGN_16 },
1140 { X86::UNPCKHPSrr, X86::UNPCKHPSrm, TB_ALIGN_16 },
1141 { X86::UNPCKLPDrr, X86::UNPCKLPDrm, TB_ALIGN_16 },
1142 { X86::UNPCKLPSrr, X86::UNPCKLPSrm, TB_ALIGN_16 },
1143 { X86::XOR16rr, X86::XOR16rm, 0 },
1144 { X86::XOR32rr, X86::XOR32rm, 0 },
1145 { X86::XOR64rr, X86::XOR64rm, 0 },
1146 { X86::XOR8rr, X86::XOR8rm, 0 },
1147 { X86::XORPDrr, X86::XORPDrm, TB_ALIGN_16 },
1148 { X86::XORPSrr, X86::XORPSrm, TB_ALIGN_16 },
1149
1150 // MMX version of foldable instructions
1151 { X86::MMX_CVTPI2PSirr, X86::MMX_CVTPI2PSirm, 0 },
1152 { X86::MMX_PACKSSDWirr, X86::MMX_PACKSSDWirm, 0 },
1153 { X86::MMX_PACKSSWBirr, X86::MMX_PACKSSWBirm, 0 },
1154 { X86::MMX_PACKUSWBirr, X86::MMX_PACKUSWBirm, 0 },
1155 { X86::MMX_PADDBirr, X86::MMX_PADDBirm, 0 },
1156 { X86::MMX_PADDDirr, X86::MMX_PADDDirm, 0 },
1157 { X86::MMX_PADDQirr, X86::MMX_PADDQirm, 0 },
1158 { X86::MMX_PADDSBirr, X86::MMX_PADDSBirm, 0 },
1159 { X86::MMX_PADDSWirr, X86::MMX_PADDSWirm, 0 },
1160 { X86::MMX_PADDUSBirr, X86::MMX_PADDUSBirm, 0 },
1161 { X86::MMX_PADDUSWirr, X86::MMX_PADDUSWirm, 0 },
1162 { X86::MMX_PADDWirr, X86::MMX_PADDWirm, 0 },
1163 { X86::MMX_PALIGNR64irr, X86::MMX_PALIGNR64irm, 0 },
1164 { X86::MMX_PANDNirr, X86::MMX_PANDNirm, 0 },
1165 { X86::MMX_PANDirr, X86::MMX_PANDirm, 0 },
1166 { X86::MMX_PAVGBirr, X86::MMX_PAVGBirm, 0 },
1167 { X86::MMX_PAVGWirr, X86::MMX_PAVGWirm, 0 },
1168 { X86::MMX_PCMPEQBirr, X86::MMX_PCMPEQBirm, 0 },
1169 { X86::MMX_PCMPEQDirr, X86::MMX_PCMPEQDirm, 0 },
1170 { X86::MMX_PCMPEQWirr, X86::MMX_PCMPEQWirm, 0 },
1171 { X86::MMX_PCMPGTBirr, X86::MMX_PCMPGTBirm, 0 },
1172 { X86::MMX_PCMPGTDirr, X86::MMX_PCMPGTDirm, 0 },
1173 { X86::MMX_PCMPGTWirr, X86::MMX_PCMPGTWirm, 0 },
1174 { X86::MMX_PHADDSWrr64, X86::MMX_PHADDSWrm64, 0 },
1175 { X86::MMX_PHADDWrr64, X86::MMX_PHADDWrm64, 0 },
1176 { X86::MMX_PHADDrr64, X86::MMX_PHADDrm64, 0 },
1177 { X86::MMX_PHSUBDrr64, X86::MMX_PHSUBDrm64, 0 },
1178 { X86::MMX_PHSUBSWrr64, X86::MMX_PHSUBSWrm64, 0 },
1179 { X86::MMX_PHSUBWrr64, X86::MMX_PHSUBWrm64, 0 },
1180 { X86::MMX_PINSRWirri, X86::MMX_PINSRWirmi, 0 },
1181 { X86::MMX_PMADDUBSWrr64, X86::MMX_PMADDUBSWrm64, 0 },
1182 { X86::MMX_PMADDWDirr, X86::MMX_PMADDWDirm, 0 },
1183 { X86::MMX_PMAXSWirr, X86::MMX_PMAXSWirm, 0 },
1184 { X86::MMX_PMAXUBirr, X86::MMX_PMAXUBirm, 0 },
1185 { X86::MMX_PMINSWirr, X86::MMX_PMINSWirm, 0 },
1186 { X86::MMX_PMINUBirr, X86::MMX_PMINUBirm, 0 },
1187 { X86::MMX_PMULHRSWrr64, X86::MMX_PMULHRSWrm64, 0 },
1188 { X86::MMX_PMULHUWirr, X86::MMX_PMULHUWirm, 0 },
1189 { X86::MMX_PMULHWirr, X86::MMX_PMULHWirm, 0 },
1190 { X86::MMX_PMULLWirr, X86::MMX_PMULLWirm, 0 },
1191 { X86::MMX_PMULUDQirr, X86::MMX_PMULUDQirm, 0 },
1192 { X86::MMX_PORirr, X86::MMX_PORirm, 0 },
1193 { X86::MMX_PSADBWirr, X86::MMX_PSADBWirm, 0 },
1194 { X86::MMX_PSHUFBrr64, X86::MMX_PSHUFBrm64, 0 },
1195 { X86::MMX_PSIGNBrr64, X86::MMX_PSIGNBrm64, 0 },
1196 { X86::MMX_PSIGNDrr64, X86::MMX_PSIGNDrm64, 0 },
1197 { X86::MMX_PSIGNWrr64, X86::MMX_PSIGNWrm64, 0 },
1198 { X86::MMX_PSLLDrr, X86::MMX_PSLLDrm, 0 },
1199 { X86::MMX_PSLLQrr, X86::MMX_PSLLQrm, 0 },
1200 { X86::MMX_PSLLWrr, X86::MMX_PSLLWrm, 0 },
1201 { X86::MMX_PSRADrr, X86::MMX_PSRADrm, 0 },
1202 { X86::MMX_PSRAWrr, X86::MMX_PSRAWrm, 0 },
1203 { X86::MMX_PSRLDrr, X86::MMX_PSRLDrm, 0 },
1204 { X86::MMX_PSRLQrr, X86::MMX_PSRLQrm, 0 },
1205 { X86::MMX_PSRLWrr, X86::MMX_PSRLWrm, 0 },
1206 { X86::MMX_PSUBBirr, X86::MMX_PSUBBirm, 0 },
1207 { X86::MMX_PSUBDirr, X86::MMX_PSUBDirm, 0 },
1208 { X86::MMX_PSUBQirr, X86::MMX_PSUBQirm, 0 },
1209 { X86::MMX_PSUBSBirr, X86::MMX_PSUBSBirm, 0 },
1210 { X86::MMX_PSUBSWirr, X86::MMX_PSUBSWirm, 0 },
1211 { X86::MMX_PSUBUSBirr, X86::MMX_PSUBUSBirm, 0 },
1212 { X86::MMX_PSUBUSWirr, X86::MMX_PSUBUSWirm, 0 },
1213 { X86::MMX_PSUBWirr, X86::MMX_PSUBWirm, 0 },
1214 { X86::MMX_PUNPCKHBWirr, X86::MMX_PUNPCKHBWirm, 0 },
1215 { X86::MMX_PUNPCKHDQirr, X86::MMX_PUNPCKHDQirm, 0 },
1216 { X86::MMX_PUNPCKHWDirr, X86::MMX_PUNPCKHWDirm, 0 },
1217 { X86::MMX_PUNPCKLBWirr, X86::MMX_PUNPCKLBWirm, 0 },
1218 { X86::MMX_PUNPCKLDQirr, X86::MMX_PUNPCKLDQirm, 0 },
1219 { X86::MMX_PUNPCKLWDirr, X86::MMX_PUNPCKLWDirm, 0 },
1220 { X86::MMX_PXORirr, X86::MMX_PXORirm, 0 },
1221
1222 // 3DNow! version of foldable instructions
1223 { X86::PAVGUSBrr, X86::PAVGUSBrm, 0 },
1224 { X86::PFACCrr, X86::PFACCrm, 0 },
1225 { X86::PFADDrr, X86::PFADDrm, 0 },
1226 { X86::PFCMPEQrr, X86::PFCMPEQrm, 0 },
1227 { X86::PFCMPGErr, X86::PFCMPGErm, 0 },
1228 { X86::PFCMPGTrr, X86::PFCMPGTrm, 0 },
1229 { X86::PFMAXrr, X86::PFMAXrm, 0 },
1230 { X86::PFMINrr, X86::PFMINrm, 0 },
1231 { X86::PFMULrr, X86::PFMULrm, 0 },
1232 { X86::PFNACCrr, X86::PFNACCrm, 0 },
1233 { X86::PFPNACCrr, X86::PFPNACCrm, 0 },
1234 { X86::PFRCPIT1rr, X86::PFRCPIT1rm, 0 },
1235 { X86::PFRCPIT2rr, X86::PFRCPIT2rm, 0 },
1236 { X86::PFRSQIT1rr, X86::PFRSQIT1rm, 0 },
1237 { X86::PFSUBrr, X86::PFSUBrm, 0 },
1238 { X86::PFSUBRrr, X86::PFSUBRrm, 0 },
1239 { X86::PMULHRWrr, X86::PMULHRWrm, 0 },
1240
1241 // AVX 128-bit versions of foldable instructions
1242 { X86::VCVTSD2SSrr, X86::VCVTSD2SSrm, 0 },
1243 { X86::Int_VCVTSD2SSrr, X86::Int_VCVTSD2SSrm, 0 },
1244 { X86::VCVTSI2SD64rr, X86::VCVTSI2SD64rm, 0 },
1245 { X86::Int_VCVTSI2SD64rr, X86::Int_VCVTSI2SD64rm, 0 },
1246 { X86::VCVTSI2SDrr, X86::VCVTSI2SDrm, 0 },
1247 { X86::Int_VCVTSI2SDrr, X86::Int_VCVTSI2SDrm, 0 },
1248 { X86::VCVTSI2SS64rr, X86::VCVTSI2SS64rm, 0 },
1249 { X86::Int_VCVTSI2SS64rr, X86::Int_VCVTSI2SS64rm, 0 },
1250 { X86::VCVTSI2SSrr, X86::VCVTSI2SSrm, 0 },
1251 { X86::Int_VCVTSI2SSrr, X86::Int_VCVTSI2SSrm, 0 },
1252 { X86::VCVTSS2SDrr, X86::VCVTSS2SDrm, 0 },
1253 { X86::Int_VCVTSS2SDrr, X86::Int_VCVTSS2SDrm, 0 },
1254 { X86::VRCPSSr, X86::VRCPSSm, 0 },
1255 { X86::VRCPSSr_Int, X86::VRCPSSm_Int, 0 },
1256 { X86::VRSQRTSSr, X86::VRSQRTSSm, 0 },
1257 { X86::VRSQRTSSr_Int, X86::VRSQRTSSm_Int, 0 },
1258 { X86::VSQRTSDr, X86::VSQRTSDm, 0 },
1259 { X86::VSQRTSDr_Int, X86::VSQRTSDm_Int, 0 },
1260 { X86::VSQRTSSr, X86::VSQRTSSm, 0 },
1261 { X86::VSQRTSSr_Int, X86::VSQRTSSm_Int, 0 },
1262 { X86::VADDPDrr, X86::VADDPDrm, 0 },
1263 { X86::VADDPSrr, X86::VADDPSrm, 0 },
1264 { X86::VADDSDrr, X86::VADDSDrm, 0 },
1265 { X86::VADDSDrr_Int, X86::VADDSDrm_Int, 0 },
1266 { X86::VADDSSrr, X86::VADDSSrm, 0 },
1267 { X86::VADDSSrr_Int, X86::VADDSSrm_Int, 0 },
1268 { X86::VADDSUBPDrr, X86::VADDSUBPDrm, 0 },
1269 { X86::VADDSUBPSrr, X86::VADDSUBPSrm, 0 },
1270 { X86::VANDNPDrr, X86::VANDNPDrm, 0 },
1271 { X86::VANDNPSrr, X86::VANDNPSrm, 0 },
1272 { X86::VANDPDrr, X86::VANDPDrm, 0 },
1273 { X86::VANDPSrr, X86::VANDPSrm, 0 },
1274 { X86::VBLENDPDrri, X86::VBLENDPDrmi, 0 },
1275 { X86::VBLENDPSrri, X86::VBLENDPSrmi, 0 },
1276 { X86::VBLENDVPDrr, X86::VBLENDVPDrm, 0 },
1277 { X86::VBLENDVPSrr, X86::VBLENDVPSrm, 0 },
1278 { X86::VCMPPDrri, X86::VCMPPDrmi, 0 },
1279 { X86::VCMPPSrri, X86::VCMPPSrmi, 0 },
1280 { X86::VCMPSDrr, X86::VCMPSDrm, 0 },
1281 { X86::VCMPSSrr, X86::VCMPSSrm, 0 },
1282 { X86::VDIVPDrr, X86::VDIVPDrm, 0 },
1283 { X86::VDIVPSrr, X86::VDIVPSrm, 0 },
1284 { X86::VDIVSDrr, X86::VDIVSDrm, 0 },
1285 { X86::VDIVSDrr_Int, X86::VDIVSDrm_Int, 0 },
1286 { X86::VDIVSSrr, X86::VDIVSSrm, 0 },
1287 { X86::VDIVSSrr_Int, X86::VDIVSSrm_Int, 0 },
1288 { X86::VDPPDrri, X86::VDPPDrmi, 0 },
1289 { X86::VDPPSrri, X86::VDPPSrmi, 0 },
1290 // Do not fold VFs* loads because there are no scalar load variants for
1291 // these instructions. When folded, the load is required to be 128-bits, so
1292 // the load size would not match.
1293 { X86::VFvANDNPDrr, X86::VFvANDNPDrm, 0 },
1294 { X86::VFvANDNPSrr, X86::VFvANDNPSrm, 0 },
1295 { X86::VFvANDPDrr, X86::VFvANDPDrm, 0 },
1296 { X86::VFvANDPSrr, X86::VFvANDPSrm, 0 },
1297 { X86::VFvORPDrr, X86::VFvORPDrm, 0 },
1298 { X86::VFvORPSrr, X86::VFvORPSrm, 0 },
1299 { X86::VFvXORPDrr, X86::VFvXORPDrm, 0 },
1300 { X86::VFvXORPSrr, X86::VFvXORPSrm, 0 },
1301 { X86::VHADDPDrr, X86::VHADDPDrm, 0 },
1302 { X86::VHADDPSrr, X86::VHADDPSrm, 0 },
1303 { X86::VHSUBPDrr, X86::VHSUBPDrm, 0 },
1304 { X86::VHSUBPSrr, X86::VHSUBPSrm, 0 },
1305 { X86::Int_VCMPSDrr, X86::Int_VCMPSDrm, 0 },
1306 { X86::Int_VCMPSSrr, X86::Int_VCMPSSrm, 0 },
1307 { X86::VMAXPDrr, X86::VMAXPDrm, 0 },
1308 { X86::VMAXPSrr, X86::VMAXPSrm, 0 },
1309 { X86::VMAXSDrr, X86::VMAXSDrm, 0 },
1310 { X86::VMAXSDrr_Int, X86::VMAXSDrm_Int, 0 },
1311 { X86::VMAXSSrr, X86::VMAXSSrm, 0 },
1312 { X86::VMAXSSrr_Int, X86::VMAXSSrm_Int, 0 },
1313 { X86::VMINPDrr, X86::VMINPDrm, 0 },
1314 { X86::VMINPSrr, X86::VMINPSrm, 0 },
1315 { X86::VMINSDrr, X86::VMINSDrm, 0 },
1316 { X86::VMINSDrr_Int, X86::VMINSDrm_Int, 0 },
1317 { X86::VMINSSrr, X86::VMINSSrm, 0 },
1318 { X86::VMINSSrr_Int, X86::VMINSSrm_Int, 0 },
1319 { X86::VMOVLHPSrr, X86::VMOVHPSrm, TB_NO_REVERSE },
1320 { X86::VMPSADBWrri, X86::VMPSADBWrmi, 0 },
1321 { X86::VMULPDrr, X86::VMULPDrm, 0 },
1322 { X86::VMULPSrr, X86::VMULPSrm, 0 },
1323 { X86::VMULSDrr, X86::VMULSDrm, 0 },
1324 { X86::VMULSDrr_Int, X86::VMULSDrm_Int, 0 },
1325 { X86::VMULSSrr, X86::VMULSSrm, 0 },
1326 { X86::VMULSSrr_Int, X86::VMULSSrm_Int, 0 },
1327 { X86::VORPDrr, X86::VORPDrm, 0 },
1328 { X86::VORPSrr, X86::VORPSrm, 0 },
1329 { X86::VPACKSSDWrr, X86::VPACKSSDWrm, 0 },
1330 { X86::VPACKSSWBrr, X86::VPACKSSWBrm, 0 },
1331 { X86::VPACKUSDWrr, X86::VPACKUSDWrm, 0 },
1332 { X86::VPACKUSWBrr, X86::VPACKUSWBrm, 0 },
1333 { X86::VPADDBrr, X86::VPADDBrm, 0 },
1334 { X86::VPADDDrr, X86::VPADDDrm, 0 },
1335 { X86::VPADDQrr, X86::VPADDQrm, 0 },
1336 { X86::VPADDSBrr, X86::VPADDSBrm, 0 },
1337 { X86::VPADDSWrr, X86::VPADDSWrm, 0 },
1338 { X86::VPADDUSBrr, X86::VPADDUSBrm, 0 },
1339 { X86::VPADDUSWrr, X86::VPADDUSWrm, 0 },
1340 { X86::VPADDWrr, X86::VPADDWrm, 0 },
1341 { X86::VPALIGNRrri, X86::VPALIGNRrmi, 0 },
1342 { X86::VPANDNrr, X86::VPANDNrm, 0 },
1343 { X86::VPANDrr, X86::VPANDrm, 0 },
1344 { X86::VPAVGBrr, X86::VPAVGBrm, 0 },
1345 { X86::VPAVGWrr, X86::VPAVGWrm, 0 },
1346 { X86::VPBLENDVBrr, X86::VPBLENDVBrm, 0 },
1347 { X86::VPBLENDWrri, X86::VPBLENDWrmi, 0 },
1348 { X86::VPCLMULQDQrr, X86::VPCLMULQDQrm, 0 },
1349 { X86::VPCMPEQBrr, X86::VPCMPEQBrm, 0 },
1350 { X86::VPCMPEQDrr, X86::VPCMPEQDrm, 0 },
1351 { X86::VPCMPEQQrr, X86::VPCMPEQQrm, 0 },
1352 { X86::VPCMPEQWrr, X86::VPCMPEQWrm, 0 },
1353 { X86::VPCMPGTBrr, X86::VPCMPGTBrm, 0 },
1354 { X86::VPCMPGTDrr, X86::VPCMPGTDrm, 0 },
1355 { X86::VPCMPGTQrr, X86::VPCMPGTQrm, 0 },
1356 { X86::VPCMPGTWrr, X86::VPCMPGTWrm, 0 },
1357 { X86::VPHADDDrr, X86::VPHADDDrm, 0 },
1358 { X86::VPHADDSWrr128, X86::VPHADDSWrm128, 0 },
1359 { X86::VPHADDWrr, X86::VPHADDWrm, 0 },
1360 { X86::VPHSUBDrr, X86::VPHSUBDrm, 0 },
1361 { X86::VPHSUBSWrr128, X86::VPHSUBSWrm128, 0 },
1362 { X86::VPHSUBWrr, X86::VPHSUBWrm, 0 },
1363 { X86::VPERMILPDrr, X86::VPERMILPDrm, 0 },
1364 { X86::VPERMILPSrr, X86::VPERMILPSrm, 0 },
1365 { X86::VPINSRBrr, X86::VPINSRBrm, 0 },
1366 { X86::VPINSRDrr, X86::VPINSRDrm, 0 },
1367 { X86::VPINSRQrr, X86::VPINSRQrm, 0 },
1368 { X86::VPINSRWrri, X86::VPINSRWrmi, 0 },
1369 { X86::VPMADDUBSWrr128, X86::VPMADDUBSWrm128, 0 },
1370 { X86::VPMADDWDrr, X86::VPMADDWDrm, 0 },
1371 { X86::VPMAXSWrr, X86::VPMAXSWrm, 0 },
1372 { X86::VPMAXUBrr, X86::VPMAXUBrm, 0 },
1373 { X86::VPMINSWrr, X86::VPMINSWrm, 0 },
1374 { X86::VPMINUBrr, X86::VPMINUBrm, 0 },
1375 { X86::VPMINSBrr, X86::VPMINSBrm, 0 },
1376 { X86::VPMINSDrr, X86::VPMINSDrm, 0 },
1377 { X86::VPMINUDrr, X86::VPMINUDrm, 0 },
1378 { X86::VPMINUWrr, X86::VPMINUWrm, 0 },
1379 { X86::VPMAXSBrr, X86::VPMAXSBrm, 0 },
1380 { X86::VPMAXSDrr, X86::VPMAXSDrm, 0 },
1381 { X86::VPMAXUDrr, X86::VPMAXUDrm, 0 },
1382 { X86::VPMAXUWrr, X86::VPMAXUWrm, 0 },
1383 { X86::VPMULDQrr, X86::VPMULDQrm, 0 },
1384 { X86::VPMULHRSWrr128, X86::VPMULHRSWrm128, 0 },
1385 { X86::VPMULHUWrr, X86::VPMULHUWrm, 0 },
1386 { X86::VPMULHWrr, X86::VPMULHWrm, 0 },
1387 { X86::VPMULLDrr, X86::VPMULLDrm, 0 },
1388 { X86::VPMULLWrr, X86::VPMULLWrm, 0 },
1389 { X86::VPMULUDQrr, X86::VPMULUDQrm, 0 },
1390 { X86::VPORrr, X86::VPORrm, 0 },
1391 { X86::VPSADBWrr, X86::VPSADBWrm, 0 },
1392 { X86::VPSHUFBrr, X86::VPSHUFBrm, 0 },
1393 { X86::VPSIGNBrr128, X86::VPSIGNBrm128, 0 },
1394 { X86::VPSIGNWrr128, X86::VPSIGNWrm128, 0 },
1395 { X86::VPSIGNDrr128, X86::VPSIGNDrm128, 0 },
1396 { X86::VPSLLDrr, X86::VPSLLDrm, 0 },
1397 { X86::VPSLLQrr, X86::VPSLLQrm, 0 },
1398 { X86::VPSLLWrr, X86::VPSLLWrm, 0 },
1399 { X86::VPSRADrr, X86::VPSRADrm, 0 },
1400 { X86::VPSRAWrr, X86::VPSRAWrm, 0 },
1401 { X86::VPSRLDrr, X86::VPSRLDrm, 0 },
1402 { X86::VPSRLQrr, X86::VPSRLQrm, 0 },
1403 { X86::VPSRLWrr, X86::VPSRLWrm, 0 },
1404 { X86::VPSUBBrr, X86::VPSUBBrm, 0 },
1405 { X86::VPSUBDrr, X86::VPSUBDrm, 0 },
1406 { X86::VPSUBQrr, X86::VPSUBQrm, 0 },
1407 { X86::VPSUBSBrr, X86::VPSUBSBrm, 0 },
1408 { X86::VPSUBSWrr, X86::VPSUBSWrm, 0 },
1409 { X86::VPSUBUSBrr, X86::VPSUBUSBrm, 0 },
1410 { X86::VPSUBUSWrr, X86::VPSUBUSWrm, 0 },
1411 { X86::VPSUBWrr, X86::VPSUBWrm, 0 },
1412 { X86::VPUNPCKHBWrr, X86::VPUNPCKHBWrm, 0 },
1413 { X86::VPUNPCKHDQrr, X86::VPUNPCKHDQrm, 0 },
1414 { X86::VPUNPCKHQDQrr, X86::VPUNPCKHQDQrm, 0 },
1415 { X86::VPUNPCKHWDrr, X86::VPUNPCKHWDrm, 0 },
1416 { X86::VPUNPCKLBWrr, X86::VPUNPCKLBWrm, 0 },
1417 { X86::VPUNPCKLDQrr, X86::VPUNPCKLDQrm, 0 },
1418 { X86::VPUNPCKLQDQrr, X86::VPUNPCKLQDQrm, 0 },
1419 { X86::VPUNPCKLWDrr, X86::VPUNPCKLWDrm, 0 },
1420 { X86::VPXORrr, X86::VPXORrm, 0 },
1421 { X86::VROUNDSDr, X86::VROUNDSDm, 0 },
1422 { X86::VROUNDSSr, X86::VROUNDSSm, 0 },
1423 { X86::VSHUFPDrri, X86::VSHUFPDrmi, 0 },
1424 { X86::VSHUFPSrri, X86::VSHUFPSrmi, 0 },
1425 { X86::VSUBPDrr, X86::VSUBPDrm, 0 },
1426 { X86::VSUBPSrr, X86::VSUBPSrm, 0 },
1427 { X86::VSUBSDrr, X86::VSUBSDrm, 0 },
1428 { X86::VSUBSDrr_Int, X86::VSUBSDrm_Int, 0 },
1429 { X86::VSUBSSrr, X86::VSUBSSrm, 0 },
1430 { X86::VSUBSSrr_Int, X86::VSUBSSrm_Int, 0 },
1431 { X86::VUNPCKHPDrr, X86::VUNPCKHPDrm, 0 },
1432 { X86::VUNPCKHPSrr, X86::VUNPCKHPSrm, 0 },
1433 { X86::VUNPCKLPDrr, X86::VUNPCKLPDrm, 0 },
1434 { X86::VUNPCKLPSrr, X86::VUNPCKLPSrm, 0 },
1435 { X86::VXORPDrr, X86::VXORPDrm, 0 },
1436 { X86::VXORPSrr, X86::VXORPSrm, 0 },
1437
1438 // AVX 256-bit foldable instructions
1439 { X86::VADDPDYrr, X86::VADDPDYrm, 0 },
1440 { X86::VADDPSYrr, X86::VADDPSYrm, 0 },
1441 { X86::VADDSUBPDYrr, X86::VADDSUBPDYrm, 0 },
1442 { X86::VADDSUBPSYrr, X86::VADDSUBPSYrm, 0 },
1443 { X86::VANDNPDYrr, X86::VANDNPDYrm, 0 },
1444 { X86::VANDNPSYrr, X86::VANDNPSYrm, 0 },
1445 { X86::VANDPDYrr, X86::VANDPDYrm, 0 },
1446 { X86::VANDPSYrr, X86::VANDPSYrm, 0 },
1447 { X86::VBLENDPDYrri, X86::VBLENDPDYrmi, 0 },
1448 { X86::VBLENDPSYrri, X86::VBLENDPSYrmi, 0 },
1449 { X86::VBLENDVPDYrr, X86::VBLENDVPDYrm, 0 },
1450 { X86::VBLENDVPSYrr, X86::VBLENDVPSYrm, 0 },
1451 { X86::VCMPPDYrri, X86::VCMPPDYrmi, 0 },
1452 { X86::VCMPPSYrri, X86::VCMPPSYrmi, 0 },
1453 { X86::VDIVPDYrr, X86::VDIVPDYrm, 0 },
1454 { X86::VDIVPSYrr, X86::VDIVPSYrm, 0 },
1455 { X86::VDPPSYrri, X86::VDPPSYrmi, 0 },
1456 { X86::VHADDPDYrr, X86::VHADDPDYrm, 0 },
1457 { X86::VHADDPSYrr, X86::VHADDPSYrm, 0 },
1458 { X86::VHSUBPDYrr, X86::VHSUBPDYrm, 0 },
1459 { X86::VHSUBPSYrr, X86::VHSUBPSYrm, 0 },
1460 { X86::VINSERTF128rr, X86::VINSERTF128rm, 0 },
1461 { X86::VMAXPDYrr, X86::VMAXPDYrm, 0 },
1462 { X86::VMAXPSYrr, X86::VMAXPSYrm, 0 },
1463 { X86::VMINPDYrr, X86::VMINPDYrm, 0 },
1464 { X86::VMINPSYrr, X86::VMINPSYrm, 0 },
1465 { X86::VMULPDYrr, X86::VMULPDYrm, 0 },
1466 { X86::VMULPSYrr, X86::VMULPSYrm, 0 },
1467 { X86::VORPDYrr, X86::VORPDYrm, 0 },
1468 { X86::VORPSYrr, X86::VORPSYrm, 0 },
1469 { X86::VPERM2F128rr, X86::VPERM2F128rm, 0 },
1470 { X86::VPERMILPDYrr, X86::VPERMILPDYrm, 0 },
1471 { X86::VPERMILPSYrr, X86::VPERMILPSYrm, 0 },
1472 { X86::VSHUFPDYrri, X86::VSHUFPDYrmi, 0 },
1473 { X86::VSHUFPSYrri, X86::VSHUFPSYrmi, 0 },
1474 { X86::VSUBPDYrr, X86::VSUBPDYrm, 0 },
1475 { X86::VSUBPSYrr, X86::VSUBPSYrm, 0 },
1476 { X86::VUNPCKHPDYrr, X86::VUNPCKHPDYrm, 0 },
1477 { X86::VUNPCKHPSYrr, X86::VUNPCKHPSYrm, 0 },
1478 { X86::VUNPCKLPDYrr, X86::VUNPCKLPDYrm, 0 },
1479 { X86::VUNPCKLPSYrr, X86::VUNPCKLPSYrm, 0 },
1480 { X86::VXORPDYrr, X86::VXORPDYrm, 0 },
1481 { X86::VXORPSYrr, X86::VXORPSYrm, 0 },
1482
1483 // AVX2 foldable instructions
1484 { X86::VINSERTI128rr, X86::VINSERTI128rm, 0 },
1485 { X86::VPACKSSDWYrr, X86::VPACKSSDWYrm, 0 },
1486 { X86::VPACKSSWBYrr, X86::VPACKSSWBYrm, 0 },
1487 { X86::VPACKUSDWYrr, X86::VPACKUSDWYrm, 0 },
1488 { X86::VPACKUSWBYrr, X86::VPACKUSWBYrm, 0 },
1489 { X86::VPADDBYrr, X86::VPADDBYrm, 0 },
1490 { X86::VPADDDYrr, X86::VPADDDYrm, 0 },
1491 { X86::VPADDQYrr, X86::VPADDQYrm, 0 },
1492 { X86::VPADDSBYrr, X86::VPADDSBYrm, 0 },
1493 { X86::VPADDSWYrr, X86::VPADDSWYrm, 0 },
1494 { X86::VPADDUSBYrr, X86::VPADDUSBYrm, 0 },
1495 { X86::VPADDUSWYrr, X86::VPADDUSWYrm, 0 },
1496 { X86::VPADDWYrr, X86::VPADDWYrm, 0 },
1497 { X86::VPALIGNRYrri, X86::VPALIGNRYrmi, 0 },
1498 { X86::VPANDNYrr, X86::VPANDNYrm, 0 },
1499 { X86::VPANDYrr, X86::VPANDYrm, 0 },
1500 { X86::VPAVGBYrr, X86::VPAVGBYrm, 0 },
1501 { X86::VPAVGWYrr, X86::VPAVGWYrm, 0 },
1502 { X86::VPBLENDDrri, X86::VPBLENDDrmi, 0 },
1503 { X86::VPBLENDDYrri, X86::VPBLENDDYrmi, 0 },
1504 { X86::VPBLENDVBYrr, X86::VPBLENDVBYrm, 0 },
1505 { X86::VPBLENDWYrri, X86::VPBLENDWYrmi, 0 },
1506 { X86::VPCMPEQBYrr, X86::VPCMPEQBYrm, 0 },
1507 { X86::VPCMPEQDYrr, X86::VPCMPEQDYrm, 0 },
1508 { X86::VPCMPEQQYrr, X86::VPCMPEQQYrm, 0 },
1509 { X86::VPCMPEQWYrr, X86::VPCMPEQWYrm, 0 },
1510 { X86::VPCMPGTBYrr, X86::VPCMPGTBYrm, 0 },
1511 { X86::VPCMPGTDYrr, X86::VPCMPGTDYrm, 0 },
1512 { X86::VPCMPGTQYrr, X86::VPCMPGTQYrm, 0 },
1513 { X86::VPCMPGTWYrr, X86::VPCMPGTWYrm, 0 },
1514 { X86::VPERM2I128rr, X86::VPERM2I128rm, 0 },
1515 { X86::VPERMDYrr, X86::VPERMDYrm, 0 },
1516 { X86::VPERMPSYrr, X86::VPERMPSYrm, 0 },
1517 { X86::VPHADDDYrr, X86::VPHADDDYrm, 0 },
1518 { X86::VPHADDSWrr256, X86::VPHADDSWrm256, 0 },
1519 { X86::VPHADDWYrr, X86::VPHADDWYrm, 0 },
1520 { X86::VPHSUBDYrr, X86::VPHSUBDYrm, 0 },
1521 { X86::VPHSUBSWrr256, X86::VPHSUBSWrm256, 0 },
1522 { X86::VPHSUBWYrr, X86::VPHSUBWYrm, 0 },
1523 { X86::VPMADDUBSWrr256, X86::VPMADDUBSWrm256, 0 },
1524 { X86::VPMADDWDYrr, X86::VPMADDWDYrm, 0 },
1525 { X86::VPMAXSWYrr, X86::VPMAXSWYrm, 0 },
1526 { X86::VPMAXUBYrr, X86::VPMAXUBYrm, 0 },
1527 { X86::VPMINSWYrr, X86::VPMINSWYrm, 0 },
1528 { X86::VPMINUBYrr, X86::VPMINUBYrm, 0 },
1529 { X86::VPMINSBYrr, X86::VPMINSBYrm, 0 },
1530 { X86::VPMINSDYrr, X86::VPMINSDYrm, 0 },
1531 { X86::VPMINUDYrr, X86::VPMINUDYrm, 0 },
1532 { X86::VPMINUWYrr, X86::VPMINUWYrm, 0 },
1533 { X86::VPMAXSBYrr, X86::VPMAXSBYrm, 0 },
1534 { X86::VPMAXSDYrr, X86::VPMAXSDYrm, 0 },
1535 { X86::VPMAXUDYrr, X86::VPMAXUDYrm, 0 },
1536 { X86::VPMAXUWYrr, X86::VPMAXUWYrm, 0 },
1537 { X86::VMPSADBWYrri, X86::VMPSADBWYrmi, 0 },
1538 { X86::VPMULDQYrr, X86::VPMULDQYrm, 0 },
1539 { X86::VPMULHRSWrr256, X86::VPMULHRSWrm256, 0 },
1540 { X86::VPMULHUWYrr, X86::VPMULHUWYrm, 0 },
1541 { X86::VPMULHWYrr, X86::VPMULHWYrm, 0 },
1542 { X86::VPMULLDYrr, X86::VPMULLDYrm, 0 },
1543 { X86::VPMULLWYrr, X86::VPMULLWYrm, 0 },
1544 { X86::VPMULUDQYrr, X86::VPMULUDQYrm, 0 },
1545 { X86::VPORYrr, X86::VPORYrm, 0 },
1546 { X86::VPSADBWYrr, X86::VPSADBWYrm, 0 },
1547 { X86::VPSHUFBYrr, X86::VPSHUFBYrm, 0 },
1548 { X86::VPSIGNBYrr256, X86::VPSIGNBYrm256, 0 },
1549 { X86::VPSIGNWYrr256, X86::VPSIGNWYrm256, 0 },
1550 { X86::VPSIGNDYrr256, X86::VPSIGNDYrm256, 0 },
1551 { X86::VPSLLDYrr, X86::VPSLLDYrm, 0 },
1552 { X86::VPSLLQYrr, X86::VPSLLQYrm, 0 },
1553 { X86::VPSLLWYrr, X86::VPSLLWYrm, 0 },
1554 { X86::VPSLLVDrr, X86::VPSLLVDrm, 0 },
1555 { X86::VPSLLVDYrr, X86::VPSLLVDYrm, 0 },
1556 { X86::VPSLLVQrr, X86::VPSLLVQrm, 0 },
1557 { X86::VPSLLVQYrr, X86::VPSLLVQYrm, 0 },
1558 { X86::VPSRADYrr, X86::VPSRADYrm, 0 },
1559 { X86::VPSRAWYrr, X86::VPSRAWYrm, 0 },
1560 { X86::VPSRAVDrr, X86::VPSRAVDrm, 0 },
1561 { X86::VPSRAVDYrr, X86::VPSRAVDYrm, 0 },
1562 { X86::VPSRAVD_Intrr, X86::VPSRAVD_Intrm, 0 },
1563 { X86::VPSRAVD_IntYrr, X86::VPSRAVD_IntYrm, 0 },
1564 { X86::VPSRLDYrr, X86::VPSRLDYrm, 0 },
1565 { X86::VPSRLQYrr, X86::VPSRLQYrm, 0 },
1566 { X86::VPSRLWYrr, X86::VPSRLWYrm, 0 },
1567 { X86::VPSRLVDrr, X86::VPSRLVDrm, 0 },
1568 { X86::VPSRLVDYrr, X86::VPSRLVDYrm, 0 },
1569 { X86::VPSRLVQrr, X86::VPSRLVQrm, 0 },
1570 { X86::VPSRLVQYrr, X86::VPSRLVQYrm, 0 },
1571 { X86::VPSUBBYrr, X86::VPSUBBYrm, 0 },
1572 { X86::VPSUBDYrr, X86::VPSUBDYrm, 0 },
1573 { X86::VPSUBQYrr, X86::VPSUBQYrm, 0 },
1574 { X86::VPSUBSBYrr, X86::VPSUBSBYrm, 0 },
1575 { X86::VPSUBSWYrr, X86::VPSUBSWYrm, 0 },
1576 { X86::VPSUBUSBYrr, X86::VPSUBUSBYrm, 0 },
1577 { X86::VPSUBUSWYrr, X86::VPSUBUSWYrm, 0 },
1578 { X86::VPSUBWYrr, X86::VPSUBWYrm, 0 },
1579 { X86::VPUNPCKHBWYrr, X86::VPUNPCKHBWYrm, 0 },
1580 { X86::VPUNPCKHDQYrr, X86::VPUNPCKHDQYrm, 0 },
1581 { X86::VPUNPCKHQDQYrr, X86::VPUNPCKHQDQYrm, 0 },
1582 { X86::VPUNPCKHWDYrr, X86::VPUNPCKHWDYrm, 0 },
1583 { X86::VPUNPCKLBWYrr, X86::VPUNPCKLBWYrm, 0 },
1584 { X86::VPUNPCKLDQYrr, X86::VPUNPCKLDQYrm, 0 },
1585 { X86::VPUNPCKLQDQYrr, X86::VPUNPCKLQDQYrm, 0 },
1586 { X86::VPUNPCKLWDYrr, X86::VPUNPCKLWDYrm, 0 },
1587 { X86::VPXORYrr, X86::VPXORYrm, 0 },
1588
1589 // FMA4 foldable patterns
1590 { X86::VFMADDSS4rr, X86::VFMADDSS4mr, TB_ALIGN_NONE },
1591 { X86::VFMADDSD4rr, X86::VFMADDSD4mr, TB_ALIGN_NONE },
1592 { X86::VFMADDPS4rr, X86::VFMADDPS4mr, TB_ALIGN_NONE },
1593 { X86::VFMADDPD4rr, X86::VFMADDPD4mr, TB_ALIGN_NONE },
1594 { X86::VFMADDPS4rrY, X86::VFMADDPS4mrY, TB_ALIGN_NONE },
1595 { X86::VFMADDPD4rrY, X86::VFMADDPD4mrY, TB_ALIGN_NONE },
1596 { X86::VFNMADDSS4rr, X86::VFNMADDSS4mr, TB_ALIGN_NONE },
1597 { X86::VFNMADDSD4rr, X86::VFNMADDSD4mr, TB_ALIGN_NONE },
1598 { X86::VFNMADDPS4rr, X86::VFNMADDPS4mr, TB_ALIGN_NONE },
1599 { X86::VFNMADDPD4rr, X86::VFNMADDPD4mr, TB_ALIGN_NONE },
1600 { X86::VFNMADDPS4rrY, X86::VFNMADDPS4mrY, TB_ALIGN_NONE },
1601 { X86::VFNMADDPD4rrY, X86::VFNMADDPD4mrY, TB_ALIGN_NONE },
1602 { X86::VFMSUBSS4rr, X86::VFMSUBSS4mr, TB_ALIGN_NONE },
1603 { X86::VFMSUBSD4rr, X86::VFMSUBSD4mr, TB_ALIGN_NONE },
1604 { X86::VFMSUBPS4rr, X86::VFMSUBPS4mr, TB_ALIGN_NONE },
1605 { X86::VFMSUBPD4rr, X86::VFMSUBPD4mr, TB_ALIGN_NONE },
1606 { X86::VFMSUBPS4rrY, X86::VFMSUBPS4mrY, TB_ALIGN_NONE },
1607 { X86::VFMSUBPD4rrY, X86::VFMSUBPD4mrY, TB_ALIGN_NONE },
1608 { X86::VFNMSUBSS4rr, X86::VFNMSUBSS4mr, TB_ALIGN_NONE },
1609 { X86::VFNMSUBSD4rr, X86::VFNMSUBSD4mr, TB_ALIGN_NONE },
1610 { X86::VFNMSUBPS4rr, X86::VFNMSUBPS4mr, TB_ALIGN_NONE },
1611 { X86::VFNMSUBPD4rr, X86::VFNMSUBPD4mr, TB_ALIGN_NONE },
1612 { X86::VFNMSUBPS4rrY, X86::VFNMSUBPS4mrY, TB_ALIGN_NONE },
1613 { X86::VFNMSUBPD4rrY, X86::VFNMSUBPD4mrY, TB_ALIGN_NONE },
1614 { X86::VFMADDSUBPS4rr, X86::VFMADDSUBPS4mr, TB_ALIGN_NONE },
1615 { X86::VFMADDSUBPD4rr, X86::VFMADDSUBPD4mr, TB_ALIGN_NONE },
1616 { X86::VFMADDSUBPS4rrY, X86::VFMADDSUBPS4mrY, TB_ALIGN_NONE },
1617 { X86::VFMADDSUBPD4rrY, X86::VFMADDSUBPD4mrY, TB_ALIGN_NONE },
1618 { X86::VFMSUBADDPS4rr, X86::VFMSUBADDPS4mr, TB_ALIGN_NONE },
1619 { X86::VFMSUBADDPD4rr, X86::VFMSUBADDPD4mr, TB_ALIGN_NONE },
1620 { X86::VFMSUBADDPS4rrY, X86::VFMSUBADDPS4mrY, TB_ALIGN_NONE },
1621 { X86::VFMSUBADDPD4rrY, X86::VFMSUBADDPD4mrY, TB_ALIGN_NONE },
1622
1623 // XOP foldable instructions
1624 { X86::VPCMOVrrr, X86::VPCMOVrmr, 0 },
1625 { X86::VPCMOVrrrY, X86::VPCMOVrmrY, 0 },
1626 { X86::VPCOMBri, X86::VPCOMBmi, 0 },
1627 { X86::VPCOMDri, X86::VPCOMDmi, 0 },
1628 { X86::VPCOMQri, X86::VPCOMQmi, 0 },
1629 { X86::VPCOMWri, X86::VPCOMWmi, 0 },
1630 { X86::VPCOMUBri, X86::VPCOMUBmi, 0 },
1631 { X86::VPCOMUDri, X86::VPCOMUDmi, 0 },
1632 { X86::VPCOMUQri, X86::VPCOMUQmi, 0 },
1633 { X86::VPCOMUWri, X86::VPCOMUWmi, 0 },
1634 { X86::VPERMIL2PDrr, X86::VPERMIL2PDmr, 0 },
1635 { X86::VPERMIL2PDrrY, X86::VPERMIL2PDmrY, 0 },
1636 { X86::VPERMIL2PSrr, X86::VPERMIL2PSmr, 0 },
1637 { X86::VPERMIL2PSrrY, X86::VPERMIL2PSmrY, 0 },
1638 { X86::VPMACSDDrr, X86::VPMACSDDrm, 0 },
1639 { X86::VPMACSDQHrr, X86::VPMACSDQHrm, 0 },
1640 { X86::VPMACSDQLrr, X86::VPMACSDQLrm, 0 },
1641 { X86::VPMACSSDDrr, X86::VPMACSSDDrm, 0 },
1642 { X86::VPMACSSDQHrr, X86::VPMACSSDQHrm, 0 },
1643 { X86::VPMACSSDQLrr, X86::VPMACSSDQLrm, 0 },
1644 { X86::VPMACSSWDrr, X86::VPMACSSWDrm, 0 },
1645 { X86::VPMACSSWWrr, X86::VPMACSSWWrm, 0 },
1646 { X86::VPMACSWDrr, X86::VPMACSWDrm, 0 },
1647 { X86::VPMACSWWrr, X86::VPMACSWWrm, 0 },
1648 { X86::VPMADCSSWDrr, X86::VPMADCSSWDrm, 0 },
1649 { X86::VPMADCSWDrr, X86::VPMADCSWDrm, 0 },
1650 { X86::VPPERMrrr, X86::VPPERMrmr, 0 },
1651 { X86::VPROTBrr, X86::VPROTBrm, 0 },
1652 { X86::VPROTDrr, X86::VPROTDrm, 0 },
1653 { X86::VPROTQrr, X86::VPROTQrm, 0 },
1654 { X86::VPROTWrr, X86::VPROTWrm, 0 },
1655 { X86::VPSHABrr, X86::VPSHABrm, 0 },
1656 { X86::VPSHADrr, X86::VPSHADrm, 0 },
1657 { X86::VPSHAQrr, X86::VPSHAQrm, 0 },
1658 { X86::VPSHAWrr, X86::VPSHAWrm, 0 },
1659 { X86::VPSHLBrr, X86::VPSHLBrm, 0 },
1660 { X86::VPSHLDrr, X86::VPSHLDrm, 0 },
1661 { X86::VPSHLQrr, X86::VPSHLQrm, 0 },
1662 { X86::VPSHLWrr, X86::VPSHLWrm, 0 },
1663
1664 // BMI/BMI2 foldable instructions
1665 { X86::ANDN32rr, X86::ANDN32rm, 0 },
1666 { X86::ANDN64rr, X86::ANDN64rm, 0 },
1667 { X86::MULX32rr, X86::MULX32rm, 0 },
1668 { X86::MULX64rr, X86::MULX64rm, 0 },
1669 { X86::PDEP32rr, X86::PDEP32rm, 0 },
1670 { X86::PDEP64rr, X86::PDEP64rm, 0 },
1671 { X86::PEXT32rr, X86::PEXT32rm, 0 },
1672 { X86::PEXT64rr, X86::PEXT64rm, 0 },
1673
1674 // ADX foldable instructions
1675 { X86::ADCX32rr, X86::ADCX32rm, 0 },
1676 { X86::ADCX64rr, X86::ADCX64rm, 0 },
1677 { X86::ADOX32rr, X86::ADOX32rm, 0 },
1678 { X86::ADOX64rr, X86::ADOX64rm, 0 },
1679
1680 // AVX-512 foldable instructions
1681 { X86::VADDPSZrr, X86::VADDPSZrm, 0 },
1682 { X86::VADDPDZrr, X86::VADDPDZrm, 0 },
1683 { X86::VSUBPSZrr, X86::VSUBPSZrm, 0 },
1684 { X86::VSUBPDZrr, X86::VSUBPDZrm, 0 },
1685 { X86::VMULPSZrr, X86::VMULPSZrm, 0 },
1686 { X86::VMULPDZrr, X86::VMULPDZrm, 0 },
1687 { X86::VDIVPSZrr, X86::VDIVPSZrm, 0 },
1688 { X86::VDIVPDZrr, X86::VDIVPDZrm, 0 },
1689 { X86::VMINPSZrr, X86::VMINPSZrm, 0 },
1690 { X86::VMINPDZrr, X86::VMINPDZrm, 0 },
1691 { X86::VMAXPSZrr, X86::VMAXPSZrm, 0 },
1692 { X86::VMAXPDZrr, X86::VMAXPDZrm, 0 },
1693 { X86::VPADDDZrr, X86::VPADDDZrm, 0 },
1694 { X86::VPADDQZrr, X86::VPADDQZrm, 0 },
1695 { X86::VPERMPDZri, X86::VPERMPDZmi, 0 },
1696 { X86::VPERMPSZrr, X86::VPERMPSZrm, 0 },
1697 { X86::VPMAXSDZrr, X86::VPMAXSDZrm, 0 },
1698 { X86::VPMAXSQZrr, X86::VPMAXSQZrm, 0 },
1699 { X86::VPMAXUDZrr, X86::VPMAXUDZrm, 0 },
1700 { X86::VPMAXUQZrr, X86::VPMAXUQZrm, 0 },
1701 { X86::VPMINSDZrr, X86::VPMINSDZrm, 0 },
1702 { X86::VPMINSQZrr, X86::VPMINSQZrm, 0 },
1703 { X86::VPMINUDZrr, X86::VPMINUDZrm, 0 },
1704 { X86::VPMINUQZrr, X86::VPMINUQZrm, 0 },
1705 { X86::VPMULDQZrr, X86::VPMULDQZrm, 0 },
1706 { X86::VPSLLVDZrr, X86::VPSLLVDZrm, 0 },
1707 { X86::VPSLLVQZrr, X86::VPSLLVQZrm, 0 },
1708 { X86::VPSRAVDZrr, X86::VPSRAVDZrm, 0 },
1709 { X86::VPSRLVDZrr, X86::VPSRLVDZrm, 0 },
1710 { X86::VPSRLVQZrr, X86::VPSRLVQZrm, 0 },
1711 { X86::VPSUBDZrr, X86::VPSUBDZrm, 0 },
1712 { X86::VPSUBQZrr, X86::VPSUBQZrm, 0 },
1713 { X86::VSHUFPDZrri, X86::VSHUFPDZrmi, 0 },
1714 { X86::VSHUFPSZrri, X86::VSHUFPSZrmi, 0 },
1715 { X86::VALIGNQZrri, X86::VALIGNQZrmi, 0 },
1716 { X86::VALIGNDZrri, X86::VALIGNDZrmi, 0 },
1717 { X86::VPMULUDQZrr, X86::VPMULUDQZrm, 0 },
1718 { X86::VBROADCASTSSZrkz, X86::VBROADCASTSSZmkz, TB_NO_REVERSE },
1719 { X86::VBROADCASTSDZrkz, X86::VBROADCASTSDZmkz, TB_NO_REVERSE },
1720
1721 // AVX-512{F,VL} foldable instructions
1722 { X86::VBROADCASTSSZ256rkz, X86::VBROADCASTSSZ256mkz, TB_NO_REVERSE },
1723 { X86::VBROADCASTSDZ256rkz, X86::VBROADCASTSDZ256mkz, TB_NO_REVERSE },
1724 { X86::VBROADCASTSSZ128rkz, X86::VBROADCASTSSZ128mkz, TB_NO_REVERSE },
1725
1726 // AVX-512{F,VL} foldable instructions
1727 { X86::VADDPDZ128rr, X86::VADDPDZ128rm, 0 },
1728 { X86::VADDPDZ256rr, X86::VADDPDZ256rm, 0 },
1729 { X86::VADDPSZ128rr, X86::VADDPSZ128rm, 0 },
1730 { X86::VADDPSZ256rr, X86::VADDPSZ256rm, 0 },
1731
1732 // AES foldable instructions
1733 { X86::AESDECLASTrr, X86::AESDECLASTrm, TB_ALIGN_16 },
1734 { X86::AESDECrr, X86::AESDECrm, TB_ALIGN_16 },
1735 { X86::AESENCLASTrr, X86::AESENCLASTrm, TB_ALIGN_16 },
1736 { X86::AESENCrr, X86::AESENCrm, TB_ALIGN_16 },
1737 { X86::VAESDECLASTrr, X86::VAESDECLASTrm, 0 },
1738 { X86::VAESDECrr, X86::VAESDECrm, 0 },
1739 { X86::VAESENCLASTrr, X86::VAESENCLASTrm, 0 },
1740 { X86::VAESENCrr, X86::VAESENCrm, 0 },
1741
1742 // SHA foldable instructions
1743 { X86::SHA1MSG1rr, X86::SHA1MSG1rm, TB_ALIGN_16 },
1744 { X86::SHA1MSG2rr, X86::SHA1MSG2rm, TB_ALIGN_16 },
1745 { X86::SHA1NEXTErr, X86::SHA1NEXTErm, TB_ALIGN_16 },
1746 { X86::SHA1RNDS4rri, X86::SHA1RNDS4rmi, TB_ALIGN_16 },
1747 { X86::SHA256MSG1rr, X86::SHA256MSG1rm, TB_ALIGN_16 },
1748 { X86::SHA256MSG2rr, X86::SHA256MSG2rm, TB_ALIGN_16 },
1749 { X86::SHA256RNDS2rr, X86::SHA256RNDS2rm, TB_ALIGN_16 }
1750 };
1751
1752 for (X86MemoryFoldTableEntry Entry : MemoryFoldTable2) {
1753 AddTableEntry(RegOp2MemOpTable2, MemOp2RegOpTable,
1754 Entry.RegOp, Entry.MemOp,
1755 // Index 2, folded load
1756 Entry.Flags | TB_INDEX_2 | TB_FOLDED_LOAD);
1757 }
1758
1759 static const X86MemoryFoldTableEntry MemoryFoldTable3[] = {
1760 // FMA foldable instructions
1761 { X86::VFMADDSSr231r, X86::VFMADDSSr231m, TB_ALIGN_NONE },
1762 { X86::VFMADDSSr231r_Int, X86::VFMADDSSr231m_Int, TB_ALIGN_NONE },
1763 { X86::VFMADDSDr231r, X86::VFMADDSDr231m, TB_ALIGN_NONE },
1764 { X86::VFMADDSDr231r_Int, X86::VFMADDSDr231m_Int, TB_ALIGN_NONE },
1765 { X86::VFMADDSSr132r, X86::VFMADDSSr132m, TB_ALIGN_NONE },
1766 { X86::VFMADDSSr132r_Int, X86::VFMADDSSr132m_Int, TB_ALIGN_NONE },
1767 { X86::VFMADDSDr132r, X86::VFMADDSDr132m, TB_ALIGN_NONE },
1768 { X86::VFMADDSDr132r_Int, X86::VFMADDSDr132m_Int, TB_ALIGN_NONE },
1769 { X86::VFMADDSSr213r, X86::VFMADDSSr213m, TB_ALIGN_NONE },
1770 { X86::VFMADDSSr213r_Int, X86::VFMADDSSr213m_Int, TB_ALIGN_NONE },
1771 { X86::VFMADDSDr213r, X86::VFMADDSDr213m, TB_ALIGN_NONE },
1772 { X86::VFMADDSDr213r_Int, X86::VFMADDSDr213m_Int, TB_ALIGN_NONE },
1773
1774 { X86::VFMADDPSr231r, X86::VFMADDPSr231m, TB_ALIGN_NONE },
1775 { X86::VFMADDPDr231r, X86::VFMADDPDr231m, TB_ALIGN_NONE },
1776 { X86::VFMADDPSr132r, X86::VFMADDPSr132m, TB_ALIGN_NONE },
1777 { X86::VFMADDPDr132r, X86::VFMADDPDr132m, TB_ALIGN_NONE },
1778 { X86::VFMADDPSr213r, X86::VFMADDPSr213m, TB_ALIGN_NONE },
1779 { X86::VFMADDPDr213r, X86::VFMADDPDr213m, TB_ALIGN_NONE },
1780 { X86::VFMADDPSr231rY, X86::VFMADDPSr231mY, TB_ALIGN_NONE },
1781 { X86::VFMADDPDr231rY, X86::VFMADDPDr231mY, TB_ALIGN_NONE },
1782 { X86::VFMADDPSr132rY, X86::VFMADDPSr132mY, TB_ALIGN_NONE },
1783 { X86::VFMADDPDr132rY, X86::VFMADDPDr132mY, TB_ALIGN_NONE },
1784 { X86::VFMADDPSr213rY, X86::VFMADDPSr213mY, TB_ALIGN_NONE },
1785 { X86::VFMADDPDr213rY, X86::VFMADDPDr213mY, TB_ALIGN_NONE },
1786
1787 { X86::VFNMADDSSr231r, X86::VFNMADDSSr231m, TB_ALIGN_NONE },
1788 { X86::VFNMADDSSr231r_Int, X86::VFNMADDSSr231m_Int, TB_ALIGN_NONE },
1789 { X86::VFNMADDSDr231r, X86::VFNMADDSDr231m, TB_ALIGN_NONE },
1790 { X86::VFNMADDSDr231r_Int, X86::VFNMADDSDr231m_Int, TB_ALIGN_NONE },
1791 { X86::VFNMADDSSr132r, X86::VFNMADDSSr132m, TB_ALIGN_NONE },
1792 { X86::VFNMADDSSr132r_Int, X86::VFNMADDSSr132m_Int, TB_ALIGN_NONE },
1793 { X86::VFNMADDSDr132r, X86::VFNMADDSDr132m, TB_ALIGN_NONE },
1794 { X86::VFNMADDSDr132r_Int, X86::VFNMADDSDr132m_Int, TB_ALIGN_NONE },
1795 { X86::VFNMADDSSr213r, X86::VFNMADDSSr213m, TB_ALIGN_NONE },
1796 { X86::VFNMADDSSr213r_Int, X86::VFNMADDSSr213m_Int, TB_ALIGN_NONE },
1797 { X86::VFNMADDSDr213r, X86::VFNMADDSDr213m, TB_ALIGN_NONE },
1798 { X86::VFNMADDSDr213r_Int, X86::VFNMADDSDr213m_Int, TB_ALIGN_NONE },
1799
1800 { X86::VFNMADDPSr231r, X86::VFNMADDPSr231m, TB_ALIGN_NONE },
1801 { X86::VFNMADDPDr231r, X86::VFNMADDPDr231m, TB_ALIGN_NONE },
1802 { X86::VFNMADDPSr132r, X86::VFNMADDPSr132m, TB_ALIGN_NONE },
1803 { X86::VFNMADDPDr132r, X86::VFNMADDPDr132m, TB_ALIGN_NONE },
1804 { X86::VFNMADDPSr213r, X86::VFNMADDPSr213m, TB_ALIGN_NONE },
1805 { X86::VFNMADDPDr213r, X86::VFNMADDPDr213m, TB_ALIGN_NONE },
1806 { X86::VFNMADDPSr231rY, X86::VFNMADDPSr231mY, TB_ALIGN_NONE },
1807 { X86::VFNMADDPDr231rY, X86::VFNMADDPDr231mY, TB_ALIGN_NONE },
1808 { X86::VFNMADDPSr132rY, X86::VFNMADDPSr132mY, TB_ALIGN_NONE },
1809 { X86::VFNMADDPDr132rY, X86::VFNMADDPDr132mY, TB_ALIGN_NONE },
1810 { X86::VFNMADDPSr213rY, X86::VFNMADDPSr213mY, TB_ALIGN_NONE },
1811 { X86::VFNMADDPDr213rY, X86::VFNMADDPDr213mY, TB_ALIGN_NONE },
1812
1813 { X86::VFMSUBSSr231r, X86::VFMSUBSSr231m, TB_ALIGN_NONE },
1814 { X86::VFMSUBSSr231r_Int, X86::VFMSUBSSr231m_Int, TB_ALIGN_NONE },
1815 { X86::VFMSUBSDr231r, X86::VFMSUBSDr231m, TB_ALIGN_NONE },
1816 { X86::VFMSUBSDr231r_Int, X86::VFMSUBSDr231m_Int, TB_ALIGN_NONE },
1817 { X86::VFMSUBSSr132r, X86::VFMSUBSSr132m, TB_ALIGN_NONE },
1818 { X86::VFMSUBSSr132r_Int, X86::VFMSUBSSr132m_Int, TB_ALIGN_NONE },
1819 { X86::VFMSUBSDr132r, X86::VFMSUBSDr132m, TB_ALIGN_NONE },
1820 { X86::VFMSUBSDr132r_Int, X86::VFMSUBSDr132m_Int, TB_ALIGN_NONE },
1821 { X86::VFMSUBSSr213r, X86::VFMSUBSSr213m, TB_ALIGN_NONE },
1822 { X86::VFMSUBSSr213r_Int, X86::VFMSUBSSr213m_Int, TB_ALIGN_NONE },
1823 { X86::VFMSUBSDr213r, X86::VFMSUBSDr213m, TB_ALIGN_NONE },
1824 { X86::VFMSUBSDr213r_Int, X86::VFMSUBSDr213m_Int, TB_ALIGN_NONE },
1825
1826 { X86::VFMSUBPSr231r, X86::VFMSUBPSr231m, TB_ALIGN_NONE },
1827 { X86::VFMSUBPDr231r, X86::VFMSUBPDr231m, TB_ALIGN_NONE },
1828 { X86::VFMSUBPSr132r, X86::VFMSUBPSr132m, TB_ALIGN_NONE },
1829 { X86::VFMSUBPDr132r, X86::VFMSUBPDr132m, TB_ALIGN_NONE },
1830 { X86::VFMSUBPSr213r, X86::VFMSUBPSr213m, TB_ALIGN_NONE },
1831 { X86::VFMSUBPDr213r, X86::VFMSUBPDr213m, TB_ALIGN_NONE },
1832 { X86::VFMSUBPSr231rY, X86::VFMSUBPSr231mY, TB_ALIGN_NONE },
1833 { X86::VFMSUBPDr231rY, X86::VFMSUBPDr231mY, TB_ALIGN_NONE },
1834 { X86::VFMSUBPSr132rY, X86::VFMSUBPSr132mY, TB_ALIGN_NONE },
1835 { X86::VFMSUBPDr132rY, X86::VFMSUBPDr132mY, TB_ALIGN_NONE },
1836 { X86::VFMSUBPSr213rY, X86::VFMSUBPSr213mY, TB_ALIGN_NONE },
1837 { X86::VFMSUBPDr213rY, X86::VFMSUBPDr213mY, TB_ALIGN_NONE },
1838
1839 { X86::VFNMSUBSSr231r, X86::VFNMSUBSSr231m, TB_ALIGN_NONE },
1840 { X86::VFNMSUBSSr231r_Int, X86::VFNMSUBSSr231m_Int, TB_ALIGN_NONE },
1841 { X86::VFNMSUBSDr231r, X86::VFNMSUBSDr231m, TB_ALIGN_NONE },
1842 { X86::VFNMSUBSDr231r_Int, X86::VFNMSUBSDr231m_Int, TB_ALIGN_NONE },
1843 { X86::VFNMSUBSSr132r, X86::VFNMSUBSSr132m, TB_ALIGN_NONE },
1844 { X86::VFNMSUBSSr132r_Int, X86::VFNMSUBSSr132m_Int, TB_ALIGN_NONE },
1845 { X86::VFNMSUBSDr132r, X86::VFNMSUBSDr132m, TB_ALIGN_NONE },
1846 { X86::VFNMSUBSDr132r_Int, X86::VFNMSUBSDr132m_Int, TB_ALIGN_NONE },
1847 { X86::VFNMSUBSSr213r, X86::VFNMSUBSSr213m, TB_ALIGN_NONE },
1848 { X86::VFNMSUBSSr213r_Int, X86::VFNMSUBSSr213m_Int, TB_ALIGN_NONE },
1849 { X86::VFNMSUBSDr213r, X86::VFNMSUBSDr213m, TB_ALIGN_NONE },
1850 { X86::VFNMSUBSDr213r_Int, X86::VFNMSUBSDr213m_Int, TB_ALIGN_NONE },
1851
1852 { X86::VFNMSUBPSr231r, X86::VFNMSUBPSr231m, TB_ALIGN_NONE },
1853 { X86::VFNMSUBPDr231r, X86::VFNMSUBPDr231m, TB_ALIGN_NONE },
1854 { X86::VFNMSUBPSr132r, X86::VFNMSUBPSr132m, TB_ALIGN_NONE },
1855 { X86::VFNMSUBPDr132r, X86::VFNMSUBPDr132m, TB_ALIGN_NONE },
1856 { X86::VFNMSUBPSr213r, X86::VFNMSUBPSr213m, TB_ALIGN_NONE },
1857 { X86::VFNMSUBPDr213r, X86::VFNMSUBPDr213m, TB_ALIGN_NONE },
1858 { X86::VFNMSUBPSr231rY, X86::VFNMSUBPSr231mY, TB_ALIGN_NONE },
1859 { X86::VFNMSUBPDr231rY, X86::VFNMSUBPDr231mY, TB_ALIGN_NONE },
1860 { X86::VFNMSUBPSr132rY, X86::VFNMSUBPSr132mY, TB_ALIGN_NONE },
1861 { X86::VFNMSUBPDr132rY, X86::VFNMSUBPDr132mY, TB_ALIGN_NONE },
1862 { X86::VFNMSUBPSr213rY, X86::VFNMSUBPSr213mY, TB_ALIGN_NONE },
1863 { X86::VFNMSUBPDr213rY, X86::VFNMSUBPDr213mY, TB_ALIGN_NONE },
1864
1865 { X86::VFMADDSUBPSr231r, X86::VFMADDSUBPSr231m, TB_ALIGN_NONE },
1866 { X86::VFMADDSUBPDr231r, X86::VFMADDSUBPDr231m, TB_ALIGN_NONE },
1867 { X86::VFMADDSUBPSr132r, X86::VFMADDSUBPSr132m, TB_ALIGN_NONE },
1868 { X86::VFMADDSUBPDr132r, X86::VFMADDSUBPDr132m, TB_ALIGN_NONE },
1869 { X86::VFMADDSUBPSr213r, X86::VFMADDSUBPSr213m, TB_ALIGN_NONE },
1870 { X86::VFMADDSUBPDr213r, X86::VFMADDSUBPDr213m, TB_ALIGN_NONE },
1871 { X86::VFMADDSUBPSr231rY, X86::VFMADDSUBPSr231mY, TB_ALIGN_NONE },
1872 { X86::VFMADDSUBPDr231rY, X86::VFMADDSUBPDr231mY, TB_ALIGN_NONE },
1873 { X86::VFMADDSUBPSr132rY, X86::VFMADDSUBPSr132mY, TB_ALIGN_NONE },
1874 { X86::VFMADDSUBPDr132rY, X86::VFMADDSUBPDr132mY, TB_ALIGN_NONE },
1875 { X86::VFMADDSUBPSr213rY, X86::VFMADDSUBPSr213mY, TB_ALIGN_NONE },
1876 { X86::VFMADDSUBPDr213rY, X86::VFMADDSUBPDr213mY, TB_ALIGN_NONE },
1877
1878 { X86::VFMSUBADDPSr231r, X86::VFMSUBADDPSr231m, TB_ALIGN_NONE },
1879 { X86::VFMSUBADDPDr231r, X86::VFMSUBADDPDr231m, TB_ALIGN_NONE },
1880 { X86::VFMSUBADDPSr132r, X86::VFMSUBADDPSr132m, TB_ALIGN_NONE },
1881 { X86::VFMSUBADDPDr132r, X86::VFMSUBADDPDr132m, TB_ALIGN_NONE },
1882 { X86::VFMSUBADDPSr213r, X86::VFMSUBADDPSr213m, TB_ALIGN_NONE },
1883 { X86::VFMSUBADDPDr213r, X86::VFMSUBADDPDr213m, TB_ALIGN_NONE },
1884 { X86::VFMSUBADDPSr231rY, X86::VFMSUBADDPSr231mY, TB_ALIGN_NONE },
1885 { X86::VFMSUBADDPDr231rY, X86::VFMSUBADDPDr231mY, TB_ALIGN_NONE },
1886 { X86::VFMSUBADDPSr132rY, X86::VFMSUBADDPSr132mY, TB_ALIGN_NONE },
1887 { X86::VFMSUBADDPDr132rY, X86::VFMSUBADDPDr132mY, TB_ALIGN_NONE },
1888 { X86::VFMSUBADDPSr213rY, X86::VFMSUBADDPSr213mY, TB_ALIGN_NONE },
1889 { X86::VFMSUBADDPDr213rY, X86::VFMSUBADDPDr213mY, TB_ALIGN_NONE },
1890
1891 // FMA4 foldable patterns
1892 { X86::VFMADDSS4rr, X86::VFMADDSS4rm, TB_ALIGN_NONE },
1893 { X86::VFMADDSD4rr, X86::VFMADDSD4rm, TB_ALIGN_NONE },
1894 { X86::VFMADDPS4rr, X86::VFMADDPS4rm, TB_ALIGN_NONE },
1895 { X86::VFMADDPD4rr, X86::VFMADDPD4rm, TB_ALIGN_NONE },
1896 { X86::VFMADDPS4rrY, X86::VFMADDPS4rmY, TB_ALIGN_NONE },
1897 { X86::VFMADDPD4rrY, X86::VFMADDPD4rmY, TB_ALIGN_NONE },
1898 { X86::VFNMADDSS4rr, X86::VFNMADDSS4rm, TB_ALIGN_NONE },
1899 { X86::VFNMADDSD4rr, X86::VFNMADDSD4rm, TB_ALIGN_NONE },
1900 { X86::VFNMADDPS4rr, X86::VFNMADDPS4rm, TB_ALIGN_NONE },
1901 { X86::VFNMADDPD4rr, X86::VFNMADDPD4rm, TB_ALIGN_NONE },
1902 { X86::VFNMADDPS4rrY, X86::VFNMADDPS4rmY, TB_ALIGN_NONE },
1903 { X86::VFNMADDPD4rrY, X86::VFNMADDPD4rmY, TB_ALIGN_NONE },
1904 { X86::VFMSUBSS4rr, X86::VFMSUBSS4rm, TB_ALIGN_NONE },
1905 { X86::VFMSUBSD4rr, X86::VFMSUBSD4rm, TB_ALIGN_NONE },
1906 { X86::VFMSUBPS4rr, X86::VFMSUBPS4rm, TB_ALIGN_NONE },
1907 { X86::VFMSUBPD4rr, X86::VFMSUBPD4rm, TB_ALIGN_NONE },
1908 { X86::VFMSUBPS4rrY, X86::VFMSUBPS4rmY, TB_ALIGN_NONE },
1909 { X86::VFMSUBPD4rrY, X86::VFMSUBPD4rmY, TB_ALIGN_NONE },
1910 { X86::VFNMSUBSS4rr, X86::VFNMSUBSS4rm, TB_ALIGN_NONE },
1911 { X86::VFNMSUBSD4rr, X86::VFNMSUBSD4rm, TB_ALIGN_NONE },
1912 { X86::VFNMSUBPS4rr, X86::VFNMSUBPS4rm, TB_ALIGN_NONE },
1913 { X86::VFNMSUBPD4rr, X86::VFNMSUBPD4rm, TB_ALIGN_NONE },
1914 { X86::VFNMSUBPS4rrY, X86::VFNMSUBPS4rmY, TB_ALIGN_NONE },
1915 { X86::VFNMSUBPD4rrY, X86::VFNMSUBPD4rmY, TB_ALIGN_NONE },
1916 { X86::VFMADDSUBPS4rr, X86::VFMADDSUBPS4rm, TB_ALIGN_NONE },
1917 { X86::VFMADDSUBPD4rr, X86::VFMADDSUBPD4rm, TB_ALIGN_NONE },
1918 { X86::VFMADDSUBPS4rrY, X86::VFMADDSUBPS4rmY, TB_ALIGN_NONE },
1919 { X86::VFMADDSUBPD4rrY, X86::VFMADDSUBPD4rmY, TB_ALIGN_NONE },
1920 { X86::VFMSUBADDPS4rr, X86::VFMSUBADDPS4rm, TB_ALIGN_NONE },
1921 { X86::VFMSUBADDPD4rr, X86::VFMSUBADDPD4rm, TB_ALIGN_NONE },
1922 { X86::VFMSUBADDPS4rrY, X86::VFMSUBADDPS4rmY, TB_ALIGN_NONE },
1923 { X86::VFMSUBADDPD4rrY, X86::VFMSUBADDPD4rmY, TB_ALIGN_NONE },
1924
1925 // XOP foldable instructions
1926 { X86::VPCMOVrrr, X86::VPCMOVrrm, 0 },
1927 { X86::VPCMOVrrrY, X86::VPCMOVrrmY, 0 },
1928 { X86::VPERMIL2PDrr, X86::VPERMIL2PDrm, 0 },
1929 { X86::VPERMIL2PDrrY, X86::VPERMIL2PDrmY, 0 },
1930 { X86::VPERMIL2PSrr, X86::VPERMIL2PSrm, 0 },
1931 { X86::VPERMIL2PSrrY, X86::VPERMIL2PSrmY, 0 },
1932 { X86::VPPERMrrr, X86::VPPERMrrm, 0 },
1933
1934 // AVX-512 VPERMI instructions with 3 source operands.
1935 { X86::VPERMI2Drr, X86::VPERMI2Drm, 0 },
1936 { X86::VPERMI2Qrr, X86::VPERMI2Qrm, 0 },
1937 { X86::VPERMI2PSrr, X86::VPERMI2PSrm, 0 },
1938 { X86::VPERMI2PDrr, X86::VPERMI2PDrm, 0 },
1939 { X86::VBLENDMPDZrr, X86::VBLENDMPDZrm, 0 },
1940 { X86::VBLENDMPSZrr, X86::VBLENDMPSZrm, 0 },
1941 { X86::VPBLENDMDZrr, X86::VPBLENDMDZrm, 0 },
1942 { X86::VPBLENDMQZrr, X86::VPBLENDMQZrm, 0 },
1943 { X86::VBROADCASTSSZrk, X86::VBROADCASTSSZmk, TB_NO_REVERSE },
1944 { X86::VBROADCASTSDZrk, X86::VBROADCASTSDZmk, TB_NO_REVERSE },
1945 { X86::VBROADCASTSSZ256rk, X86::VBROADCASTSSZ256mk, TB_NO_REVERSE },
1946 { X86::VBROADCASTSDZ256rk, X86::VBROADCASTSDZ256mk, TB_NO_REVERSE },
1947 { X86::VBROADCASTSSZ128rk, X86::VBROADCASTSSZ128mk, TB_NO_REVERSE },
1948 // AVX-512 arithmetic instructions
1949 { X86::VADDPSZrrkz, X86::VADDPSZrmkz, 0 },
1950 { X86::VADDPDZrrkz, X86::VADDPDZrmkz, 0 },
1951 { X86::VSUBPSZrrkz, X86::VSUBPSZrmkz, 0 },
1952 { X86::VSUBPDZrrkz, X86::VSUBPDZrmkz, 0 },
1953 { X86::VMULPSZrrkz, X86::VMULPSZrmkz, 0 },
1954 { X86::VMULPDZrrkz, X86::VMULPDZrmkz, 0 },
1955 { X86::VDIVPSZrrkz, X86::VDIVPSZrmkz, 0 },
1956 { X86::VDIVPDZrrkz, X86::VDIVPDZrmkz, 0 },
1957 { X86::VMINPSZrrkz, X86::VMINPSZrmkz, 0 },
1958 { X86::VMINPDZrrkz, X86::VMINPDZrmkz, 0 },
1959 { X86::VMAXPSZrrkz, X86::VMAXPSZrmkz, 0 },
1960 { X86::VMAXPDZrrkz, X86::VMAXPDZrmkz, 0 },
1961 // AVX-512{F,VL} arithmetic instructions 256-bit
1962 { X86::VADDPSZ256rrkz, X86::VADDPSZ256rmkz, 0 },
1963 { X86::VADDPDZ256rrkz, X86::VADDPDZ256rmkz, 0 },
1964 { X86::VSUBPSZ256rrkz, X86::VSUBPSZ256rmkz, 0 },
1965 { X86::VSUBPDZ256rrkz, X86::VSUBPDZ256rmkz, 0 },
1966 { X86::VMULPSZ256rrkz, X86::VMULPSZ256rmkz, 0 },
1967 { X86::VMULPDZ256rrkz, X86::VMULPDZ256rmkz, 0 },
1968 { X86::VDIVPSZ256rrkz, X86::VDIVPSZ256rmkz, 0 },
1969 { X86::VDIVPDZ256rrkz, X86::VDIVPDZ256rmkz, 0 },
1970 { X86::VMINPSZ256rrkz, X86::VMINPSZ256rmkz, 0 },
1971 { X86::VMINPDZ256rrkz, X86::VMINPDZ256rmkz, 0 },
1972 { X86::VMAXPSZ256rrkz, X86::VMAXPSZ256rmkz, 0 },
1973 { X86::VMAXPDZ256rrkz, X86::VMAXPDZ256rmkz, 0 },
1974 // AVX-512{F,VL} arithmetic instructions 128-bit
1975 { X86::VADDPSZ128rrkz, X86::VADDPSZ128rmkz, 0 },
1976 { X86::VADDPDZ128rrkz, X86::VADDPDZ128rmkz, 0 },
1977 { X86::VSUBPSZ128rrkz, X86::VSUBPSZ128rmkz, 0 },
1978 { X86::VSUBPDZ128rrkz, X86::VSUBPDZ128rmkz, 0 },
1979 { X86::VMULPSZ128rrkz, X86::VMULPSZ128rmkz, 0 },
1980 { X86::VMULPDZ128rrkz, X86::VMULPDZ128rmkz, 0 },
1981 { X86::VDIVPSZ128rrkz, X86::VDIVPSZ128rmkz, 0 },
1982 { X86::VDIVPDZ128rrkz, X86::VDIVPDZ128rmkz, 0 },
1983 { X86::VMINPSZ128rrkz, X86::VMINPSZ128rmkz, 0 },
1984 { X86::VMINPDZ128rrkz, X86::VMINPDZ128rmkz, 0 },
1985 { X86::VMAXPSZ128rrkz, X86::VMAXPSZ128rmkz, 0 },
1986 { X86::VMAXPDZ128rrkz, X86::VMAXPDZ128rmkz, 0 }
1987 };
1988
1989 for (X86MemoryFoldTableEntry Entry : MemoryFoldTable3) {
1990 AddTableEntry(RegOp2MemOpTable3, MemOp2RegOpTable,
1991 Entry.RegOp, Entry.MemOp,
1992 // Index 3, folded load
1993 Entry.Flags | TB_INDEX_3 | TB_FOLDED_LOAD);
1994 }
1995
1996 static const X86MemoryFoldTableEntry MemoryFoldTable4[] = {
1997 // AVX-512 foldable instructions
1998 { X86::VADDPSZrrk, X86::VADDPSZrmk, 0 },
1999 { X86::VADDPDZrrk, X86::VADDPDZrmk, 0 },
2000 { X86::VSUBPSZrrk, X86::VSUBPSZrmk, 0 },
2001 { X86::VSUBPDZrrk, X86::VSUBPDZrmk, 0 },
2002 { X86::VMULPSZrrk, X86::VMULPSZrmk, 0 },
2003 { X86::VMULPDZrrk, X86::VMULPDZrmk, 0 },
2004 { X86::VDIVPSZrrk, X86::VDIVPSZrmk, 0 },
2005 { X86::VDIVPDZrrk, X86::VDIVPDZrmk, 0 },
2006 { X86::VMINPSZrrk, X86::VMINPSZrmk, 0 },
2007 { X86::VMINPDZrrk, X86::VMINPDZrmk, 0 },
2008 { X86::VMAXPSZrrk, X86::VMAXPSZrmk, 0 },
2009 { X86::VMAXPDZrrk, X86::VMAXPDZrmk, 0 },
2010 // AVX-512{F,VL} foldable instructions 256-bit
2011 { X86::VADDPSZ256rrk, X86::VADDPSZ256rmk, 0 },
2012 { X86::VADDPDZ256rrk, X86::VADDPDZ256rmk, 0 },
2013 { X86::VSUBPSZ256rrk, X86::VSUBPSZ256rmk, 0 },
2014 { X86::VSUBPDZ256rrk, X86::VSUBPDZ256rmk, 0 },
2015 { X86::VMULPSZ256rrk, X86::VMULPSZ256rmk, 0 },
2016 { X86::VMULPDZ256rrk, X86::VMULPDZ256rmk, 0 },
2017 { X86::VDIVPSZ256rrk, X86::VDIVPSZ256rmk, 0 },
2018 { X86::VDIVPDZ256rrk, X86::VDIVPDZ256rmk, 0 },
2019 { X86::VMINPSZ256rrk, X86::VMINPSZ256rmk, 0 },
2020 { X86::VMINPDZ256rrk, X86::VMINPDZ256rmk, 0 },
2021 { X86::VMAXPSZ256rrk, X86::VMAXPSZ256rmk, 0 },
2022 { X86::VMAXPDZ256rrk, X86::VMAXPDZ256rmk, 0 },
2023 // AVX-512{F,VL} foldable instructions 128-bit
2024 { X86::VADDPSZ128rrk, X86::VADDPSZ128rmk, 0 },
2025 { X86::VADDPDZ128rrk, X86::VADDPDZ128rmk, 0 },
2026 { X86::VSUBPSZ128rrk, X86::VSUBPSZ128rmk, 0 },
2027 { X86::VSUBPDZ128rrk, X86::VSUBPDZ128rmk, 0 },
2028 { X86::VMULPSZ128rrk, X86::VMULPSZ128rmk, 0 },
2029 { X86::VMULPDZ128rrk, X86::VMULPDZ128rmk, 0 },
2030 { X86::VDIVPSZ128rrk, X86::VDIVPSZ128rmk, 0 },
2031 { X86::VDIVPDZ128rrk, X86::VDIVPDZ128rmk, 0 },
2032 { X86::VMINPSZ128rrk, X86::VMINPSZ128rmk, 0 },
2033 { X86::VMINPDZ128rrk, X86::VMINPDZ128rmk, 0 },
2034 { X86::VMAXPSZ128rrk, X86::VMAXPSZ128rmk, 0 },
2035 { X86::VMAXPDZ128rrk, X86::VMAXPDZ128rmk, 0 }
2036 };
2037
2038 for (X86MemoryFoldTableEntry Entry : MemoryFoldTable4) {
2039 AddTableEntry(RegOp2MemOpTable4, MemOp2RegOpTable,
2040 Entry.RegOp, Entry.MemOp,
2041 // Index 4, folded load
2042 Entry.Flags | TB_INDEX_4 | TB_FOLDED_LOAD);
2043 }
2044 }
2045
2046 void
AddTableEntry(RegOp2MemOpTableType & R2MTable,MemOp2RegOpTableType & M2RTable,uint16_t RegOp,uint16_t MemOp,uint16_t Flags)2047 X86InstrInfo::AddTableEntry(RegOp2MemOpTableType &R2MTable,
2048 MemOp2RegOpTableType &M2RTable,
2049 uint16_t RegOp, uint16_t MemOp, uint16_t Flags) {
2050 if ((Flags & TB_NO_FORWARD) == 0) {
2051 assert(!R2MTable.count(RegOp) && "Duplicate entry!");
2052 R2MTable[RegOp] = std::make_pair(MemOp, Flags);
2053 }
2054 if ((Flags & TB_NO_REVERSE) == 0) {
2055 assert(!M2RTable.count(MemOp) &&
2056 "Duplicated entries in unfolding maps?");
2057 M2RTable[MemOp] = std::make_pair(RegOp, Flags);
2058 }
2059 }
2060
2061 bool
isCoalescableExtInstr(const MachineInstr & MI,unsigned & SrcReg,unsigned & DstReg,unsigned & SubIdx) const2062 X86InstrInfo::isCoalescableExtInstr(const MachineInstr &MI,
2063 unsigned &SrcReg, unsigned &DstReg,
2064 unsigned &SubIdx) const {
2065 switch (MI.getOpcode()) {
2066 default: break;
2067 case X86::MOVSX16rr8:
2068 case X86::MOVZX16rr8:
2069 case X86::MOVSX32rr8:
2070 case X86::MOVZX32rr8:
2071 case X86::MOVSX64rr8:
2072 if (!Subtarget.is64Bit())
2073 // It's not always legal to reference the low 8-bit of the larger
2074 // register in 32-bit mode.
2075 return false;
2076 case X86::MOVSX32rr16:
2077 case X86::MOVZX32rr16:
2078 case X86::MOVSX64rr16:
2079 case X86::MOVSX64rr32: {
2080 if (MI.getOperand(0).getSubReg() || MI.getOperand(1).getSubReg())
2081 // Be conservative.
2082 return false;
2083 SrcReg = MI.getOperand(1).getReg();
2084 DstReg = MI.getOperand(0).getReg();
2085 switch (MI.getOpcode()) {
2086 default: llvm_unreachable("Unreachable!");
2087 case X86::MOVSX16rr8:
2088 case X86::MOVZX16rr8:
2089 case X86::MOVSX32rr8:
2090 case X86::MOVZX32rr8:
2091 case X86::MOVSX64rr8:
2092 SubIdx = X86::sub_8bit;
2093 break;
2094 case X86::MOVSX32rr16:
2095 case X86::MOVZX32rr16:
2096 case X86::MOVSX64rr16:
2097 SubIdx = X86::sub_16bit;
2098 break;
2099 case X86::MOVSX64rr32:
2100 SubIdx = X86::sub_32bit;
2101 break;
2102 }
2103 return true;
2104 }
2105 }
2106 return false;
2107 }
2108
getSPAdjust(const MachineInstr & MI) const2109 int X86InstrInfo::getSPAdjust(const MachineInstr &MI) const {
2110 const MachineFunction *MF = MI.getParent()->getParent();
2111 const TargetFrameLowering *TFI = MF->getSubtarget().getFrameLowering();
2112
2113 if (MI.getOpcode() == getCallFrameSetupOpcode() ||
2114 MI.getOpcode() == getCallFrameDestroyOpcode()) {
2115 unsigned StackAlign = TFI->getStackAlignment();
2116 int SPAdj =
2117 (MI.getOperand(0).getImm() + StackAlign - 1) / StackAlign * StackAlign;
2118
2119 SPAdj -= MI.getOperand(1).getImm();
2120
2121 if (MI.getOpcode() == getCallFrameSetupOpcode())
2122 return SPAdj;
2123 else
2124 return -SPAdj;
2125 }
2126
2127 // To know whether a call adjusts the stack, we need information
2128 // that is bound to the following ADJCALLSTACKUP pseudo.
2129 // Look for the next ADJCALLSTACKUP that follows the call.
2130 if (MI.isCall()) {
2131 const MachineBasicBlock *MBB = MI.getParent();
2132 auto I = ++MachineBasicBlock::const_iterator(MI);
2133 for (auto E = MBB->end(); I != E; ++I) {
2134 if (I->getOpcode() == getCallFrameDestroyOpcode() ||
2135 I->isCall())
2136 break;
2137 }
2138
2139 // If we could not find a frame destroy opcode, then it has already
2140 // been simplified, so we don't care.
2141 if (I->getOpcode() != getCallFrameDestroyOpcode())
2142 return 0;
2143
2144 return -(I->getOperand(1).getImm());
2145 }
2146
2147 // Currently handle only PUSHes we can reasonably expect to see
2148 // in call sequences
2149 switch (MI.getOpcode()) {
2150 default:
2151 return 0;
2152 case X86::PUSH32i8:
2153 case X86::PUSH32r:
2154 case X86::PUSH32rmm:
2155 case X86::PUSH32rmr:
2156 case X86::PUSHi32:
2157 return 4;
2158 case X86::PUSH64i8:
2159 case X86::PUSH64r:
2160 case X86::PUSH64rmm:
2161 case X86::PUSH64rmr:
2162 case X86::PUSH64i32:
2163 return 8;
2164 }
2165 }
2166
2167 /// Return true and the FrameIndex if the specified
2168 /// operand and follow operands form a reference to the stack frame.
isFrameOperand(const MachineInstr & MI,unsigned int Op,int & FrameIndex) const2169 bool X86InstrInfo::isFrameOperand(const MachineInstr &MI, unsigned int Op,
2170 int &FrameIndex) const {
2171 if (MI.getOperand(Op + X86::AddrBaseReg).isFI() &&
2172 MI.getOperand(Op + X86::AddrScaleAmt).isImm() &&
2173 MI.getOperand(Op + X86::AddrIndexReg).isReg() &&
2174 MI.getOperand(Op + X86::AddrDisp).isImm() &&
2175 MI.getOperand(Op + X86::AddrScaleAmt).getImm() == 1 &&
2176 MI.getOperand(Op + X86::AddrIndexReg).getReg() == 0 &&
2177 MI.getOperand(Op + X86::AddrDisp).getImm() == 0) {
2178 FrameIndex = MI.getOperand(Op + X86::AddrBaseReg).getIndex();
2179 return true;
2180 }
2181 return false;
2182 }
2183
isFrameLoadOpcode(int Opcode)2184 static bool isFrameLoadOpcode(int Opcode) {
2185 switch (Opcode) {
2186 default:
2187 return false;
2188 case X86::MOV8rm:
2189 case X86::MOV16rm:
2190 case X86::MOV32rm:
2191 case X86::MOV64rm:
2192 case X86::LD_Fp64m:
2193 case X86::MOVSSrm:
2194 case X86::MOVSDrm:
2195 case X86::MOVAPSrm:
2196 case X86::MOVAPDrm:
2197 case X86::MOVDQArm:
2198 case X86::VMOVSSrm:
2199 case X86::VMOVSDrm:
2200 case X86::VMOVAPSrm:
2201 case X86::VMOVAPDrm:
2202 case X86::VMOVDQArm:
2203 case X86::VMOVUPSYrm:
2204 case X86::VMOVAPSYrm:
2205 case X86::VMOVUPDYrm:
2206 case X86::VMOVAPDYrm:
2207 case X86::VMOVDQUYrm:
2208 case X86::VMOVDQAYrm:
2209 case X86::MMX_MOVD64rm:
2210 case X86::MMX_MOVQ64rm:
2211 case X86::VMOVAPSZrm:
2212 case X86::VMOVUPSZrm:
2213 return true;
2214 }
2215 }
2216
isFrameStoreOpcode(int Opcode)2217 static bool isFrameStoreOpcode(int Opcode) {
2218 switch (Opcode) {
2219 default: break;
2220 case X86::MOV8mr:
2221 case X86::MOV16mr:
2222 case X86::MOV32mr:
2223 case X86::MOV64mr:
2224 case X86::ST_FpP64m:
2225 case X86::MOVSSmr:
2226 case X86::MOVSDmr:
2227 case X86::MOVAPSmr:
2228 case X86::MOVAPDmr:
2229 case X86::MOVDQAmr:
2230 case X86::VMOVSSmr:
2231 case X86::VMOVSDmr:
2232 case X86::VMOVAPSmr:
2233 case X86::VMOVAPDmr:
2234 case X86::VMOVDQAmr:
2235 case X86::VMOVUPSYmr:
2236 case X86::VMOVAPSYmr:
2237 case X86::VMOVUPDYmr:
2238 case X86::VMOVAPDYmr:
2239 case X86::VMOVDQUYmr:
2240 case X86::VMOVDQAYmr:
2241 case X86::VMOVUPSZmr:
2242 case X86::VMOVAPSZmr:
2243 case X86::MMX_MOVD64mr:
2244 case X86::MMX_MOVQ64mr:
2245 case X86::MMX_MOVNTQmr:
2246 return true;
2247 }
2248 return false;
2249 }
2250
isLoadFromStackSlot(const MachineInstr & MI,int & FrameIndex) const2251 unsigned X86InstrInfo::isLoadFromStackSlot(const MachineInstr &MI,
2252 int &FrameIndex) const {
2253 if (isFrameLoadOpcode(MI.getOpcode()))
2254 if (MI.getOperand(0).getSubReg() == 0 && isFrameOperand(MI, 1, FrameIndex))
2255 return MI.getOperand(0).getReg();
2256 return 0;
2257 }
2258
isLoadFromStackSlotPostFE(const MachineInstr & MI,int & FrameIndex) const2259 unsigned X86InstrInfo::isLoadFromStackSlotPostFE(const MachineInstr &MI,
2260 int &FrameIndex) const {
2261 if (isFrameLoadOpcode(MI.getOpcode())) {
2262 unsigned Reg;
2263 if ((Reg = isLoadFromStackSlot(MI, FrameIndex)))
2264 return Reg;
2265 // Check for post-frame index elimination operations
2266 const MachineMemOperand *Dummy;
2267 return hasLoadFromStackSlot(MI, Dummy, FrameIndex);
2268 }
2269 return 0;
2270 }
2271
isStoreToStackSlot(const MachineInstr & MI,int & FrameIndex) const2272 unsigned X86InstrInfo::isStoreToStackSlot(const MachineInstr &MI,
2273 int &FrameIndex) const {
2274 if (isFrameStoreOpcode(MI.getOpcode()))
2275 if (MI.getOperand(X86::AddrNumOperands).getSubReg() == 0 &&
2276 isFrameOperand(MI, 0, FrameIndex))
2277 return MI.getOperand(X86::AddrNumOperands).getReg();
2278 return 0;
2279 }
2280
isStoreToStackSlotPostFE(const MachineInstr & MI,int & FrameIndex) const2281 unsigned X86InstrInfo::isStoreToStackSlotPostFE(const MachineInstr &MI,
2282 int &FrameIndex) const {
2283 if (isFrameStoreOpcode(MI.getOpcode())) {
2284 unsigned Reg;
2285 if ((Reg = isStoreToStackSlot(MI, FrameIndex)))
2286 return Reg;
2287 // Check for post-frame index elimination operations
2288 const MachineMemOperand *Dummy;
2289 return hasStoreToStackSlot(MI, Dummy, FrameIndex);
2290 }
2291 return 0;
2292 }
2293
2294 /// Return true if register is PIC base; i.e.g defined by X86::MOVPC32r.
regIsPICBase(unsigned BaseReg,const MachineRegisterInfo & MRI)2295 static bool regIsPICBase(unsigned BaseReg, const MachineRegisterInfo &MRI) {
2296 // Don't waste compile time scanning use-def chains of physregs.
2297 if (!TargetRegisterInfo::isVirtualRegister(BaseReg))
2298 return false;
2299 bool isPICBase = false;
2300 for (MachineRegisterInfo::def_instr_iterator I = MRI.def_instr_begin(BaseReg),
2301 E = MRI.def_instr_end(); I != E; ++I) {
2302 MachineInstr *DefMI = &*I;
2303 if (DefMI->getOpcode() != X86::MOVPC32r)
2304 return false;
2305 assert(!isPICBase && "More than one PIC base?");
2306 isPICBase = true;
2307 }
2308 return isPICBase;
2309 }
2310
isReallyTriviallyReMaterializable(const MachineInstr & MI,AliasAnalysis * AA) const2311 bool X86InstrInfo::isReallyTriviallyReMaterializable(const MachineInstr &MI,
2312 AliasAnalysis *AA) const {
2313 switch (MI.getOpcode()) {
2314 default: break;
2315 case X86::MOV8rm:
2316 case X86::MOV16rm:
2317 case X86::MOV32rm:
2318 case X86::MOV64rm:
2319 case X86::LD_Fp64m:
2320 case X86::MOVSSrm:
2321 case X86::MOVSDrm:
2322 case X86::MOVAPSrm:
2323 case X86::MOVUPSrm:
2324 case X86::MOVAPDrm:
2325 case X86::MOVDQArm:
2326 case X86::MOVDQUrm:
2327 case X86::VMOVSSrm:
2328 case X86::VMOVSDrm:
2329 case X86::VMOVAPSrm:
2330 case X86::VMOVUPSrm:
2331 case X86::VMOVAPDrm:
2332 case X86::VMOVDQArm:
2333 case X86::VMOVDQUrm:
2334 case X86::VMOVAPSYrm:
2335 case X86::VMOVUPSYrm:
2336 case X86::VMOVAPDYrm:
2337 case X86::VMOVDQAYrm:
2338 case X86::VMOVDQUYrm:
2339 case X86::MMX_MOVD64rm:
2340 case X86::MMX_MOVQ64rm:
2341 case X86::FsVMOVAPSrm:
2342 case X86::FsVMOVAPDrm:
2343 case X86::FsMOVAPSrm:
2344 case X86::FsMOVAPDrm:
2345 // AVX-512
2346 case X86::VMOVAPDZ128rm:
2347 case X86::VMOVAPDZ256rm:
2348 case X86::VMOVAPDZrm:
2349 case X86::VMOVAPSZ128rm:
2350 case X86::VMOVAPSZ256rm:
2351 case X86::VMOVAPSZrm:
2352 case X86::VMOVDQA32Z128rm:
2353 case X86::VMOVDQA32Z256rm:
2354 case X86::VMOVDQA32Zrm:
2355 case X86::VMOVDQA64Z128rm:
2356 case X86::VMOVDQA64Z256rm:
2357 case X86::VMOVDQA64Zrm:
2358 case X86::VMOVDQU16Z128rm:
2359 case X86::VMOVDQU16Z256rm:
2360 case X86::VMOVDQU16Zrm:
2361 case X86::VMOVDQU32Z128rm:
2362 case X86::VMOVDQU32Z256rm:
2363 case X86::VMOVDQU32Zrm:
2364 case X86::VMOVDQU64Z128rm:
2365 case X86::VMOVDQU64Z256rm:
2366 case X86::VMOVDQU64Zrm:
2367 case X86::VMOVDQU8Z128rm:
2368 case X86::VMOVDQU8Z256rm:
2369 case X86::VMOVDQU8Zrm:
2370 case X86::VMOVUPSZ128rm:
2371 case X86::VMOVUPSZ256rm:
2372 case X86::VMOVUPSZrm: {
2373 // Loads from constant pools are trivially rematerializable.
2374 if (MI.getOperand(1 + X86::AddrBaseReg).isReg() &&
2375 MI.getOperand(1 + X86::AddrScaleAmt).isImm() &&
2376 MI.getOperand(1 + X86::AddrIndexReg).isReg() &&
2377 MI.getOperand(1 + X86::AddrIndexReg).getReg() == 0 &&
2378 MI.isInvariantLoad(AA)) {
2379 unsigned BaseReg = MI.getOperand(1 + X86::AddrBaseReg).getReg();
2380 if (BaseReg == 0 || BaseReg == X86::RIP)
2381 return true;
2382 // Allow re-materialization of PIC load.
2383 if (!ReMatPICStubLoad && MI.getOperand(1 + X86::AddrDisp).isGlobal())
2384 return false;
2385 const MachineFunction &MF = *MI.getParent()->getParent();
2386 const MachineRegisterInfo &MRI = MF.getRegInfo();
2387 return regIsPICBase(BaseReg, MRI);
2388 }
2389 return false;
2390 }
2391
2392 case X86::LEA32r:
2393 case X86::LEA64r: {
2394 if (MI.getOperand(1 + X86::AddrScaleAmt).isImm() &&
2395 MI.getOperand(1 + X86::AddrIndexReg).isReg() &&
2396 MI.getOperand(1 + X86::AddrIndexReg).getReg() == 0 &&
2397 !MI.getOperand(1 + X86::AddrDisp).isReg()) {
2398 // lea fi#, lea GV, etc. are all rematerializable.
2399 if (!MI.getOperand(1 + X86::AddrBaseReg).isReg())
2400 return true;
2401 unsigned BaseReg = MI.getOperand(1 + X86::AddrBaseReg).getReg();
2402 if (BaseReg == 0)
2403 return true;
2404 // Allow re-materialization of lea PICBase + x.
2405 const MachineFunction &MF = *MI.getParent()->getParent();
2406 const MachineRegisterInfo &MRI = MF.getRegInfo();
2407 return regIsPICBase(BaseReg, MRI);
2408 }
2409 return false;
2410 }
2411 }
2412
2413 // All other instructions marked M_REMATERIALIZABLE are always trivially
2414 // rematerializable.
2415 return true;
2416 }
2417
isSafeToClobberEFLAGS(MachineBasicBlock & MBB,MachineBasicBlock::iterator I) const2418 bool X86InstrInfo::isSafeToClobberEFLAGS(MachineBasicBlock &MBB,
2419 MachineBasicBlock::iterator I) const {
2420 MachineBasicBlock::iterator E = MBB.end();
2421
2422 // For compile time consideration, if we are not able to determine the
2423 // safety after visiting 4 instructions in each direction, we will assume
2424 // it's not safe.
2425 MachineBasicBlock::iterator Iter = I;
2426 for (unsigned i = 0; Iter != E && i < 4; ++i) {
2427 bool SeenDef = false;
2428 for (unsigned j = 0, e = Iter->getNumOperands(); j != e; ++j) {
2429 MachineOperand &MO = Iter->getOperand(j);
2430 if (MO.isRegMask() && MO.clobbersPhysReg(X86::EFLAGS))
2431 SeenDef = true;
2432 if (!MO.isReg())
2433 continue;
2434 if (MO.getReg() == X86::EFLAGS) {
2435 if (MO.isUse())
2436 return false;
2437 SeenDef = true;
2438 }
2439 }
2440
2441 if (SeenDef)
2442 // This instruction defines EFLAGS, no need to look any further.
2443 return true;
2444 ++Iter;
2445 // Skip over DBG_VALUE.
2446 while (Iter != E && Iter->isDebugValue())
2447 ++Iter;
2448 }
2449
2450 // It is safe to clobber EFLAGS at the end of a block of no successor has it
2451 // live in.
2452 if (Iter == E) {
2453 for (MachineBasicBlock *S : MBB.successors())
2454 if (S->isLiveIn(X86::EFLAGS))
2455 return false;
2456 return true;
2457 }
2458
2459 MachineBasicBlock::iterator B = MBB.begin();
2460 Iter = I;
2461 for (unsigned i = 0; i < 4; ++i) {
2462 // If we make it to the beginning of the block, it's safe to clobber
2463 // EFLAGS iff EFLAGS is not live-in.
2464 if (Iter == B)
2465 return !MBB.isLiveIn(X86::EFLAGS);
2466
2467 --Iter;
2468 // Skip over DBG_VALUE.
2469 while (Iter != B && Iter->isDebugValue())
2470 --Iter;
2471
2472 bool SawKill = false;
2473 for (unsigned j = 0, e = Iter->getNumOperands(); j != e; ++j) {
2474 MachineOperand &MO = Iter->getOperand(j);
2475 // A register mask may clobber EFLAGS, but we should still look for a
2476 // live EFLAGS def.
2477 if (MO.isRegMask() && MO.clobbersPhysReg(X86::EFLAGS))
2478 SawKill = true;
2479 if (MO.isReg() && MO.getReg() == X86::EFLAGS) {
2480 if (MO.isDef()) return MO.isDead();
2481 if (MO.isKill()) SawKill = true;
2482 }
2483 }
2484
2485 if (SawKill)
2486 // This instruction kills EFLAGS and doesn't redefine it, so
2487 // there's no need to look further.
2488 return true;
2489 }
2490
2491 // Conservative answer.
2492 return false;
2493 }
2494
reMaterialize(MachineBasicBlock & MBB,MachineBasicBlock::iterator I,unsigned DestReg,unsigned SubIdx,const MachineInstr & Orig,const TargetRegisterInfo & TRI) const2495 void X86InstrInfo::reMaterialize(MachineBasicBlock &MBB,
2496 MachineBasicBlock::iterator I,
2497 unsigned DestReg, unsigned SubIdx,
2498 const MachineInstr &Orig,
2499 const TargetRegisterInfo &TRI) const {
2500 bool ClobbersEFLAGS = false;
2501 for (const MachineOperand &MO : Orig.operands()) {
2502 if (MO.isReg() && MO.isDef() && MO.getReg() == X86::EFLAGS) {
2503 ClobbersEFLAGS = true;
2504 break;
2505 }
2506 }
2507
2508 if (ClobbersEFLAGS && !isSafeToClobberEFLAGS(MBB, I)) {
2509 // The instruction clobbers EFLAGS. Re-materialize as MOV32ri to avoid side
2510 // effects.
2511 int Value;
2512 switch (Orig.getOpcode()) {
2513 case X86::MOV32r0: Value = 0; break;
2514 case X86::MOV32r1: Value = 1; break;
2515 case X86::MOV32r_1: Value = -1; break;
2516 default:
2517 llvm_unreachable("Unexpected instruction!");
2518 }
2519
2520 const DebugLoc &DL = Orig.getDebugLoc();
2521 BuildMI(MBB, I, DL, get(X86::MOV32ri))
2522 .addOperand(Orig.getOperand(0))
2523 .addImm(Value);
2524 } else {
2525 MachineInstr *MI = MBB.getParent()->CloneMachineInstr(&Orig);
2526 MBB.insert(I, MI);
2527 }
2528
2529 MachineInstr &NewMI = *std::prev(I);
2530 NewMI.substituteRegister(Orig.getOperand(0).getReg(), DestReg, SubIdx, TRI);
2531 }
2532
2533 /// True if MI has a condition code def, e.g. EFLAGS, that is not marked dead.
hasLiveCondCodeDef(MachineInstr & MI) const2534 bool X86InstrInfo::hasLiveCondCodeDef(MachineInstr &MI) const {
2535 for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) {
2536 MachineOperand &MO = MI.getOperand(i);
2537 if (MO.isReg() && MO.isDef() &&
2538 MO.getReg() == X86::EFLAGS && !MO.isDead()) {
2539 return true;
2540 }
2541 }
2542 return false;
2543 }
2544
2545 /// Check whether the shift count for a machine operand is non-zero.
getTruncatedShiftCount(MachineInstr & MI,unsigned ShiftAmtOperandIdx)2546 inline static unsigned getTruncatedShiftCount(MachineInstr &MI,
2547 unsigned ShiftAmtOperandIdx) {
2548 // The shift count is six bits with the REX.W prefix and five bits without.
2549 unsigned ShiftCountMask = (MI.getDesc().TSFlags & X86II::REX_W) ? 63 : 31;
2550 unsigned Imm = MI.getOperand(ShiftAmtOperandIdx).getImm();
2551 return Imm & ShiftCountMask;
2552 }
2553
2554 /// Check whether the given shift count is appropriate
2555 /// can be represented by a LEA instruction.
isTruncatedShiftCountForLEA(unsigned ShAmt)2556 inline static bool isTruncatedShiftCountForLEA(unsigned ShAmt) {
2557 // Left shift instructions can be transformed into load-effective-address
2558 // instructions if we can encode them appropriately.
2559 // A LEA instruction utilizes a SIB byte to encode its scale factor.
2560 // The SIB.scale field is two bits wide which means that we can encode any
2561 // shift amount less than 4.
2562 return ShAmt < 4 && ShAmt > 0;
2563 }
2564
classifyLEAReg(MachineInstr & MI,const MachineOperand & Src,unsigned Opc,bool AllowSP,unsigned & NewSrc,bool & isKill,bool & isUndef,MachineOperand & ImplicitOp) const2565 bool X86InstrInfo::classifyLEAReg(MachineInstr &MI, const MachineOperand &Src,
2566 unsigned Opc, bool AllowSP, unsigned &NewSrc,
2567 bool &isKill, bool &isUndef,
2568 MachineOperand &ImplicitOp) const {
2569 MachineFunction &MF = *MI.getParent()->getParent();
2570 const TargetRegisterClass *RC;
2571 if (AllowSP) {
2572 RC = Opc != X86::LEA32r ? &X86::GR64RegClass : &X86::GR32RegClass;
2573 } else {
2574 RC = Opc != X86::LEA32r ?
2575 &X86::GR64_NOSPRegClass : &X86::GR32_NOSPRegClass;
2576 }
2577 unsigned SrcReg = Src.getReg();
2578
2579 // For both LEA64 and LEA32 the register already has essentially the right
2580 // type (32-bit or 64-bit) we may just need to forbid SP.
2581 if (Opc != X86::LEA64_32r) {
2582 NewSrc = SrcReg;
2583 isKill = Src.isKill();
2584 isUndef = Src.isUndef();
2585
2586 if (TargetRegisterInfo::isVirtualRegister(NewSrc) &&
2587 !MF.getRegInfo().constrainRegClass(NewSrc, RC))
2588 return false;
2589
2590 return true;
2591 }
2592
2593 // This is for an LEA64_32r and incoming registers are 32-bit. One way or
2594 // another we need to add 64-bit registers to the final MI.
2595 if (TargetRegisterInfo::isPhysicalRegister(SrcReg)) {
2596 ImplicitOp = Src;
2597 ImplicitOp.setImplicit();
2598
2599 NewSrc = getX86SubSuperRegister(Src.getReg(), 64);
2600 MachineBasicBlock::LivenessQueryResult LQR =
2601 MI.getParent()->computeRegisterLiveness(&getRegisterInfo(), NewSrc, MI);
2602
2603 switch (LQR) {
2604 case MachineBasicBlock::LQR_Unknown:
2605 // We can't give sane liveness flags to the instruction, abandon LEA
2606 // formation.
2607 return false;
2608 case MachineBasicBlock::LQR_Live:
2609 isKill = MI.killsRegister(SrcReg);
2610 isUndef = false;
2611 break;
2612 default:
2613 // The physreg itself is dead, so we have to use it as an <undef>.
2614 isKill = false;
2615 isUndef = true;
2616 break;
2617 }
2618 } else {
2619 // Virtual register of the wrong class, we have to create a temporary 64-bit
2620 // vreg to feed into the LEA.
2621 NewSrc = MF.getRegInfo().createVirtualRegister(RC);
2622 BuildMI(*MI.getParent(), MI, MI.getDebugLoc(), get(TargetOpcode::COPY))
2623 .addReg(NewSrc, RegState::Define | RegState::Undef, X86::sub_32bit)
2624 .addOperand(Src);
2625
2626 // Which is obviously going to be dead after we're done with it.
2627 isKill = true;
2628 isUndef = false;
2629 }
2630
2631 // We've set all the parameters without issue.
2632 return true;
2633 }
2634
2635 /// Helper for convertToThreeAddress when 16-bit LEA is disabled, use 32-bit
2636 /// LEA to form 3-address code by promoting to a 32-bit superregister and then
2637 /// truncating back down to a 16-bit subregister.
convertToThreeAddressWithLEA(unsigned MIOpc,MachineFunction::iterator & MFI,MachineInstr & MI,LiveVariables * LV) const2638 MachineInstr *X86InstrInfo::convertToThreeAddressWithLEA(
2639 unsigned MIOpc, MachineFunction::iterator &MFI, MachineInstr &MI,
2640 LiveVariables *LV) const {
2641 MachineBasicBlock::iterator MBBI = MI.getIterator();
2642 unsigned Dest = MI.getOperand(0).getReg();
2643 unsigned Src = MI.getOperand(1).getReg();
2644 bool isDead = MI.getOperand(0).isDead();
2645 bool isKill = MI.getOperand(1).isKill();
2646
2647 MachineRegisterInfo &RegInfo = MFI->getParent()->getRegInfo();
2648 unsigned leaOutReg = RegInfo.createVirtualRegister(&X86::GR32RegClass);
2649 unsigned Opc, leaInReg;
2650 if (Subtarget.is64Bit()) {
2651 Opc = X86::LEA64_32r;
2652 leaInReg = RegInfo.createVirtualRegister(&X86::GR64_NOSPRegClass);
2653 } else {
2654 Opc = X86::LEA32r;
2655 leaInReg = RegInfo.createVirtualRegister(&X86::GR32_NOSPRegClass);
2656 }
2657
2658 // Build and insert into an implicit UNDEF value. This is OK because
2659 // well be shifting and then extracting the lower 16-bits.
2660 // This has the potential to cause partial register stall. e.g.
2661 // movw (%rbp,%rcx,2), %dx
2662 // leal -65(%rdx), %esi
2663 // But testing has shown this *does* help performance in 64-bit mode (at
2664 // least on modern x86 machines).
2665 BuildMI(*MFI, MBBI, MI.getDebugLoc(), get(X86::IMPLICIT_DEF), leaInReg);
2666 MachineInstr *InsMI =
2667 BuildMI(*MFI, MBBI, MI.getDebugLoc(), get(TargetOpcode::COPY))
2668 .addReg(leaInReg, RegState::Define, X86::sub_16bit)
2669 .addReg(Src, getKillRegState(isKill));
2670
2671 MachineInstrBuilder MIB =
2672 BuildMI(*MFI, MBBI, MI.getDebugLoc(), get(Opc), leaOutReg);
2673 switch (MIOpc) {
2674 default: llvm_unreachable("Unreachable!");
2675 case X86::SHL16ri: {
2676 unsigned ShAmt = MI.getOperand(2).getImm();
2677 MIB.addReg(0).addImm(1ULL << ShAmt)
2678 .addReg(leaInReg, RegState::Kill).addImm(0).addReg(0);
2679 break;
2680 }
2681 case X86::INC16r:
2682 addRegOffset(MIB, leaInReg, true, 1);
2683 break;
2684 case X86::DEC16r:
2685 addRegOffset(MIB, leaInReg, true, -1);
2686 break;
2687 case X86::ADD16ri:
2688 case X86::ADD16ri8:
2689 case X86::ADD16ri_DB:
2690 case X86::ADD16ri8_DB:
2691 addRegOffset(MIB, leaInReg, true, MI.getOperand(2).getImm());
2692 break;
2693 case X86::ADD16rr:
2694 case X86::ADD16rr_DB: {
2695 unsigned Src2 = MI.getOperand(2).getReg();
2696 bool isKill2 = MI.getOperand(2).isKill();
2697 unsigned leaInReg2 = 0;
2698 MachineInstr *InsMI2 = nullptr;
2699 if (Src == Src2) {
2700 // ADD16rr %reg1028<kill>, %reg1028
2701 // just a single insert_subreg.
2702 addRegReg(MIB, leaInReg, true, leaInReg, false);
2703 } else {
2704 if (Subtarget.is64Bit())
2705 leaInReg2 = RegInfo.createVirtualRegister(&X86::GR64_NOSPRegClass);
2706 else
2707 leaInReg2 = RegInfo.createVirtualRegister(&X86::GR32_NOSPRegClass);
2708 // Build and insert into an implicit UNDEF value. This is OK because
2709 // well be shifting and then extracting the lower 16-bits.
2710 BuildMI(*MFI, &*MIB, MI.getDebugLoc(), get(X86::IMPLICIT_DEF), leaInReg2);
2711 InsMI2 = BuildMI(*MFI, &*MIB, MI.getDebugLoc(), get(TargetOpcode::COPY))
2712 .addReg(leaInReg2, RegState::Define, X86::sub_16bit)
2713 .addReg(Src2, getKillRegState(isKill2));
2714 addRegReg(MIB, leaInReg, true, leaInReg2, true);
2715 }
2716 if (LV && isKill2 && InsMI2)
2717 LV->replaceKillInstruction(Src2, MI, *InsMI2);
2718 break;
2719 }
2720 }
2721
2722 MachineInstr *NewMI = MIB;
2723 MachineInstr *ExtMI =
2724 BuildMI(*MFI, MBBI, MI.getDebugLoc(), get(TargetOpcode::COPY))
2725 .addReg(Dest, RegState::Define | getDeadRegState(isDead))
2726 .addReg(leaOutReg, RegState::Kill, X86::sub_16bit);
2727
2728 if (LV) {
2729 // Update live variables
2730 LV->getVarInfo(leaInReg).Kills.push_back(NewMI);
2731 LV->getVarInfo(leaOutReg).Kills.push_back(ExtMI);
2732 if (isKill)
2733 LV->replaceKillInstruction(Src, MI, *InsMI);
2734 if (isDead)
2735 LV->replaceKillInstruction(Dest, MI, *ExtMI);
2736 }
2737
2738 return ExtMI;
2739 }
2740
2741 /// This method must be implemented by targets that
2742 /// set the M_CONVERTIBLE_TO_3_ADDR flag. When this flag is set, the target
2743 /// may be able to convert a two-address instruction into a true
2744 /// three-address instruction on demand. This allows the X86 target (for
2745 /// example) to convert ADD and SHL instructions into LEA instructions if they
2746 /// would require register copies due to two-addressness.
2747 ///
2748 /// This method returns a null pointer if the transformation cannot be
2749 /// performed, otherwise it returns the new instruction.
2750 ///
2751 MachineInstr *
convertToThreeAddress(MachineFunction::iterator & MFI,MachineInstr & MI,LiveVariables * LV) const2752 X86InstrInfo::convertToThreeAddress(MachineFunction::iterator &MFI,
2753 MachineInstr &MI, LiveVariables *LV) const {
2754 // The following opcodes also sets the condition code register(s). Only
2755 // convert them to equivalent lea if the condition code register def's
2756 // are dead!
2757 if (hasLiveCondCodeDef(MI))
2758 return nullptr;
2759
2760 MachineFunction &MF = *MI.getParent()->getParent();
2761 // All instructions input are two-addr instructions. Get the known operands.
2762 const MachineOperand &Dest = MI.getOperand(0);
2763 const MachineOperand &Src = MI.getOperand(1);
2764
2765 MachineInstr *NewMI = nullptr;
2766 // FIXME: 16-bit LEA's are really slow on Athlons, but not bad on P4's. When
2767 // we have better subtarget support, enable the 16-bit LEA generation here.
2768 // 16-bit LEA is also slow on Core2.
2769 bool DisableLEA16 = true;
2770 bool is64Bit = Subtarget.is64Bit();
2771
2772 unsigned MIOpc = MI.getOpcode();
2773 switch (MIOpc) {
2774 default: return nullptr;
2775 case X86::SHL64ri: {
2776 assert(MI.getNumOperands() >= 3 && "Unknown shift instruction!");
2777 unsigned ShAmt = getTruncatedShiftCount(MI, 2);
2778 if (!isTruncatedShiftCountForLEA(ShAmt)) return nullptr;
2779
2780 // LEA can't handle RSP.
2781 if (TargetRegisterInfo::isVirtualRegister(Src.getReg()) &&
2782 !MF.getRegInfo().constrainRegClass(Src.getReg(),
2783 &X86::GR64_NOSPRegClass))
2784 return nullptr;
2785
2786 NewMI = BuildMI(MF, MI.getDebugLoc(), get(X86::LEA64r))
2787 .addOperand(Dest)
2788 .addReg(0)
2789 .addImm(1ULL << ShAmt)
2790 .addOperand(Src)
2791 .addImm(0)
2792 .addReg(0);
2793 break;
2794 }
2795 case X86::SHL32ri: {
2796 assert(MI.getNumOperands() >= 3 && "Unknown shift instruction!");
2797 unsigned ShAmt = getTruncatedShiftCount(MI, 2);
2798 if (!isTruncatedShiftCountForLEA(ShAmt)) return nullptr;
2799
2800 unsigned Opc = is64Bit ? X86::LEA64_32r : X86::LEA32r;
2801
2802 // LEA can't handle ESP.
2803 bool isKill, isUndef;
2804 unsigned SrcReg;
2805 MachineOperand ImplicitOp = MachineOperand::CreateReg(0, false);
2806 if (!classifyLEAReg(MI, Src, Opc, /*AllowSP=*/ false,
2807 SrcReg, isKill, isUndef, ImplicitOp))
2808 return nullptr;
2809
2810 MachineInstrBuilder MIB =
2811 BuildMI(MF, MI.getDebugLoc(), get(Opc))
2812 .addOperand(Dest)
2813 .addReg(0)
2814 .addImm(1ULL << ShAmt)
2815 .addReg(SrcReg, getKillRegState(isKill) | getUndefRegState(isUndef))
2816 .addImm(0)
2817 .addReg(0);
2818 if (ImplicitOp.getReg() != 0)
2819 MIB.addOperand(ImplicitOp);
2820 NewMI = MIB;
2821
2822 break;
2823 }
2824 case X86::SHL16ri: {
2825 assert(MI.getNumOperands() >= 3 && "Unknown shift instruction!");
2826 unsigned ShAmt = getTruncatedShiftCount(MI, 2);
2827 if (!isTruncatedShiftCountForLEA(ShAmt)) return nullptr;
2828
2829 if (DisableLEA16)
2830 return is64Bit ? convertToThreeAddressWithLEA(MIOpc, MFI, MI, LV)
2831 : nullptr;
2832 NewMI = BuildMI(MF, MI.getDebugLoc(), get(X86::LEA16r))
2833 .addOperand(Dest)
2834 .addReg(0)
2835 .addImm(1ULL << ShAmt)
2836 .addOperand(Src)
2837 .addImm(0)
2838 .addReg(0);
2839 break;
2840 }
2841 case X86::INC64r:
2842 case X86::INC32r: {
2843 assert(MI.getNumOperands() >= 2 && "Unknown inc instruction!");
2844 unsigned Opc = MIOpc == X86::INC64r ? X86::LEA64r
2845 : (is64Bit ? X86::LEA64_32r : X86::LEA32r);
2846 bool isKill, isUndef;
2847 unsigned SrcReg;
2848 MachineOperand ImplicitOp = MachineOperand::CreateReg(0, false);
2849 if (!classifyLEAReg(MI, Src, Opc, /*AllowSP=*/ false,
2850 SrcReg, isKill, isUndef, ImplicitOp))
2851 return nullptr;
2852
2853 MachineInstrBuilder MIB =
2854 BuildMI(MF, MI.getDebugLoc(), get(Opc))
2855 .addOperand(Dest)
2856 .addReg(SrcReg,
2857 getKillRegState(isKill) | getUndefRegState(isUndef));
2858 if (ImplicitOp.getReg() != 0)
2859 MIB.addOperand(ImplicitOp);
2860
2861 NewMI = addOffset(MIB, 1);
2862 break;
2863 }
2864 case X86::INC16r:
2865 if (DisableLEA16)
2866 return is64Bit ? convertToThreeAddressWithLEA(MIOpc, MFI, MI, LV)
2867 : nullptr;
2868 assert(MI.getNumOperands() >= 2 && "Unknown inc instruction!");
2869 NewMI = addOffset(BuildMI(MF, MI.getDebugLoc(), get(X86::LEA16r))
2870 .addOperand(Dest)
2871 .addOperand(Src),
2872 1);
2873 break;
2874 case X86::DEC64r:
2875 case X86::DEC32r: {
2876 assert(MI.getNumOperands() >= 2 && "Unknown dec instruction!");
2877 unsigned Opc = MIOpc == X86::DEC64r ? X86::LEA64r
2878 : (is64Bit ? X86::LEA64_32r : X86::LEA32r);
2879
2880 bool isKill, isUndef;
2881 unsigned SrcReg;
2882 MachineOperand ImplicitOp = MachineOperand::CreateReg(0, false);
2883 if (!classifyLEAReg(MI, Src, Opc, /*AllowSP=*/ false,
2884 SrcReg, isKill, isUndef, ImplicitOp))
2885 return nullptr;
2886
2887 MachineInstrBuilder MIB = BuildMI(MF, MI.getDebugLoc(), get(Opc))
2888 .addOperand(Dest)
2889 .addReg(SrcReg, getUndefRegState(isUndef) |
2890 getKillRegState(isKill));
2891 if (ImplicitOp.getReg() != 0)
2892 MIB.addOperand(ImplicitOp);
2893
2894 NewMI = addOffset(MIB, -1);
2895
2896 break;
2897 }
2898 case X86::DEC16r:
2899 if (DisableLEA16)
2900 return is64Bit ? convertToThreeAddressWithLEA(MIOpc, MFI, MI, LV)
2901 : nullptr;
2902 assert(MI.getNumOperands() >= 2 && "Unknown dec instruction!");
2903 NewMI = addOffset(BuildMI(MF, MI.getDebugLoc(), get(X86::LEA16r))
2904 .addOperand(Dest)
2905 .addOperand(Src),
2906 -1);
2907 break;
2908 case X86::ADD64rr:
2909 case X86::ADD64rr_DB:
2910 case X86::ADD32rr:
2911 case X86::ADD32rr_DB: {
2912 assert(MI.getNumOperands() >= 3 && "Unknown add instruction!");
2913 unsigned Opc;
2914 if (MIOpc == X86::ADD64rr || MIOpc == X86::ADD64rr_DB)
2915 Opc = X86::LEA64r;
2916 else
2917 Opc = is64Bit ? X86::LEA64_32r : X86::LEA32r;
2918
2919 bool isKill, isUndef;
2920 unsigned SrcReg;
2921 MachineOperand ImplicitOp = MachineOperand::CreateReg(0, false);
2922 if (!classifyLEAReg(MI, Src, Opc, /*AllowSP=*/ true,
2923 SrcReg, isKill, isUndef, ImplicitOp))
2924 return nullptr;
2925
2926 const MachineOperand &Src2 = MI.getOperand(2);
2927 bool isKill2, isUndef2;
2928 unsigned SrcReg2;
2929 MachineOperand ImplicitOp2 = MachineOperand::CreateReg(0, false);
2930 if (!classifyLEAReg(MI, Src2, Opc, /*AllowSP=*/ false,
2931 SrcReg2, isKill2, isUndef2, ImplicitOp2))
2932 return nullptr;
2933
2934 MachineInstrBuilder MIB =
2935 BuildMI(MF, MI.getDebugLoc(), get(Opc)).addOperand(Dest);
2936 if (ImplicitOp.getReg() != 0)
2937 MIB.addOperand(ImplicitOp);
2938 if (ImplicitOp2.getReg() != 0)
2939 MIB.addOperand(ImplicitOp2);
2940
2941 NewMI = addRegReg(MIB, SrcReg, isKill, SrcReg2, isKill2);
2942
2943 // Preserve undefness of the operands.
2944 NewMI->getOperand(1).setIsUndef(isUndef);
2945 NewMI->getOperand(3).setIsUndef(isUndef2);
2946
2947 if (LV && Src2.isKill())
2948 LV->replaceKillInstruction(SrcReg2, MI, *NewMI);
2949 break;
2950 }
2951 case X86::ADD16rr:
2952 case X86::ADD16rr_DB: {
2953 if (DisableLEA16)
2954 return is64Bit ? convertToThreeAddressWithLEA(MIOpc, MFI, MI, LV)
2955 : nullptr;
2956 assert(MI.getNumOperands() >= 3 && "Unknown add instruction!");
2957 unsigned Src2 = MI.getOperand(2).getReg();
2958 bool isKill2 = MI.getOperand(2).isKill();
2959 NewMI = addRegReg(
2960 BuildMI(MF, MI.getDebugLoc(), get(X86::LEA16r)).addOperand(Dest),
2961 Src.getReg(), Src.isKill(), Src2, isKill2);
2962
2963 // Preserve undefness of the operands.
2964 bool isUndef = MI.getOperand(1).isUndef();
2965 bool isUndef2 = MI.getOperand(2).isUndef();
2966 NewMI->getOperand(1).setIsUndef(isUndef);
2967 NewMI->getOperand(3).setIsUndef(isUndef2);
2968
2969 if (LV && isKill2)
2970 LV->replaceKillInstruction(Src2, MI, *NewMI);
2971 break;
2972 }
2973 case X86::ADD64ri32:
2974 case X86::ADD64ri8:
2975 case X86::ADD64ri32_DB:
2976 case X86::ADD64ri8_DB:
2977 assert(MI.getNumOperands() >= 3 && "Unknown add instruction!");
2978 NewMI = addOffset(BuildMI(MF, MI.getDebugLoc(), get(X86::LEA64r))
2979 .addOperand(Dest)
2980 .addOperand(Src),
2981 MI.getOperand(2).getImm());
2982 break;
2983 case X86::ADD32ri:
2984 case X86::ADD32ri8:
2985 case X86::ADD32ri_DB:
2986 case X86::ADD32ri8_DB: {
2987 assert(MI.getNumOperands() >= 3 && "Unknown add instruction!");
2988 unsigned Opc = is64Bit ? X86::LEA64_32r : X86::LEA32r;
2989
2990 bool isKill, isUndef;
2991 unsigned SrcReg;
2992 MachineOperand ImplicitOp = MachineOperand::CreateReg(0, false);
2993 if (!classifyLEAReg(MI, Src, Opc, /*AllowSP=*/ true,
2994 SrcReg, isKill, isUndef, ImplicitOp))
2995 return nullptr;
2996
2997 MachineInstrBuilder MIB = BuildMI(MF, MI.getDebugLoc(), get(Opc))
2998 .addOperand(Dest)
2999 .addReg(SrcReg, getUndefRegState(isUndef) |
3000 getKillRegState(isKill));
3001 if (ImplicitOp.getReg() != 0)
3002 MIB.addOperand(ImplicitOp);
3003
3004 NewMI = addOffset(MIB, MI.getOperand(2).getImm());
3005 break;
3006 }
3007 case X86::ADD16ri:
3008 case X86::ADD16ri8:
3009 case X86::ADD16ri_DB:
3010 case X86::ADD16ri8_DB:
3011 if (DisableLEA16)
3012 return is64Bit ? convertToThreeAddressWithLEA(MIOpc, MFI, MI, LV)
3013 : nullptr;
3014 assert(MI.getNumOperands() >= 3 && "Unknown add instruction!");
3015 NewMI = addOffset(BuildMI(MF, MI.getDebugLoc(), get(X86::LEA16r))
3016 .addOperand(Dest)
3017 .addOperand(Src),
3018 MI.getOperand(2).getImm());
3019 break;
3020 }
3021
3022 if (!NewMI) return nullptr;
3023
3024 if (LV) { // Update live variables
3025 if (Src.isKill())
3026 LV->replaceKillInstruction(Src.getReg(), MI, *NewMI);
3027 if (Dest.isDead())
3028 LV->replaceKillInstruction(Dest.getReg(), MI, *NewMI);
3029 }
3030
3031 MFI->insert(MI.getIterator(), NewMI); // Insert the new inst
3032 return NewMI;
3033 }
3034
3035 /// Returns true if the given instruction opcode is FMA3.
3036 /// Otherwise, returns false.
3037 /// The second parameter is optional and is used as the second return from
3038 /// the function. It is set to true if the given instruction has FMA3 opcode
3039 /// that is used for lowering of scalar FMA intrinsics, and it is set to false
3040 /// otherwise.
isFMA3(unsigned Opcode,bool * IsIntrinsic=nullptr)3041 static bool isFMA3(unsigned Opcode, bool *IsIntrinsic = nullptr) {
3042 if (IsIntrinsic)
3043 *IsIntrinsic = false;
3044
3045 switch (Opcode) {
3046 case X86::VFMADDSDr132r: case X86::VFMADDSDr132m:
3047 case X86::VFMADDSSr132r: case X86::VFMADDSSr132m:
3048 case X86::VFMSUBSDr132r: case X86::VFMSUBSDr132m:
3049 case X86::VFMSUBSSr132r: case X86::VFMSUBSSr132m:
3050 case X86::VFNMADDSDr132r: case X86::VFNMADDSDr132m:
3051 case X86::VFNMADDSSr132r: case X86::VFNMADDSSr132m:
3052 case X86::VFNMSUBSDr132r: case X86::VFNMSUBSDr132m:
3053 case X86::VFNMSUBSSr132r: case X86::VFNMSUBSSr132m:
3054
3055 case X86::VFMADDSDr213r: case X86::VFMADDSDr213m:
3056 case X86::VFMADDSSr213r: case X86::VFMADDSSr213m:
3057 case X86::VFMSUBSDr213r: case X86::VFMSUBSDr213m:
3058 case X86::VFMSUBSSr213r: case X86::VFMSUBSSr213m:
3059 case X86::VFNMADDSDr213r: case X86::VFNMADDSDr213m:
3060 case X86::VFNMADDSSr213r: case X86::VFNMADDSSr213m:
3061 case X86::VFNMSUBSDr213r: case X86::VFNMSUBSDr213m:
3062 case X86::VFNMSUBSSr213r: case X86::VFNMSUBSSr213m:
3063
3064 case X86::VFMADDSDr231r: case X86::VFMADDSDr231m:
3065 case X86::VFMADDSSr231r: case X86::VFMADDSSr231m:
3066 case X86::VFMSUBSDr231r: case X86::VFMSUBSDr231m:
3067 case X86::VFMSUBSSr231r: case X86::VFMSUBSSr231m:
3068 case X86::VFNMADDSDr231r: case X86::VFNMADDSDr231m:
3069 case X86::VFNMADDSSr231r: case X86::VFNMADDSSr231m:
3070 case X86::VFNMSUBSDr231r: case X86::VFNMSUBSDr231m:
3071 case X86::VFNMSUBSSr231r: case X86::VFNMSUBSSr231m:
3072
3073 case X86::VFMADDSUBPDr132r: case X86::VFMADDSUBPDr132m:
3074 case X86::VFMADDSUBPSr132r: case X86::VFMADDSUBPSr132m:
3075 case X86::VFMSUBADDPDr132r: case X86::VFMSUBADDPDr132m:
3076 case X86::VFMSUBADDPSr132r: case X86::VFMSUBADDPSr132m:
3077 case X86::VFMADDSUBPDr132rY: case X86::VFMADDSUBPDr132mY:
3078 case X86::VFMADDSUBPSr132rY: case X86::VFMADDSUBPSr132mY:
3079 case X86::VFMSUBADDPDr132rY: case X86::VFMSUBADDPDr132mY:
3080 case X86::VFMSUBADDPSr132rY: case X86::VFMSUBADDPSr132mY:
3081
3082 case X86::VFMADDPDr132r: case X86::VFMADDPDr132m:
3083 case X86::VFMADDPSr132r: case X86::VFMADDPSr132m:
3084 case X86::VFMSUBPDr132r: case X86::VFMSUBPDr132m:
3085 case X86::VFMSUBPSr132r: case X86::VFMSUBPSr132m:
3086 case X86::VFNMADDPDr132r: case X86::VFNMADDPDr132m:
3087 case X86::VFNMADDPSr132r: case X86::VFNMADDPSr132m:
3088 case X86::VFNMSUBPDr132r: case X86::VFNMSUBPDr132m:
3089 case X86::VFNMSUBPSr132r: case X86::VFNMSUBPSr132m:
3090 case X86::VFMADDPDr132rY: case X86::VFMADDPDr132mY:
3091 case X86::VFMADDPSr132rY: case X86::VFMADDPSr132mY:
3092 case X86::VFMSUBPDr132rY: case X86::VFMSUBPDr132mY:
3093 case X86::VFMSUBPSr132rY: case X86::VFMSUBPSr132mY:
3094 case X86::VFNMADDPDr132rY: case X86::VFNMADDPDr132mY:
3095 case X86::VFNMADDPSr132rY: case X86::VFNMADDPSr132mY:
3096 case X86::VFNMSUBPDr132rY: case X86::VFNMSUBPDr132mY:
3097 case X86::VFNMSUBPSr132rY: case X86::VFNMSUBPSr132mY:
3098
3099 case X86::VFMADDSUBPDr213r: case X86::VFMADDSUBPDr213m:
3100 case X86::VFMADDSUBPSr213r: case X86::VFMADDSUBPSr213m:
3101 case X86::VFMSUBADDPDr213r: case X86::VFMSUBADDPDr213m:
3102 case X86::VFMSUBADDPSr213r: case X86::VFMSUBADDPSr213m:
3103 case X86::VFMADDSUBPDr213rY: case X86::VFMADDSUBPDr213mY:
3104 case X86::VFMADDSUBPSr213rY: case X86::VFMADDSUBPSr213mY:
3105 case X86::VFMSUBADDPDr213rY: case X86::VFMSUBADDPDr213mY:
3106 case X86::VFMSUBADDPSr213rY: case X86::VFMSUBADDPSr213mY:
3107
3108 case X86::VFMADDPDr213r: case X86::VFMADDPDr213m:
3109 case X86::VFMADDPSr213r: case X86::VFMADDPSr213m:
3110 case X86::VFMSUBPDr213r: case X86::VFMSUBPDr213m:
3111 case X86::VFMSUBPSr213r: case X86::VFMSUBPSr213m:
3112 case X86::VFNMADDPDr213r: case X86::VFNMADDPDr213m:
3113 case X86::VFNMADDPSr213r: case X86::VFNMADDPSr213m:
3114 case X86::VFNMSUBPDr213r: case X86::VFNMSUBPDr213m:
3115 case X86::VFNMSUBPSr213r: case X86::VFNMSUBPSr213m:
3116 case X86::VFMADDPDr213rY: case X86::VFMADDPDr213mY:
3117 case X86::VFMADDPSr213rY: case X86::VFMADDPSr213mY:
3118 case X86::VFMSUBPDr213rY: case X86::VFMSUBPDr213mY:
3119 case X86::VFMSUBPSr213rY: case X86::VFMSUBPSr213mY:
3120 case X86::VFNMADDPDr213rY: case X86::VFNMADDPDr213mY:
3121 case X86::VFNMADDPSr213rY: case X86::VFNMADDPSr213mY:
3122 case X86::VFNMSUBPDr213rY: case X86::VFNMSUBPDr213mY:
3123 case X86::VFNMSUBPSr213rY: case X86::VFNMSUBPSr213mY:
3124
3125 case X86::VFMADDSUBPDr231r: case X86::VFMADDSUBPDr231m:
3126 case X86::VFMADDSUBPSr231r: case X86::VFMADDSUBPSr231m:
3127 case X86::VFMSUBADDPDr231r: case X86::VFMSUBADDPDr231m:
3128 case X86::VFMSUBADDPSr231r: case X86::VFMSUBADDPSr231m:
3129 case X86::VFMADDSUBPDr231rY: case X86::VFMADDSUBPDr231mY:
3130 case X86::VFMADDSUBPSr231rY: case X86::VFMADDSUBPSr231mY:
3131 case X86::VFMSUBADDPDr231rY: case X86::VFMSUBADDPDr231mY:
3132 case X86::VFMSUBADDPSr231rY: case X86::VFMSUBADDPSr231mY:
3133
3134 case X86::VFMADDPDr231r: case X86::VFMADDPDr231m:
3135 case X86::VFMADDPSr231r: case X86::VFMADDPSr231m:
3136 case X86::VFMSUBPDr231r: case X86::VFMSUBPDr231m:
3137 case X86::VFMSUBPSr231r: case X86::VFMSUBPSr231m:
3138 case X86::VFNMADDPDr231r: case X86::VFNMADDPDr231m:
3139 case X86::VFNMADDPSr231r: case X86::VFNMADDPSr231m:
3140 case X86::VFNMSUBPDr231r: case X86::VFNMSUBPDr231m:
3141 case X86::VFNMSUBPSr231r: case X86::VFNMSUBPSr231m:
3142 case X86::VFMADDPDr231rY: case X86::VFMADDPDr231mY:
3143 case X86::VFMADDPSr231rY: case X86::VFMADDPSr231mY:
3144 case X86::VFMSUBPDr231rY: case X86::VFMSUBPDr231mY:
3145 case X86::VFMSUBPSr231rY: case X86::VFMSUBPSr231mY:
3146 case X86::VFNMADDPDr231rY: case X86::VFNMADDPDr231mY:
3147 case X86::VFNMADDPSr231rY: case X86::VFNMADDPSr231mY:
3148 case X86::VFNMSUBPDr231rY: case X86::VFNMSUBPDr231mY:
3149 case X86::VFNMSUBPSr231rY: case X86::VFNMSUBPSr231mY:
3150 return true;
3151
3152 case X86::VFMADDSDr132r_Int: case X86::VFMADDSDr132m_Int:
3153 case X86::VFMADDSSr132r_Int: case X86::VFMADDSSr132m_Int:
3154 case X86::VFMSUBSDr132r_Int: case X86::VFMSUBSDr132m_Int:
3155 case X86::VFMSUBSSr132r_Int: case X86::VFMSUBSSr132m_Int:
3156 case X86::VFNMADDSDr132r_Int: case X86::VFNMADDSDr132m_Int:
3157 case X86::VFNMADDSSr132r_Int: case X86::VFNMADDSSr132m_Int:
3158 case X86::VFNMSUBSDr132r_Int: case X86::VFNMSUBSDr132m_Int:
3159 case X86::VFNMSUBSSr132r_Int: case X86::VFNMSUBSSr132m_Int:
3160
3161 case X86::VFMADDSDr213r_Int: case X86::VFMADDSDr213m_Int:
3162 case X86::VFMADDSSr213r_Int: case X86::VFMADDSSr213m_Int:
3163 case X86::VFMSUBSDr213r_Int: case X86::VFMSUBSDr213m_Int:
3164 case X86::VFMSUBSSr213r_Int: case X86::VFMSUBSSr213m_Int:
3165 case X86::VFNMADDSDr213r_Int: case X86::VFNMADDSDr213m_Int:
3166 case X86::VFNMADDSSr213r_Int: case X86::VFNMADDSSr213m_Int:
3167 case X86::VFNMSUBSDr213r_Int: case X86::VFNMSUBSDr213m_Int:
3168 case X86::VFNMSUBSSr213r_Int: case X86::VFNMSUBSSr213m_Int:
3169
3170 case X86::VFMADDSDr231r_Int: case X86::VFMADDSDr231m_Int:
3171 case X86::VFMADDSSr231r_Int: case X86::VFMADDSSr231m_Int:
3172 case X86::VFMSUBSDr231r_Int: case X86::VFMSUBSDr231m_Int:
3173 case X86::VFMSUBSSr231r_Int: case X86::VFMSUBSSr231m_Int:
3174 case X86::VFNMADDSDr231r_Int: case X86::VFNMADDSDr231m_Int:
3175 case X86::VFNMADDSSr231r_Int: case X86::VFNMADDSSr231m_Int:
3176 case X86::VFNMSUBSDr231r_Int: case X86::VFNMSUBSDr231m_Int:
3177 case X86::VFNMSUBSSr231r_Int: case X86::VFNMSUBSSr231m_Int:
3178 if (IsIntrinsic)
3179 *IsIntrinsic = true;
3180 return true;
3181 default:
3182 return false;
3183 }
3184 llvm_unreachable("Opcode not handled by the switch");
3185 }
3186
commuteInstructionImpl(MachineInstr & MI,bool NewMI,unsigned OpIdx1,unsigned OpIdx2) const3187 MachineInstr *X86InstrInfo::commuteInstructionImpl(MachineInstr &MI, bool NewMI,
3188 unsigned OpIdx1,
3189 unsigned OpIdx2) const {
3190 auto cloneIfNew = [NewMI](MachineInstr &MI) -> MachineInstr & {
3191 if (NewMI)
3192 return *MI.getParent()->getParent()->CloneMachineInstr(&MI);
3193 return MI;
3194 };
3195
3196 switch (MI.getOpcode()) {
3197 case X86::SHRD16rri8: // A = SHRD16rri8 B, C, I -> A = SHLD16rri8 C, B, (16-I)
3198 case X86::SHLD16rri8: // A = SHLD16rri8 B, C, I -> A = SHRD16rri8 C, B, (16-I)
3199 case X86::SHRD32rri8: // A = SHRD32rri8 B, C, I -> A = SHLD32rri8 C, B, (32-I)
3200 case X86::SHLD32rri8: // A = SHLD32rri8 B, C, I -> A = SHRD32rri8 C, B, (32-I)
3201 case X86::SHRD64rri8: // A = SHRD64rri8 B, C, I -> A = SHLD64rri8 C, B, (64-I)
3202 case X86::SHLD64rri8:{// A = SHLD64rri8 B, C, I -> A = SHRD64rri8 C, B, (64-I)
3203 unsigned Opc;
3204 unsigned Size;
3205 switch (MI.getOpcode()) {
3206 default: llvm_unreachable("Unreachable!");
3207 case X86::SHRD16rri8: Size = 16; Opc = X86::SHLD16rri8; break;
3208 case X86::SHLD16rri8: Size = 16; Opc = X86::SHRD16rri8; break;
3209 case X86::SHRD32rri8: Size = 32; Opc = X86::SHLD32rri8; break;
3210 case X86::SHLD32rri8: Size = 32; Opc = X86::SHRD32rri8; break;
3211 case X86::SHRD64rri8: Size = 64; Opc = X86::SHLD64rri8; break;
3212 case X86::SHLD64rri8: Size = 64; Opc = X86::SHRD64rri8; break;
3213 }
3214 unsigned Amt = MI.getOperand(3).getImm();
3215 auto &WorkingMI = cloneIfNew(MI);
3216 WorkingMI.setDesc(get(Opc));
3217 WorkingMI.getOperand(3).setImm(Size - Amt);
3218 return TargetInstrInfo::commuteInstructionImpl(WorkingMI, /*NewMI=*/false,
3219 OpIdx1, OpIdx2);
3220 }
3221 case X86::BLENDPDrri:
3222 case X86::BLENDPSrri:
3223 case X86::PBLENDWrri:
3224 case X86::VBLENDPDrri:
3225 case X86::VBLENDPSrri:
3226 case X86::VBLENDPDYrri:
3227 case X86::VBLENDPSYrri:
3228 case X86::VPBLENDDrri:
3229 case X86::VPBLENDWrri:
3230 case X86::VPBLENDDYrri:
3231 case X86::VPBLENDWYrri:{
3232 unsigned Mask;
3233 switch (MI.getOpcode()) {
3234 default: llvm_unreachable("Unreachable!");
3235 case X86::BLENDPDrri: Mask = 0x03; break;
3236 case X86::BLENDPSrri: Mask = 0x0F; break;
3237 case X86::PBLENDWrri: Mask = 0xFF; break;
3238 case X86::VBLENDPDrri: Mask = 0x03; break;
3239 case X86::VBLENDPSrri: Mask = 0x0F; break;
3240 case X86::VBLENDPDYrri: Mask = 0x0F; break;
3241 case X86::VBLENDPSYrri: Mask = 0xFF; break;
3242 case X86::VPBLENDDrri: Mask = 0x0F; break;
3243 case X86::VPBLENDWrri: Mask = 0xFF; break;
3244 case X86::VPBLENDDYrri: Mask = 0xFF; break;
3245 case X86::VPBLENDWYrri: Mask = 0xFF; break;
3246 }
3247 // Only the least significant bits of Imm are used.
3248 unsigned Imm = MI.getOperand(3).getImm() & Mask;
3249 auto &WorkingMI = cloneIfNew(MI);
3250 WorkingMI.getOperand(3).setImm(Mask ^ Imm);
3251 return TargetInstrInfo::commuteInstructionImpl(WorkingMI, /*NewMI=*/false,
3252 OpIdx1, OpIdx2);
3253 }
3254 case X86::PCLMULQDQrr:
3255 case X86::VPCLMULQDQrr:{
3256 // SRC1 64bits = Imm[0] ? SRC1[127:64] : SRC1[63:0]
3257 // SRC2 64bits = Imm[4] ? SRC2[127:64] : SRC2[63:0]
3258 unsigned Imm = MI.getOperand(3).getImm();
3259 unsigned Src1Hi = Imm & 0x01;
3260 unsigned Src2Hi = Imm & 0x10;
3261 auto &WorkingMI = cloneIfNew(MI);
3262 WorkingMI.getOperand(3).setImm((Src1Hi << 4) | (Src2Hi >> 4));
3263 return TargetInstrInfo::commuteInstructionImpl(WorkingMI, /*NewMI=*/false,
3264 OpIdx1, OpIdx2);
3265 }
3266 case X86::CMPPDrri:
3267 case X86::CMPPSrri:
3268 case X86::VCMPPDrri:
3269 case X86::VCMPPSrri:
3270 case X86::VCMPPDYrri:
3271 case X86::VCMPPSYrri: {
3272 // Float comparison can be safely commuted for
3273 // Ordered/Unordered/Equal/NotEqual tests
3274 unsigned Imm = MI.getOperand(3).getImm() & 0x7;
3275 switch (Imm) {
3276 case 0x00: // EQUAL
3277 case 0x03: // UNORDERED
3278 case 0x04: // NOT EQUAL
3279 case 0x07: // ORDERED
3280 return TargetInstrInfo::commuteInstructionImpl(MI, NewMI, OpIdx1, OpIdx2);
3281 default:
3282 return nullptr;
3283 }
3284 }
3285 case X86::VPCOMBri: case X86::VPCOMUBri:
3286 case X86::VPCOMDri: case X86::VPCOMUDri:
3287 case X86::VPCOMQri: case X86::VPCOMUQri:
3288 case X86::VPCOMWri: case X86::VPCOMUWri: {
3289 // Flip comparison mode immediate (if necessary).
3290 unsigned Imm = MI.getOperand(3).getImm() & 0x7;
3291 switch (Imm) {
3292 case 0x00: Imm = 0x02; break; // LT -> GT
3293 case 0x01: Imm = 0x03; break; // LE -> GE
3294 case 0x02: Imm = 0x00; break; // GT -> LT
3295 case 0x03: Imm = 0x01; break; // GE -> LE
3296 case 0x04: // EQ
3297 case 0x05: // NE
3298 case 0x06: // FALSE
3299 case 0x07: // TRUE
3300 default:
3301 break;
3302 }
3303 auto &WorkingMI = cloneIfNew(MI);
3304 WorkingMI.getOperand(3).setImm(Imm);
3305 return TargetInstrInfo::commuteInstructionImpl(WorkingMI, /*NewMI=*/false,
3306 OpIdx1, OpIdx2);
3307 }
3308 case X86::VPERM2F128rr:
3309 case X86::VPERM2I128rr: {
3310 // Flip permute source immediate.
3311 // Imm & 0x02: lo = if set, select Op1.lo/hi else Op0.lo/hi.
3312 // Imm & 0x20: hi = if set, select Op1.lo/hi else Op0.lo/hi.
3313 unsigned Imm = MI.getOperand(3).getImm() & 0xFF;
3314 auto &WorkingMI = cloneIfNew(MI);
3315 WorkingMI.getOperand(3).setImm(Imm ^ 0x22);
3316 return TargetInstrInfo::commuteInstructionImpl(WorkingMI, /*NewMI=*/false,
3317 OpIdx1, OpIdx2);
3318 }
3319 case X86::CMOVB16rr: case X86::CMOVB32rr: case X86::CMOVB64rr:
3320 case X86::CMOVAE16rr: case X86::CMOVAE32rr: case X86::CMOVAE64rr:
3321 case X86::CMOVE16rr: case X86::CMOVE32rr: case X86::CMOVE64rr:
3322 case X86::CMOVNE16rr: case X86::CMOVNE32rr: case X86::CMOVNE64rr:
3323 case X86::CMOVBE16rr: case X86::CMOVBE32rr: case X86::CMOVBE64rr:
3324 case X86::CMOVA16rr: case X86::CMOVA32rr: case X86::CMOVA64rr:
3325 case X86::CMOVL16rr: case X86::CMOVL32rr: case X86::CMOVL64rr:
3326 case X86::CMOVGE16rr: case X86::CMOVGE32rr: case X86::CMOVGE64rr:
3327 case X86::CMOVLE16rr: case X86::CMOVLE32rr: case X86::CMOVLE64rr:
3328 case X86::CMOVG16rr: case X86::CMOVG32rr: case X86::CMOVG64rr:
3329 case X86::CMOVS16rr: case X86::CMOVS32rr: case X86::CMOVS64rr:
3330 case X86::CMOVNS16rr: case X86::CMOVNS32rr: case X86::CMOVNS64rr:
3331 case X86::CMOVP16rr: case X86::CMOVP32rr: case X86::CMOVP64rr:
3332 case X86::CMOVNP16rr: case X86::CMOVNP32rr: case X86::CMOVNP64rr:
3333 case X86::CMOVO16rr: case X86::CMOVO32rr: case X86::CMOVO64rr:
3334 case X86::CMOVNO16rr: case X86::CMOVNO32rr: case X86::CMOVNO64rr: {
3335 unsigned Opc;
3336 switch (MI.getOpcode()) {
3337 default: llvm_unreachable("Unreachable!");
3338 case X86::CMOVB16rr: Opc = X86::CMOVAE16rr; break;
3339 case X86::CMOVB32rr: Opc = X86::CMOVAE32rr; break;
3340 case X86::CMOVB64rr: Opc = X86::CMOVAE64rr; break;
3341 case X86::CMOVAE16rr: Opc = X86::CMOVB16rr; break;
3342 case X86::CMOVAE32rr: Opc = X86::CMOVB32rr; break;
3343 case X86::CMOVAE64rr: Opc = X86::CMOVB64rr; break;
3344 case X86::CMOVE16rr: Opc = X86::CMOVNE16rr; break;
3345 case X86::CMOVE32rr: Opc = X86::CMOVNE32rr; break;
3346 case X86::CMOVE64rr: Opc = X86::CMOVNE64rr; break;
3347 case X86::CMOVNE16rr: Opc = X86::CMOVE16rr; break;
3348 case X86::CMOVNE32rr: Opc = X86::CMOVE32rr; break;
3349 case X86::CMOVNE64rr: Opc = X86::CMOVE64rr; break;
3350 case X86::CMOVBE16rr: Opc = X86::CMOVA16rr; break;
3351 case X86::CMOVBE32rr: Opc = X86::CMOVA32rr; break;
3352 case X86::CMOVBE64rr: Opc = X86::CMOVA64rr; break;
3353 case X86::CMOVA16rr: Opc = X86::CMOVBE16rr; break;
3354 case X86::CMOVA32rr: Opc = X86::CMOVBE32rr; break;
3355 case X86::CMOVA64rr: Opc = X86::CMOVBE64rr; break;
3356 case X86::CMOVL16rr: Opc = X86::CMOVGE16rr; break;
3357 case X86::CMOVL32rr: Opc = X86::CMOVGE32rr; break;
3358 case X86::CMOVL64rr: Opc = X86::CMOVGE64rr; break;
3359 case X86::CMOVGE16rr: Opc = X86::CMOVL16rr; break;
3360 case X86::CMOVGE32rr: Opc = X86::CMOVL32rr; break;
3361 case X86::CMOVGE64rr: Opc = X86::CMOVL64rr; break;
3362 case X86::CMOVLE16rr: Opc = X86::CMOVG16rr; break;
3363 case X86::CMOVLE32rr: Opc = X86::CMOVG32rr; break;
3364 case X86::CMOVLE64rr: Opc = X86::CMOVG64rr; break;
3365 case X86::CMOVG16rr: Opc = X86::CMOVLE16rr; break;
3366 case X86::CMOVG32rr: Opc = X86::CMOVLE32rr; break;
3367 case X86::CMOVG64rr: Opc = X86::CMOVLE64rr; break;
3368 case X86::CMOVS16rr: Opc = X86::CMOVNS16rr; break;
3369 case X86::CMOVS32rr: Opc = X86::CMOVNS32rr; break;
3370 case X86::CMOVS64rr: Opc = X86::CMOVNS64rr; break;
3371 case X86::CMOVNS16rr: Opc = X86::CMOVS16rr; break;
3372 case X86::CMOVNS32rr: Opc = X86::CMOVS32rr; break;
3373 case X86::CMOVNS64rr: Opc = X86::CMOVS64rr; break;
3374 case X86::CMOVP16rr: Opc = X86::CMOVNP16rr; break;
3375 case X86::CMOVP32rr: Opc = X86::CMOVNP32rr; break;
3376 case X86::CMOVP64rr: Opc = X86::CMOVNP64rr; break;
3377 case X86::CMOVNP16rr: Opc = X86::CMOVP16rr; break;
3378 case X86::CMOVNP32rr: Opc = X86::CMOVP32rr; break;
3379 case X86::CMOVNP64rr: Opc = X86::CMOVP64rr; break;
3380 case X86::CMOVO16rr: Opc = X86::CMOVNO16rr; break;
3381 case X86::CMOVO32rr: Opc = X86::CMOVNO32rr; break;
3382 case X86::CMOVO64rr: Opc = X86::CMOVNO64rr; break;
3383 case X86::CMOVNO16rr: Opc = X86::CMOVO16rr; break;
3384 case X86::CMOVNO32rr: Opc = X86::CMOVO32rr; break;
3385 case X86::CMOVNO64rr: Opc = X86::CMOVO64rr; break;
3386 }
3387 auto &WorkingMI = cloneIfNew(MI);
3388 WorkingMI.setDesc(get(Opc));
3389 return TargetInstrInfo::commuteInstructionImpl(WorkingMI, /*NewMI=*/false,
3390 OpIdx1, OpIdx2);
3391 }
3392 default:
3393 if (isFMA3(MI.getOpcode())) {
3394 unsigned Opc = getFMA3OpcodeToCommuteOperands(MI, OpIdx1, OpIdx2);
3395 if (Opc == 0)
3396 return nullptr;
3397 auto &WorkingMI = cloneIfNew(MI);
3398 WorkingMI.setDesc(get(Opc));
3399 return TargetInstrInfo::commuteInstructionImpl(WorkingMI, /*NewMI=*/false,
3400 OpIdx1, OpIdx2);
3401 }
3402
3403 return TargetInstrInfo::commuteInstructionImpl(MI, NewMI, OpIdx1, OpIdx2);
3404 }
3405 }
3406
findFMA3CommutedOpIndices(MachineInstr & MI,unsigned & SrcOpIdx1,unsigned & SrcOpIdx2) const3407 bool X86InstrInfo::findFMA3CommutedOpIndices(MachineInstr &MI,
3408 unsigned &SrcOpIdx1,
3409 unsigned &SrcOpIdx2) const {
3410
3411 unsigned RegOpsNum = isMem(MI, 3) ? 2 : 3;
3412
3413 // Only the first RegOpsNum operands are commutable.
3414 // Also, the value 'CommuteAnyOperandIndex' is valid here as it means
3415 // that the operand is not specified/fixed.
3416 if (SrcOpIdx1 != CommuteAnyOperandIndex &&
3417 (SrcOpIdx1 < 1 || SrcOpIdx1 > RegOpsNum))
3418 return false;
3419 if (SrcOpIdx2 != CommuteAnyOperandIndex &&
3420 (SrcOpIdx2 < 1 || SrcOpIdx2 > RegOpsNum))
3421 return false;
3422
3423 // Look for two different register operands assumed to be commutable
3424 // regardless of the FMA opcode. The FMA opcode is adjusted later.
3425 if (SrcOpIdx1 == CommuteAnyOperandIndex ||
3426 SrcOpIdx2 == CommuteAnyOperandIndex) {
3427 unsigned CommutableOpIdx1 = SrcOpIdx1;
3428 unsigned CommutableOpIdx2 = SrcOpIdx2;
3429
3430 // At least one of operands to be commuted is not specified and
3431 // this method is free to choose appropriate commutable operands.
3432 if (SrcOpIdx1 == SrcOpIdx2)
3433 // Both of operands are not fixed. By default set one of commutable
3434 // operands to the last register operand of the instruction.
3435 CommutableOpIdx2 = RegOpsNum;
3436 else if (SrcOpIdx2 == CommuteAnyOperandIndex)
3437 // Only one of operands is not fixed.
3438 CommutableOpIdx2 = SrcOpIdx1;
3439
3440 // CommutableOpIdx2 is well defined now. Let's choose another commutable
3441 // operand and assign its index to CommutableOpIdx1.
3442 unsigned Op2Reg = MI.getOperand(CommutableOpIdx2).getReg();
3443 for (CommutableOpIdx1 = RegOpsNum; CommutableOpIdx1 > 0; CommutableOpIdx1--) {
3444 // The commuted operands must have different registers.
3445 // Otherwise, the commute transformation does not change anything and
3446 // is useless then.
3447 if (Op2Reg != MI.getOperand(CommutableOpIdx1).getReg())
3448 break;
3449 }
3450
3451 // No appropriate commutable operands were found.
3452 if (CommutableOpIdx1 == 0)
3453 return false;
3454
3455 // Assign the found pair of commutable indices to SrcOpIdx1 and SrcOpidx2
3456 // to return those values.
3457 if (!fixCommutedOpIndices(SrcOpIdx1, SrcOpIdx2,
3458 CommutableOpIdx1, CommutableOpIdx2))
3459 return false;
3460 }
3461
3462 // Check if we can adjust the opcode to preserve the semantics when
3463 // commute the register operands.
3464 return getFMA3OpcodeToCommuteOperands(MI, SrcOpIdx1, SrcOpIdx2) != 0;
3465 }
3466
getFMA3OpcodeToCommuteOperands(MachineInstr & MI,unsigned SrcOpIdx1,unsigned SrcOpIdx2) const3467 unsigned X86InstrInfo::getFMA3OpcodeToCommuteOperands(
3468 MachineInstr &MI, unsigned SrcOpIdx1, unsigned SrcOpIdx2) const {
3469 unsigned Opc = MI.getOpcode();
3470
3471 // Define the array that holds FMA opcodes in groups
3472 // of 3 opcodes(132, 213, 231) in each group.
3473 static const uint16_t RegularOpcodeGroups[][3] = {
3474 { X86::VFMADDSSr132r, X86::VFMADDSSr213r, X86::VFMADDSSr231r },
3475 { X86::VFMADDSDr132r, X86::VFMADDSDr213r, X86::VFMADDSDr231r },
3476 { X86::VFMADDPSr132r, X86::VFMADDPSr213r, X86::VFMADDPSr231r },
3477 { X86::VFMADDPDr132r, X86::VFMADDPDr213r, X86::VFMADDPDr231r },
3478 { X86::VFMADDPSr132rY, X86::VFMADDPSr213rY, X86::VFMADDPSr231rY },
3479 { X86::VFMADDPDr132rY, X86::VFMADDPDr213rY, X86::VFMADDPDr231rY },
3480 { X86::VFMADDSSr132m, X86::VFMADDSSr213m, X86::VFMADDSSr231m },
3481 { X86::VFMADDSDr132m, X86::VFMADDSDr213m, X86::VFMADDSDr231m },
3482 { X86::VFMADDPSr132m, X86::VFMADDPSr213m, X86::VFMADDPSr231m },
3483 { X86::VFMADDPDr132m, X86::VFMADDPDr213m, X86::VFMADDPDr231m },
3484 { X86::VFMADDPSr132mY, X86::VFMADDPSr213mY, X86::VFMADDPSr231mY },
3485 { X86::VFMADDPDr132mY, X86::VFMADDPDr213mY, X86::VFMADDPDr231mY },
3486
3487 { X86::VFMSUBSSr132r, X86::VFMSUBSSr213r, X86::VFMSUBSSr231r },
3488 { X86::VFMSUBSDr132r, X86::VFMSUBSDr213r, X86::VFMSUBSDr231r },
3489 { X86::VFMSUBPSr132r, X86::VFMSUBPSr213r, X86::VFMSUBPSr231r },
3490 { X86::VFMSUBPDr132r, X86::VFMSUBPDr213r, X86::VFMSUBPDr231r },
3491 { X86::VFMSUBPSr132rY, X86::VFMSUBPSr213rY, X86::VFMSUBPSr231rY },
3492 { X86::VFMSUBPDr132rY, X86::VFMSUBPDr213rY, X86::VFMSUBPDr231rY },
3493 { X86::VFMSUBSSr132m, X86::VFMSUBSSr213m, X86::VFMSUBSSr231m },
3494 { X86::VFMSUBSDr132m, X86::VFMSUBSDr213m, X86::VFMSUBSDr231m },
3495 { X86::VFMSUBPSr132m, X86::VFMSUBPSr213m, X86::VFMSUBPSr231m },
3496 { X86::VFMSUBPDr132m, X86::VFMSUBPDr213m, X86::VFMSUBPDr231m },
3497 { X86::VFMSUBPSr132mY, X86::VFMSUBPSr213mY, X86::VFMSUBPSr231mY },
3498 { X86::VFMSUBPDr132mY, X86::VFMSUBPDr213mY, X86::VFMSUBPDr231mY },
3499
3500 { X86::VFNMADDSSr132r, X86::VFNMADDSSr213r, X86::VFNMADDSSr231r },
3501 { X86::VFNMADDSDr132r, X86::VFNMADDSDr213r, X86::VFNMADDSDr231r },
3502 { X86::VFNMADDPSr132r, X86::VFNMADDPSr213r, X86::VFNMADDPSr231r },
3503 { X86::VFNMADDPDr132r, X86::VFNMADDPDr213r, X86::VFNMADDPDr231r },
3504 { X86::VFNMADDPSr132rY, X86::VFNMADDPSr213rY, X86::VFNMADDPSr231rY },
3505 { X86::VFNMADDPDr132rY, X86::VFNMADDPDr213rY, X86::VFNMADDPDr231rY },
3506 { X86::VFNMADDSSr132m, X86::VFNMADDSSr213m, X86::VFNMADDSSr231m },
3507 { X86::VFNMADDSDr132m, X86::VFNMADDSDr213m, X86::VFNMADDSDr231m },
3508 { X86::VFNMADDPSr132m, X86::VFNMADDPSr213m, X86::VFNMADDPSr231m },
3509 { X86::VFNMADDPDr132m, X86::VFNMADDPDr213m, X86::VFNMADDPDr231m },
3510 { X86::VFNMADDPSr132mY, X86::VFNMADDPSr213mY, X86::VFNMADDPSr231mY },
3511 { X86::VFNMADDPDr132mY, X86::VFNMADDPDr213mY, X86::VFNMADDPDr231mY },
3512
3513 { X86::VFNMSUBSSr132r, X86::VFNMSUBSSr213r, X86::VFNMSUBSSr231r },
3514 { X86::VFNMSUBSDr132r, X86::VFNMSUBSDr213r, X86::VFNMSUBSDr231r },
3515 { X86::VFNMSUBPSr132r, X86::VFNMSUBPSr213r, X86::VFNMSUBPSr231r },
3516 { X86::VFNMSUBPDr132r, X86::VFNMSUBPDr213r, X86::VFNMSUBPDr231r },
3517 { X86::VFNMSUBPSr132rY, X86::VFNMSUBPSr213rY, X86::VFNMSUBPSr231rY },
3518 { X86::VFNMSUBPDr132rY, X86::VFNMSUBPDr213rY, X86::VFNMSUBPDr231rY },
3519 { X86::VFNMSUBSSr132m, X86::VFNMSUBSSr213m, X86::VFNMSUBSSr231m },
3520 { X86::VFNMSUBSDr132m, X86::VFNMSUBSDr213m, X86::VFNMSUBSDr231m },
3521 { X86::VFNMSUBPSr132m, X86::VFNMSUBPSr213m, X86::VFNMSUBPSr231m },
3522 { X86::VFNMSUBPDr132m, X86::VFNMSUBPDr213m, X86::VFNMSUBPDr231m },
3523 { X86::VFNMSUBPSr132mY, X86::VFNMSUBPSr213mY, X86::VFNMSUBPSr231mY },
3524 { X86::VFNMSUBPDr132mY, X86::VFNMSUBPDr213mY, X86::VFNMSUBPDr231mY },
3525
3526 { X86::VFMADDSUBPSr132r, X86::VFMADDSUBPSr213r, X86::VFMADDSUBPSr231r },
3527 { X86::VFMADDSUBPDr132r, X86::VFMADDSUBPDr213r, X86::VFMADDSUBPDr231r },
3528 { X86::VFMADDSUBPSr132rY, X86::VFMADDSUBPSr213rY, X86::VFMADDSUBPSr231rY },
3529 { X86::VFMADDSUBPDr132rY, X86::VFMADDSUBPDr213rY, X86::VFMADDSUBPDr231rY },
3530 { X86::VFMADDSUBPSr132m, X86::VFMADDSUBPSr213m, X86::VFMADDSUBPSr231m },
3531 { X86::VFMADDSUBPDr132m, X86::VFMADDSUBPDr213m, X86::VFMADDSUBPDr231m },
3532 { X86::VFMADDSUBPSr132mY, X86::VFMADDSUBPSr213mY, X86::VFMADDSUBPSr231mY },
3533 { X86::VFMADDSUBPDr132mY, X86::VFMADDSUBPDr213mY, X86::VFMADDSUBPDr231mY },
3534
3535 { X86::VFMSUBADDPSr132r, X86::VFMSUBADDPSr213r, X86::VFMSUBADDPSr231r },
3536 { X86::VFMSUBADDPDr132r, X86::VFMSUBADDPDr213r, X86::VFMSUBADDPDr231r },
3537 { X86::VFMSUBADDPSr132rY, X86::VFMSUBADDPSr213rY, X86::VFMSUBADDPSr231rY },
3538 { X86::VFMSUBADDPDr132rY, X86::VFMSUBADDPDr213rY, X86::VFMSUBADDPDr231rY },
3539 { X86::VFMSUBADDPSr132m, X86::VFMSUBADDPSr213m, X86::VFMSUBADDPSr231m },
3540 { X86::VFMSUBADDPDr132m, X86::VFMSUBADDPDr213m, X86::VFMSUBADDPDr231m },
3541 { X86::VFMSUBADDPSr132mY, X86::VFMSUBADDPSr213mY, X86::VFMSUBADDPSr231mY },
3542 { X86::VFMSUBADDPDr132mY, X86::VFMSUBADDPDr213mY, X86::VFMSUBADDPDr231mY }
3543 };
3544
3545 // Define the array that holds FMA*_Int opcodes in groups
3546 // of 3 opcodes(132, 213, 231) in each group.
3547 static const uint16_t IntrinOpcodeGroups[][3] = {
3548 { X86::VFMADDSSr132r_Int, X86::VFMADDSSr213r_Int, X86::VFMADDSSr231r_Int },
3549 { X86::VFMADDSDr132r_Int, X86::VFMADDSDr213r_Int, X86::VFMADDSDr231r_Int },
3550 { X86::VFMADDSSr132m_Int, X86::VFMADDSSr213m_Int, X86::VFMADDSSr231m_Int },
3551 { X86::VFMADDSDr132m_Int, X86::VFMADDSDr213m_Int, X86::VFMADDSDr231m_Int },
3552
3553 { X86::VFMSUBSSr132r_Int, X86::VFMSUBSSr213r_Int, X86::VFMSUBSSr231r_Int },
3554 { X86::VFMSUBSDr132r_Int, X86::VFMSUBSDr213r_Int, X86::VFMSUBSDr231r_Int },
3555 { X86::VFMSUBSSr132m_Int, X86::VFMSUBSSr213m_Int, X86::VFMSUBSSr231m_Int },
3556 { X86::VFMSUBSDr132m_Int, X86::VFMSUBSDr213m_Int, X86::VFMSUBSDr231m_Int },
3557
3558 { X86::VFNMADDSSr132r_Int, X86::VFNMADDSSr213r_Int, X86::VFNMADDSSr231r_Int },
3559 { X86::VFNMADDSDr132r_Int, X86::VFNMADDSDr213r_Int, X86::VFNMADDSDr231r_Int },
3560 { X86::VFNMADDSSr132m_Int, X86::VFNMADDSSr213m_Int, X86::VFNMADDSSr231m_Int },
3561 { X86::VFNMADDSDr132m_Int, X86::VFNMADDSDr213m_Int, X86::VFNMADDSDr231m_Int },
3562
3563 { X86::VFNMSUBSSr132r_Int, X86::VFNMSUBSSr213r_Int, X86::VFNMSUBSSr231r_Int },
3564 { X86::VFNMSUBSDr132r_Int, X86::VFNMSUBSDr213r_Int, X86::VFNMSUBSDr231r_Int },
3565 { X86::VFNMSUBSSr132m_Int, X86::VFNMSUBSSr213m_Int, X86::VFNMSUBSSr231m_Int },
3566 { X86::VFNMSUBSDr132m_Int, X86::VFNMSUBSDr213m_Int, X86::VFNMSUBSDr231m_Int },
3567 };
3568
3569 const unsigned Form132Index = 0;
3570 const unsigned Form213Index = 1;
3571 const unsigned Form231Index = 2;
3572 const unsigned FormsNum = 3;
3573
3574 bool IsIntrinOpcode;
3575 isFMA3(Opc, &IsIntrinOpcode);
3576
3577 size_t GroupsNum;
3578 const uint16_t (*OpcodeGroups)[3];
3579 if (IsIntrinOpcode) {
3580 GroupsNum = array_lengthof(IntrinOpcodeGroups);
3581 OpcodeGroups = IntrinOpcodeGroups;
3582 } else {
3583 GroupsNum = array_lengthof(RegularOpcodeGroups);
3584 OpcodeGroups = RegularOpcodeGroups;
3585 }
3586
3587 const uint16_t *FoundOpcodesGroup = nullptr;
3588 size_t FormIndex;
3589
3590 // Look for the input opcode in the corresponding opcodes table.
3591 for (size_t GroupIndex = 0; GroupIndex < GroupsNum && !FoundOpcodesGroup;
3592 ++GroupIndex) {
3593 for (FormIndex = 0; FormIndex < FormsNum; ++FormIndex) {
3594 if (OpcodeGroups[GroupIndex][FormIndex] == Opc) {
3595 FoundOpcodesGroup = OpcodeGroups[GroupIndex];
3596 break;
3597 }
3598 }
3599 }
3600
3601 // The input opcode does not match with any of the opcodes from the tables.
3602 // The unsupported FMA opcode must be added to one of the two opcode groups
3603 // defined above.
3604 assert(FoundOpcodesGroup != nullptr && "Unexpected FMA3 opcode");
3605
3606 // Put the lowest index to SrcOpIdx1 to simplify the checks below.
3607 if (SrcOpIdx1 > SrcOpIdx2)
3608 std::swap(SrcOpIdx1, SrcOpIdx2);
3609
3610 // TODO: Commuting the 1st operand of FMA*_Int requires some additional
3611 // analysis. The commute optimization is legal only if all users of FMA*_Int
3612 // use only the lowest element of the FMA*_Int instruction. Such analysis are
3613 // not implemented yet. So, just return 0 in that case.
3614 // When such analysis are available this place will be the right place for
3615 // calling it.
3616 if (IsIntrinOpcode && SrcOpIdx1 == 1)
3617 return 0;
3618
3619 unsigned Case;
3620 if (SrcOpIdx1 == 1 && SrcOpIdx2 == 2)
3621 Case = 0;
3622 else if (SrcOpIdx1 == 1 && SrcOpIdx2 == 3)
3623 Case = 1;
3624 else if (SrcOpIdx1 == 2 && SrcOpIdx2 == 3)
3625 Case = 2;
3626 else
3627 return 0;
3628
3629 // Define the FMA forms mapping array that helps to map input FMA form
3630 // to output FMA form to preserve the operation semantics after
3631 // commuting the operands.
3632 static const unsigned FormMapping[][3] = {
3633 // 0: SrcOpIdx1 == 1 && SrcOpIdx2 == 2;
3634 // FMA132 A, C, b; ==> FMA231 C, A, b;
3635 // FMA213 B, A, c; ==> FMA213 A, B, c;
3636 // FMA231 C, A, b; ==> FMA132 A, C, b;
3637 { Form231Index, Form213Index, Form132Index },
3638 // 1: SrcOpIdx1 == 1 && SrcOpIdx2 == 3;
3639 // FMA132 A, c, B; ==> FMA132 B, c, A;
3640 // FMA213 B, a, C; ==> FMA231 C, a, B;
3641 // FMA231 C, a, B; ==> FMA213 B, a, C;
3642 { Form132Index, Form231Index, Form213Index },
3643 // 2: SrcOpIdx1 == 2 && SrcOpIdx2 == 3;
3644 // FMA132 a, C, B; ==> FMA213 a, B, C;
3645 // FMA213 b, A, C; ==> FMA132 b, C, A;
3646 // FMA231 c, A, B; ==> FMA231 c, B, A;
3647 { Form213Index, Form132Index, Form231Index }
3648 };
3649
3650 // Everything is ready, just adjust the FMA opcode and return it.
3651 FormIndex = FormMapping[Case][FormIndex];
3652 return FoundOpcodesGroup[FormIndex];
3653 }
3654
findCommutedOpIndices(MachineInstr & MI,unsigned & SrcOpIdx1,unsigned & SrcOpIdx2) const3655 bool X86InstrInfo::findCommutedOpIndices(MachineInstr &MI, unsigned &SrcOpIdx1,
3656 unsigned &SrcOpIdx2) const {
3657 switch (MI.getOpcode()) {
3658 case X86::CMPPDrri:
3659 case X86::CMPPSrri:
3660 case X86::VCMPPDrri:
3661 case X86::VCMPPSrri:
3662 case X86::VCMPPDYrri:
3663 case X86::VCMPPSYrri: {
3664 // Float comparison can be safely commuted for
3665 // Ordered/Unordered/Equal/NotEqual tests
3666 unsigned Imm = MI.getOperand(3).getImm() & 0x7;
3667 switch (Imm) {
3668 case 0x00: // EQUAL
3669 case 0x03: // UNORDERED
3670 case 0x04: // NOT EQUAL
3671 case 0x07: // ORDERED
3672 // The indices of the commutable operands are 1 and 2.
3673 // Assign them to the returned operand indices here.
3674 return fixCommutedOpIndices(SrcOpIdx1, SrcOpIdx2, 1, 2);
3675 }
3676 return false;
3677 }
3678 default:
3679 if (isFMA3(MI.getOpcode()))
3680 return findFMA3CommutedOpIndices(MI, SrcOpIdx1, SrcOpIdx2);
3681 return TargetInstrInfo::findCommutedOpIndices(MI, SrcOpIdx1, SrcOpIdx2);
3682 }
3683 return false;
3684 }
3685
getCondFromBranchOpc(unsigned BrOpc)3686 static X86::CondCode getCondFromBranchOpc(unsigned BrOpc) {
3687 switch (BrOpc) {
3688 default: return X86::COND_INVALID;
3689 case X86::JE_1: return X86::COND_E;
3690 case X86::JNE_1: return X86::COND_NE;
3691 case X86::JL_1: return X86::COND_L;
3692 case X86::JLE_1: return X86::COND_LE;
3693 case X86::JG_1: return X86::COND_G;
3694 case X86::JGE_1: return X86::COND_GE;
3695 case X86::JB_1: return X86::COND_B;
3696 case X86::JBE_1: return X86::COND_BE;
3697 case X86::JA_1: return X86::COND_A;
3698 case X86::JAE_1: return X86::COND_AE;
3699 case X86::JS_1: return X86::COND_S;
3700 case X86::JNS_1: return X86::COND_NS;
3701 case X86::JP_1: return X86::COND_P;
3702 case X86::JNP_1: return X86::COND_NP;
3703 case X86::JO_1: return X86::COND_O;
3704 case X86::JNO_1: return X86::COND_NO;
3705 }
3706 }
3707
3708 /// Return condition code of a SET opcode.
getCondFromSETOpc(unsigned Opc)3709 static X86::CondCode getCondFromSETOpc(unsigned Opc) {
3710 switch (Opc) {
3711 default: return X86::COND_INVALID;
3712 case X86::SETAr: case X86::SETAm: return X86::COND_A;
3713 case X86::SETAEr: case X86::SETAEm: return X86::COND_AE;
3714 case X86::SETBr: case X86::SETBm: return X86::COND_B;
3715 case X86::SETBEr: case X86::SETBEm: return X86::COND_BE;
3716 case X86::SETEr: case X86::SETEm: return X86::COND_E;
3717 case X86::SETGr: case X86::SETGm: return X86::COND_G;
3718 case X86::SETGEr: case X86::SETGEm: return X86::COND_GE;
3719 case X86::SETLr: case X86::SETLm: return X86::COND_L;
3720 case X86::SETLEr: case X86::SETLEm: return X86::COND_LE;
3721 case X86::SETNEr: case X86::SETNEm: return X86::COND_NE;
3722 case X86::SETNOr: case X86::SETNOm: return X86::COND_NO;
3723 case X86::SETNPr: case X86::SETNPm: return X86::COND_NP;
3724 case X86::SETNSr: case X86::SETNSm: return X86::COND_NS;
3725 case X86::SETOr: case X86::SETOm: return X86::COND_O;
3726 case X86::SETPr: case X86::SETPm: return X86::COND_P;
3727 case X86::SETSr: case X86::SETSm: return X86::COND_S;
3728 }
3729 }
3730
3731 /// Return condition code of a CMov opcode.
getCondFromCMovOpc(unsigned Opc)3732 X86::CondCode X86::getCondFromCMovOpc(unsigned Opc) {
3733 switch (Opc) {
3734 default: return X86::COND_INVALID;
3735 case X86::CMOVA16rm: case X86::CMOVA16rr: case X86::CMOVA32rm:
3736 case X86::CMOVA32rr: case X86::CMOVA64rm: case X86::CMOVA64rr:
3737 return X86::COND_A;
3738 case X86::CMOVAE16rm: case X86::CMOVAE16rr: case X86::CMOVAE32rm:
3739 case X86::CMOVAE32rr: case X86::CMOVAE64rm: case X86::CMOVAE64rr:
3740 return X86::COND_AE;
3741 case X86::CMOVB16rm: case X86::CMOVB16rr: case X86::CMOVB32rm:
3742 case X86::CMOVB32rr: case X86::CMOVB64rm: case X86::CMOVB64rr:
3743 return X86::COND_B;
3744 case X86::CMOVBE16rm: case X86::CMOVBE16rr: case X86::CMOVBE32rm:
3745 case X86::CMOVBE32rr: case X86::CMOVBE64rm: case X86::CMOVBE64rr:
3746 return X86::COND_BE;
3747 case X86::CMOVE16rm: case X86::CMOVE16rr: case X86::CMOVE32rm:
3748 case X86::CMOVE32rr: case X86::CMOVE64rm: case X86::CMOVE64rr:
3749 return X86::COND_E;
3750 case X86::CMOVG16rm: case X86::CMOVG16rr: case X86::CMOVG32rm:
3751 case X86::CMOVG32rr: case X86::CMOVG64rm: case X86::CMOVG64rr:
3752 return X86::COND_G;
3753 case X86::CMOVGE16rm: case X86::CMOVGE16rr: case X86::CMOVGE32rm:
3754 case X86::CMOVGE32rr: case X86::CMOVGE64rm: case X86::CMOVGE64rr:
3755 return X86::COND_GE;
3756 case X86::CMOVL16rm: case X86::CMOVL16rr: case X86::CMOVL32rm:
3757 case X86::CMOVL32rr: case X86::CMOVL64rm: case X86::CMOVL64rr:
3758 return X86::COND_L;
3759 case X86::CMOVLE16rm: case X86::CMOVLE16rr: case X86::CMOVLE32rm:
3760 case X86::CMOVLE32rr: case X86::CMOVLE64rm: case X86::CMOVLE64rr:
3761 return X86::COND_LE;
3762 case X86::CMOVNE16rm: case X86::CMOVNE16rr: case X86::CMOVNE32rm:
3763 case X86::CMOVNE32rr: case X86::CMOVNE64rm: case X86::CMOVNE64rr:
3764 return X86::COND_NE;
3765 case X86::CMOVNO16rm: case X86::CMOVNO16rr: case X86::CMOVNO32rm:
3766 case X86::CMOVNO32rr: case X86::CMOVNO64rm: case X86::CMOVNO64rr:
3767 return X86::COND_NO;
3768 case X86::CMOVNP16rm: case X86::CMOVNP16rr: case X86::CMOVNP32rm:
3769 case X86::CMOVNP32rr: case X86::CMOVNP64rm: case X86::CMOVNP64rr:
3770 return X86::COND_NP;
3771 case X86::CMOVNS16rm: case X86::CMOVNS16rr: case X86::CMOVNS32rm:
3772 case X86::CMOVNS32rr: case X86::CMOVNS64rm: case X86::CMOVNS64rr:
3773 return X86::COND_NS;
3774 case X86::CMOVO16rm: case X86::CMOVO16rr: case X86::CMOVO32rm:
3775 case X86::CMOVO32rr: case X86::CMOVO64rm: case X86::CMOVO64rr:
3776 return X86::COND_O;
3777 case X86::CMOVP16rm: case X86::CMOVP16rr: case X86::CMOVP32rm:
3778 case X86::CMOVP32rr: case X86::CMOVP64rm: case X86::CMOVP64rr:
3779 return X86::COND_P;
3780 case X86::CMOVS16rm: case X86::CMOVS16rr: case X86::CMOVS32rm:
3781 case X86::CMOVS32rr: case X86::CMOVS64rm: case X86::CMOVS64rr:
3782 return X86::COND_S;
3783 }
3784 }
3785
GetCondBranchFromCond(X86::CondCode CC)3786 unsigned X86::GetCondBranchFromCond(X86::CondCode CC) {
3787 switch (CC) {
3788 default: llvm_unreachable("Illegal condition code!");
3789 case X86::COND_E: return X86::JE_1;
3790 case X86::COND_NE: return X86::JNE_1;
3791 case X86::COND_L: return X86::JL_1;
3792 case X86::COND_LE: return X86::JLE_1;
3793 case X86::COND_G: return X86::JG_1;
3794 case X86::COND_GE: return X86::JGE_1;
3795 case X86::COND_B: return X86::JB_1;
3796 case X86::COND_BE: return X86::JBE_1;
3797 case X86::COND_A: return X86::JA_1;
3798 case X86::COND_AE: return X86::JAE_1;
3799 case X86::COND_S: return X86::JS_1;
3800 case X86::COND_NS: return X86::JNS_1;
3801 case X86::COND_P: return X86::JP_1;
3802 case X86::COND_NP: return X86::JNP_1;
3803 case X86::COND_O: return X86::JO_1;
3804 case X86::COND_NO: return X86::JNO_1;
3805 }
3806 }
3807
3808 /// Return the inverse of the specified condition,
3809 /// e.g. turning COND_E to COND_NE.
GetOppositeBranchCondition(X86::CondCode CC)3810 X86::CondCode X86::GetOppositeBranchCondition(X86::CondCode CC) {
3811 switch (CC) {
3812 default: llvm_unreachable("Illegal condition code!");
3813 case X86::COND_E: return X86::COND_NE;
3814 case X86::COND_NE: return X86::COND_E;
3815 case X86::COND_L: return X86::COND_GE;
3816 case X86::COND_LE: return X86::COND_G;
3817 case X86::COND_G: return X86::COND_LE;
3818 case X86::COND_GE: return X86::COND_L;
3819 case X86::COND_B: return X86::COND_AE;
3820 case X86::COND_BE: return X86::COND_A;
3821 case X86::COND_A: return X86::COND_BE;
3822 case X86::COND_AE: return X86::COND_B;
3823 case X86::COND_S: return X86::COND_NS;
3824 case X86::COND_NS: return X86::COND_S;
3825 case X86::COND_P: return X86::COND_NP;
3826 case X86::COND_NP: return X86::COND_P;
3827 case X86::COND_O: return X86::COND_NO;
3828 case X86::COND_NO: return X86::COND_O;
3829 case X86::COND_NE_OR_P: return X86::COND_E_AND_NP;
3830 case X86::COND_E_AND_NP: return X86::COND_NE_OR_P;
3831 }
3832 }
3833
3834 /// Assuming the flags are set by MI(a,b), return the condition code if we
3835 /// modify the instructions such that flags are set by MI(b,a).
getSwappedCondition(X86::CondCode CC)3836 static X86::CondCode getSwappedCondition(X86::CondCode CC) {
3837 switch (CC) {
3838 default: return X86::COND_INVALID;
3839 case X86::COND_E: return X86::COND_E;
3840 case X86::COND_NE: return X86::COND_NE;
3841 case X86::COND_L: return X86::COND_G;
3842 case X86::COND_LE: return X86::COND_GE;
3843 case X86::COND_G: return X86::COND_L;
3844 case X86::COND_GE: return X86::COND_LE;
3845 case X86::COND_B: return X86::COND_A;
3846 case X86::COND_BE: return X86::COND_AE;
3847 case X86::COND_A: return X86::COND_B;
3848 case X86::COND_AE: return X86::COND_BE;
3849 }
3850 }
3851
3852 /// Return a set opcode for the given condition and
3853 /// whether it has memory operand.
getSETFromCond(CondCode CC,bool HasMemoryOperand)3854 unsigned X86::getSETFromCond(CondCode CC, bool HasMemoryOperand) {
3855 static const uint16_t Opc[16][2] = {
3856 { X86::SETAr, X86::SETAm },
3857 { X86::SETAEr, X86::SETAEm },
3858 { X86::SETBr, X86::SETBm },
3859 { X86::SETBEr, X86::SETBEm },
3860 { X86::SETEr, X86::SETEm },
3861 { X86::SETGr, X86::SETGm },
3862 { X86::SETGEr, X86::SETGEm },
3863 { X86::SETLr, X86::SETLm },
3864 { X86::SETLEr, X86::SETLEm },
3865 { X86::SETNEr, X86::SETNEm },
3866 { X86::SETNOr, X86::SETNOm },
3867 { X86::SETNPr, X86::SETNPm },
3868 { X86::SETNSr, X86::SETNSm },
3869 { X86::SETOr, X86::SETOm },
3870 { X86::SETPr, X86::SETPm },
3871 { X86::SETSr, X86::SETSm }
3872 };
3873
3874 assert(CC <= LAST_VALID_COND && "Can only handle standard cond codes");
3875 return Opc[CC][HasMemoryOperand ? 1 : 0];
3876 }
3877
3878 /// Return a cmov opcode for the given condition,
3879 /// register size in bytes, and operand type.
getCMovFromCond(CondCode CC,unsigned RegBytes,bool HasMemoryOperand)3880 unsigned X86::getCMovFromCond(CondCode CC, unsigned RegBytes,
3881 bool HasMemoryOperand) {
3882 static const uint16_t Opc[32][3] = {
3883 { X86::CMOVA16rr, X86::CMOVA32rr, X86::CMOVA64rr },
3884 { X86::CMOVAE16rr, X86::CMOVAE32rr, X86::CMOVAE64rr },
3885 { X86::CMOVB16rr, X86::CMOVB32rr, X86::CMOVB64rr },
3886 { X86::CMOVBE16rr, X86::CMOVBE32rr, X86::CMOVBE64rr },
3887 { X86::CMOVE16rr, X86::CMOVE32rr, X86::CMOVE64rr },
3888 { X86::CMOVG16rr, X86::CMOVG32rr, X86::CMOVG64rr },
3889 { X86::CMOVGE16rr, X86::CMOVGE32rr, X86::CMOVGE64rr },
3890 { X86::CMOVL16rr, X86::CMOVL32rr, X86::CMOVL64rr },
3891 { X86::CMOVLE16rr, X86::CMOVLE32rr, X86::CMOVLE64rr },
3892 { X86::CMOVNE16rr, X86::CMOVNE32rr, X86::CMOVNE64rr },
3893 { X86::CMOVNO16rr, X86::CMOVNO32rr, X86::CMOVNO64rr },
3894 { X86::CMOVNP16rr, X86::CMOVNP32rr, X86::CMOVNP64rr },
3895 { X86::CMOVNS16rr, X86::CMOVNS32rr, X86::CMOVNS64rr },
3896 { X86::CMOVO16rr, X86::CMOVO32rr, X86::CMOVO64rr },
3897 { X86::CMOVP16rr, X86::CMOVP32rr, X86::CMOVP64rr },
3898 { X86::CMOVS16rr, X86::CMOVS32rr, X86::CMOVS64rr },
3899 { X86::CMOVA16rm, X86::CMOVA32rm, X86::CMOVA64rm },
3900 { X86::CMOVAE16rm, X86::CMOVAE32rm, X86::CMOVAE64rm },
3901 { X86::CMOVB16rm, X86::CMOVB32rm, X86::CMOVB64rm },
3902 { X86::CMOVBE16rm, X86::CMOVBE32rm, X86::CMOVBE64rm },
3903 { X86::CMOVE16rm, X86::CMOVE32rm, X86::CMOVE64rm },
3904 { X86::CMOVG16rm, X86::CMOVG32rm, X86::CMOVG64rm },
3905 { X86::CMOVGE16rm, X86::CMOVGE32rm, X86::CMOVGE64rm },
3906 { X86::CMOVL16rm, X86::CMOVL32rm, X86::CMOVL64rm },
3907 { X86::CMOVLE16rm, X86::CMOVLE32rm, X86::CMOVLE64rm },
3908 { X86::CMOVNE16rm, X86::CMOVNE32rm, X86::CMOVNE64rm },
3909 { X86::CMOVNO16rm, X86::CMOVNO32rm, X86::CMOVNO64rm },
3910 { X86::CMOVNP16rm, X86::CMOVNP32rm, X86::CMOVNP64rm },
3911 { X86::CMOVNS16rm, X86::CMOVNS32rm, X86::CMOVNS64rm },
3912 { X86::CMOVO16rm, X86::CMOVO32rm, X86::CMOVO64rm },
3913 { X86::CMOVP16rm, X86::CMOVP32rm, X86::CMOVP64rm },
3914 { X86::CMOVS16rm, X86::CMOVS32rm, X86::CMOVS64rm }
3915 };
3916
3917 assert(CC < 16 && "Can only handle standard cond codes");
3918 unsigned Idx = HasMemoryOperand ? 16+CC : CC;
3919 switch(RegBytes) {
3920 default: llvm_unreachable("Illegal register size!");
3921 case 2: return Opc[Idx][0];
3922 case 4: return Opc[Idx][1];
3923 case 8: return Opc[Idx][2];
3924 }
3925 }
3926
isUnpredicatedTerminator(const MachineInstr & MI) const3927 bool X86InstrInfo::isUnpredicatedTerminator(const MachineInstr &MI) const {
3928 if (!MI.isTerminator()) return false;
3929
3930 // Conditional branch is a special case.
3931 if (MI.isBranch() && !MI.isBarrier())
3932 return true;
3933 if (!MI.isPredicable())
3934 return true;
3935 return !isPredicated(MI);
3936 }
3937
3938 // Given a MBB and its TBB, find the FBB which was a fallthrough MBB (it may
3939 // not be a fallthrough MBB now due to layout changes). Return nullptr if the
3940 // fallthrough MBB cannot be identified.
getFallThroughMBB(MachineBasicBlock * MBB,MachineBasicBlock * TBB)3941 static MachineBasicBlock *getFallThroughMBB(MachineBasicBlock *MBB,
3942 MachineBasicBlock *TBB) {
3943 // Look for non-EHPad successors other than TBB. If we find exactly one, it
3944 // is the fallthrough MBB. If we find zero, then TBB is both the target MBB
3945 // and fallthrough MBB. If we find more than one, we cannot identify the
3946 // fallthrough MBB and should return nullptr.
3947 MachineBasicBlock *FallthroughBB = nullptr;
3948 for (auto SI = MBB->succ_begin(), SE = MBB->succ_end(); SI != SE; ++SI) {
3949 if ((*SI)->isEHPad() || (*SI == TBB && FallthroughBB))
3950 continue;
3951 // Return a nullptr if we found more than one fallthrough successor.
3952 if (FallthroughBB && FallthroughBB != TBB)
3953 return nullptr;
3954 FallthroughBB = *SI;
3955 }
3956 return FallthroughBB;
3957 }
3958
AnalyzeBranchImpl(MachineBasicBlock & MBB,MachineBasicBlock * & TBB,MachineBasicBlock * & FBB,SmallVectorImpl<MachineOperand> & Cond,SmallVectorImpl<MachineInstr * > & CondBranches,bool AllowModify) const3959 bool X86InstrInfo::AnalyzeBranchImpl(
3960 MachineBasicBlock &MBB, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB,
3961 SmallVectorImpl<MachineOperand> &Cond,
3962 SmallVectorImpl<MachineInstr *> &CondBranches, bool AllowModify) const {
3963
3964 // Start from the bottom of the block and work up, examining the
3965 // terminator instructions.
3966 MachineBasicBlock::iterator I = MBB.end();
3967 MachineBasicBlock::iterator UnCondBrIter = MBB.end();
3968 while (I != MBB.begin()) {
3969 --I;
3970 if (I->isDebugValue())
3971 continue;
3972
3973 // Working from the bottom, when we see a non-terminator instruction, we're
3974 // done.
3975 if (!isUnpredicatedTerminator(*I))
3976 break;
3977
3978 // A terminator that isn't a branch can't easily be handled by this
3979 // analysis.
3980 if (!I->isBranch())
3981 return true;
3982
3983 // Handle unconditional branches.
3984 if (I->getOpcode() == X86::JMP_1) {
3985 UnCondBrIter = I;
3986
3987 if (!AllowModify) {
3988 TBB = I->getOperand(0).getMBB();
3989 continue;
3990 }
3991
3992 // If the block has any instructions after a JMP, delete them.
3993 while (std::next(I) != MBB.end())
3994 std::next(I)->eraseFromParent();
3995
3996 Cond.clear();
3997 FBB = nullptr;
3998
3999 // Delete the JMP if it's equivalent to a fall-through.
4000 if (MBB.isLayoutSuccessor(I->getOperand(0).getMBB())) {
4001 TBB = nullptr;
4002 I->eraseFromParent();
4003 I = MBB.end();
4004 UnCondBrIter = MBB.end();
4005 continue;
4006 }
4007
4008 // TBB is used to indicate the unconditional destination.
4009 TBB = I->getOperand(0).getMBB();
4010 continue;
4011 }
4012
4013 // Handle conditional branches.
4014 X86::CondCode BranchCode = getCondFromBranchOpc(I->getOpcode());
4015 if (BranchCode == X86::COND_INVALID)
4016 return true; // Can't handle indirect branch.
4017
4018 // Working from the bottom, handle the first conditional branch.
4019 if (Cond.empty()) {
4020 MachineBasicBlock *TargetBB = I->getOperand(0).getMBB();
4021 if (AllowModify && UnCondBrIter != MBB.end() &&
4022 MBB.isLayoutSuccessor(TargetBB)) {
4023 // If we can modify the code and it ends in something like:
4024 //
4025 // jCC L1
4026 // jmp L2
4027 // L1:
4028 // ...
4029 // L2:
4030 //
4031 // Then we can change this to:
4032 //
4033 // jnCC L2
4034 // L1:
4035 // ...
4036 // L2:
4037 //
4038 // Which is a bit more efficient.
4039 // We conditionally jump to the fall-through block.
4040 BranchCode = GetOppositeBranchCondition(BranchCode);
4041 unsigned JNCC = GetCondBranchFromCond(BranchCode);
4042 MachineBasicBlock::iterator OldInst = I;
4043
4044 BuildMI(MBB, UnCondBrIter, MBB.findDebugLoc(I), get(JNCC))
4045 .addMBB(UnCondBrIter->getOperand(0).getMBB());
4046 BuildMI(MBB, UnCondBrIter, MBB.findDebugLoc(I), get(X86::JMP_1))
4047 .addMBB(TargetBB);
4048
4049 OldInst->eraseFromParent();
4050 UnCondBrIter->eraseFromParent();
4051
4052 // Restart the analysis.
4053 UnCondBrIter = MBB.end();
4054 I = MBB.end();
4055 continue;
4056 }
4057
4058 FBB = TBB;
4059 TBB = I->getOperand(0).getMBB();
4060 Cond.push_back(MachineOperand::CreateImm(BranchCode));
4061 CondBranches.push_back(&*I);
4062 continue;
4063 }
4064
4065 // Handle subsequent conditional branches. Only handle the case where all
4066 // conditional branches branch to the same destination and their condition
4067 // opcodes fit one of the special multi-branch idioms.
4068 assert(Cond.size() == 1);
4069 assert(TBB);
4070
4071 // If the conditions are the same, we can leave them alone.
4072 X86::CondCode OldBranchCode = (X86::CondCode)Cond[0].getImm();
4073 auto NewTBB = I->getOperand(0).getMBB();
4074 if (OldBranchCode == BranchCode && TBB == NewTBB)
4075 continue;
4076
4077 // If they differ, see if they fit one of the known patterns. Theoretically,
4078 // we could handle more patterns here, but we shouldn't expect to see them
4079 // if instruction selection has done a reasonable job.
4080 if (TBB == NewTBB &&
4081 ((OldBranchCode == X86::COND_P && BranchCode == X86::COND_NE) ||
4082 (OldBranchCode == X86::COND_NE && BranchCode == X86::COND_P))) {
4083 BranchCode = X86::COND_NE_OR_P;
4084 } else if ((OldBranchCode == X86::COND_NP && BranchCode == X86::COND_NE) ||
4085 (OldBranchCode == X86::COND_E && BranchCode == X86::COND_P)) {
4086 if (NewTBB != (FBB ? FBB : getFallThroughMBB(&MBB, TBB)))
4087 return true;
4088
4089 // X86::COND_E_AND_NP usually has two different branch destinations.
4090 //
4091 // JP B1
4092 // JE B2
4093 // JMP B1
4094 // B1:
4095 // B2:
4096 //
4097 // Here this condition branches to B2 only if NP && E. It has another
4098 // equivalent form:
4099 //
4100 // JNE B1
4101 // JNP B2
4102 // JMP B1
4103 // B1:
4104 // B2:
4105 //
4106 // Similarly it branches to B2 only if E && NP. That is why this condition
4107 // is named with COND_E_AND_NP.
4108 BranchCode = X86::COND_E_AND_NP;
4109 } else
4110 return true;
4111
4112 // Update the MachineOperand.
4113 Cond[0].setImm(BranchCode);
4114 CondBranches.push_back(&*I);
4115 }
4116
4117 return false;
4118 }
4119
analyzeBranch(MachineBasicBlock & MBB,MachineBasicBlock * & TBB,MachineBasicBlock * & FBB,SmallVectorImpl<MachineOperand> & Cond,bool AllowModify) const4120 bool X86InstrInfo::analyzeBranch(MachineBasicBlock &MBB,
4121 MachineBasicBlock *&TBB,
4122 MachineBasicBlock *&FBB,
4123 SmallVectorImpl<MachineOperand> &Cond,
4124 bool AllowModify) const {
4125 SmallVector<MachineInstr *, 4> CondBranches;
4126 return AnalyzeBranchImpl(MBB, TBB, FBB, Cond, CondBranches, AllowModify);
4127 }
4128
analyzeBranchPredicate(MachineBasicBlock & MBB,MachineBranchPredicate & MBP,bool AllowModify) const4129 bool X86InstrInfo::analyzeBranchPredicate(MachineBasicBlock &MBB,
4130 MachineBranchPredicate &MBP,
4131 bool AllowModify) const {
4132 using namespace std::placeholders;
4133
4134 SmallVector<MachineOperand, 4> Cond;
4135 SmallVector<MachineInstr *, 4> CondBranches;
4136 if (AnalyzeBranchImpl(MBB, MBP.TrueDest, MBP.FalseDest, Cond, CondBranches,
4137 AllowModify))
4138 return true;
4139
4140 if (Cond.size() != 1)
4141 return true;
4142
4143 assert(MBP.TrueDest && "expected!");
4144
4145 if (!MBP.FalseDest)
4146 MBP.FalseDest = MBB.getNextNode();
4147
4148 const TargetRegisterInfo *TRI = &getRegisterInfo();
4149
4150 MachineInstr *ConditionDef = nullptr;
4151 bool SingleUseCondition = true;
4152
4153 for (auto I = std::next(MBB.rbegin()), E = MBB.rend(); I != E; ++I) {
4154 if (I->modifiesRegister(X86::EFLAGS, TRI)) {
4155 ConditionDef = &*I;
4156 break;
4157 }
4158
4159 if (I->readsRegister(X86::EFLAGS, TRI))
4160 SingleUseCondition = false;
4161 }
4162
4163 if (!ConditionDef)
4164 return true;
4165
4166 if (SingleUseCondition) {
4167 for (auto *Succ : MBB.successors())
4168 if (Succ->isLiveIn(X86::EFLAGS))
4169 SingleUseCondition = false;
4170 }
4171
4172 MBP.ConditionDef = ConditionDef;
4173 MBP.SingleUseCondition = SingleUseCondition;
4174
4175 // Currently we only recognize the simple pattern:
4176 //
4177 // test %reg, %reg
4178 // je %label
4179 //
4180 const unsigned TestOpcode =
4181 Subtarget.is64Bit() ? X86::TEST64rr : X86::TEST32rr;
4182
4183 if (ConditionDef->getOpcode() == TestOpcode &&
4184 ConditionDef->getNumOperands() == 3 &&
4185 ConditionDef->getOperand(0).isIdenticalTo(ConditionDef->getOperand(1)) &&
4186 (Cond[0].getImm() == X86::COND_NE || Cond[0].getImm() == X86::COND_E)) {
4187 MBP.LHS = ConditionDef->getOperand(0);
4188 MBP.RHS = MachineOperand::CreateImm(0);
4189 MBP.Predicate = Cond[0].getImm() == X86::COND_NE
4190 ? MachineBranchPredicate::PRED_NE
4191 : MachineBranchPredicate::PRED_EQ;
4192 return false;
4193 }
4194
4195 return true;
4196 }
4197
RemoveBranch(MachineBasicBlock & MBB) const4198 unsigned X86InstrInfo::RemoveBranch(MachineBasicBlock &MBB) const {
4199 MachineBasicBlock::iterator I = MBB.end();
4200 unsigned Count = 0;
4201
4202 while (I != MBB.begin()) {
4203 --I;
4204 if (I->isDebugValue())
4205 continue;
4206 if (I->getOpcode() != X86::JMP_1 &&
4207 getCondFromBranchOpc(I->getOpcode()) == X86::COND_INVALID)
4208 break;
4209 // Remove the branch.
4210 I->eraseFromParent();
4211 I = MBB.end();
4212 ++Count;
4213 }
4214
4215 return Count;
4216 }
4217
InsertBranch(MachineBasicBlock & MBB,MachineBasicBlock * TBB,MachineBasicBlock * FBB,ArrayRef<MachineOperand> Cond,const DebugLoc & DL) const4218 unsigned X86InstrInfo::InsertBranch(MachineBasicBlock &MBB,
4219 MachineBasicBlock *TBB,
4220 MachineBasicBlock *FBB,
4221 ArrayRef<MachineOperand> Cond,
4222 const DebugLoc &DL) const {
4223 // Shouldn't be a fall through.
4224 assert(TBB && "InsertBranch must not be told to insert a fallthrough");
4225 assert((Cond.size() == 1 || Cond.size() == 0) &&
4226 "X86 branch conditions have one component!");
4227
4228 if (Cond.empty()) {
4229 // Unconditional branch?
4230 assert(!FBB && "Unconditional branch with multiple successors!");
4231 BuildMI(&MBB, DL, get(X86::JMP_1)).addMBB(TBB);
4232 return 1;
4233 }
4234
4235 // If FBB is null, it is implied to be a fall-through block.
4236 bool FallThru = FBB == nullptr;
4237
4238 // Conditional branch.
4239 unsigned Count = 0;
4240 X86::CondCode CC = (X86::CondCode)Cond[0].getImm();
4241 switch (CC) {
4242 case X86::COND_NE_OR_P:
4243 // Synthesize NE_OR_P with two branches.
4244 BuildMI(&MBB, DL, get(X86::JNE_1)).addMBB(TBB);
4245 ++Count;
4246 BuildMI(&MBB, DL, get(X86::JP_1)).addMBB(TBB);
4247 ++Count;
4248 break;
4249 case X86::COND_E_AND_NP:
4250 // Use the next block of MBB as FBB if it is null.
4251 if (FBB == nullptr) {
4252 FBB = getFallThroughMBB(&MBB, TBB);
4253 assert(FBB && "MBB cannot be the last block in function when the false "
4254 "body is a fall-through.");
4255 }
4256 // Synthesize COND_E_AND_NP with two branches.
4257 BuildMI(&MBB, DL, get(X86::JNE_1)).addMBB(FBB);
4258 ++Count;
4259 BuildMI(&MBB, DL, get(X86::JNP_1)).addMBB(TBB);
4260 ++Count;
4261 break;
4262 default: {
4263 unsigned Opc = GetCondBranchFromCond(CC);
4264 BuildMI(&MBB, DL, get(Opc)).addMBB(TBB);
4265 ++Count;
4266 }
4267 }
4268 if (!FallThru) {
4269 // Two-way Conditional branch. Insert the second branch.
4270 BuildMI(&MBB, DL, get(X86::JMP_1)).addMBB(FBB);
4271 ++Count;
4272 }
4273 return Count;
4274 }
4275
4276 bool X86InstrInfo::
canInsertSelect(const MachineBasicBlock & MBB,ArrayRef<MachineOperand> Cond,unsigned TrueReg,unsigned FalseReg,int & CondCycles,int & TrueCycles,int & FalseCycles) const4277 canInsertSelect(const MachineBasicBlock &MBB,
4278 ArrayRef<MachineOperand> Cond,
4279 unsigned TrueReg, unsigned FalseReg,
4280 int &CondCycles, int &TrueCycles, int &FalseCycles) const {
4281 // Not all subtargets have cmov instructions.
4282 if (!Subtarget.hasCMov())
4283 return false;
4284 if (Cond.size() != 1)
4285 return false;
4286 // We cannot do the composite conditions, at least not in SSA form.
4287 if ((X86::CondCode)Cond[0].getImm() > X86::COND_S)
4288 return false;
4289
4290 // Check register classes.
4291 const MachineRegisterInfo &MRI = MBB.getParent()->getRegInfo();
4292 const TargetRegisterClass *RC =
4293 RI.getCommonSubClass(MRI.getRegClass(TrueReg), MRI.getRegClass(FalseReg));
4294 if (!RC)
4295 return false;
4296
4297 // We have cmov instructions for 16, 32, and 64 bit general purpose registers.
4298 if (X86::GR16RegClass.hasSubClassEq(RC) ||
4299 X86::GR32RegClass.hasSubClassEq(RC) ||
4300 X86::GR64RegClass.hasSubClassEq(RC)) {
4301 // This latency applies to Pentium M, Merom, Wolfdale, Nehalem, and Sandy
4302 // Bridge. Probably Ivy Bridge as well.
4303 CondCycles = 2;
4304 TrueCycles = 2;
4305 FalseCycles = 2;
4306 return true;
4307 }
4308
4309 // Can't do vectors.
4310 return false;
4311 }
4312
insertSelect(MachineBasicBlock & MBB,MachineBasicBlock::iterator I,const DebugLoc & DL,unsigned DstReg,ArrayRef<MachineOperand> Cond,unsigned TrueReg,unsigned FalseReg) const4313 void X86InstrInfo::insertSelect(MachineBasicBlock &MBB,
4314 MachineBasicBlock::iterator I,
4315 const DebugLoc &DL, unsigned DstReg,
4316 ArrayRef<MachineOperand> Cond, unsigned TrueReg,
4317 unsigned FalseReg) const {
4318 MachineRegisterInfo &MRI = MBB.getParent()->getRegInfo();
4319 assert(Cond.size() == 1 && "Invalid Cond array");
4320 unsigned Opc = getCMovFromCond((X86::CondCode)Cond[0].getImm(),
4321 MRI.getRegClass(DstReg)->getSize(),
4322 false /*HasMemoryOperand*/);
4323 BuildMI(MBB, I, DL, get(Opc), DstReg).addReg(FalseReg).addReg(TrueReg);
4324 }
4325
4326 /// Test if the given register is a physical h register.
isHReg(unsigned Reg)4327 static bool isHReg(unsigned Reg) {
4328 return X86::GR8_ABCD_HRegClass.contains(Reg);
4329 }
4330
4331 // Try and copy between VR128/VR64 and GR64 registers.
CopyToFromAsymmetricReg(unsigned DestReg,unsigned SrcReg,const X86Subtarget & Subtarget)4332 static unsigned CopyToFromAsymmetricReg(unsigned DestReg, unsigned SrcReg,
4333 const X86Subtarget &Subtarget) {
4334
4335 // SrcReg(VR128) -> DestReg(GR64)
4336 // SrcReg(VR64) -> DestReg(GR64)
4337 // SrcReg(GR64) -> DestReg(VR128)
4338 // SrcReg(GR64) -> DestReg(VR64)
4339
4340 bool HasAVX = Subtarget.hasAVX();
4341 bool HasAVX512 = Subtarget.hasAVX512();
4342 if (X86::GR64RegClass.contains(DestReg)) {
4343 if (X86::VR128XRegClass.contains(SrcReg))
4344 // Copy from a VR128 register to a GR64 register.
4345 return HasAVX512 ? X86::VMOVPQIto64Zrr: (HasAVX ? X86::VMOVPQIto64rr :
4346 X86::MOVPQIto64rr);
4347 if (X86::VR64RegClass.contains(SrcReg))
4348 // Copy from a VR64 register to a GR64 register.
4349 return X86::MMX_MOVD64from64rr;
4350 } else if (X86::GR64RegClass.contains(SrcReg)) {
4351 // Copy from a GR64 register to a VR128 register.
4352 if (X86::VR128XRegClass.contains(DestReg))
4353 return HasAVX512 ? X86::VMOV64toPQIZrr: (HasAVX ? X86::VMOV64toPQIrr :
4354 X86::MOV64toPQIrr);
4355 // Copy from a GR64 register to a VR64 register.
4356 if (X86::VR64RegClass.contains(DestReg))
4357 return X86::MMX_MOVD64to64rr;
4358 }
4359
4360 // SrcReg(FR32) -> DestReg(GR32)
4361 // SrcReg(GR32) -> DestReg(FR32)
4362
4363 if (X86::GR32RegClass.contains(DestReg) && X86::FR32XRegClass.contains(SrcReg))
4364 // Copy from a FR32 register to a GR32 register.
4365 return HasAVX512 ? X86::VMOVSS2DIZrr : (HasAVX ? X86::VMOVSS2DIrr : X86::MOVSS2DIrr);
4366
4367 if (X86::FR32XRegClass.contains(DestReg) && X86::GR32RegClass.contains(SrcReg))
4368 // Copy from a GR32 register to a FR32 register.
4369 return HasAVX512 ? X86::VMOVDI2SSZrr : (HasAVX ? X86::VMOVDI2SSrr : X86::MOVDI2SSrr);
4370 return 0;
4371 }
4372
isMaskRegClass(const TargetRegisterClass * RC)4373 static bool isMaskRegClass(const TargetRegisterClass *RC) {
4374 // All KMASK RegClasses hold the same k registers, can be tested against anyone.
4375 return X86::VK16RegClass.hasSubClassEq(RC);
4376 }
4377
MaskRegClassContains(unsigned Reg)4378 static bool MaskRegClassContains(unsigned Reg) {
4379 // All KMASK RegClasses hold the same k registers, can be tested against anyone.
4380 return X86::VK16RegClass.contains(Reg);
4381 }
4382
GRRegClassContains(unsigned Reg)4383 static bool GRRegClassContains(unsigned Reg) {
4384 return X86::GR64RegClass.contains(Reg) ||
4385 X86::GR32RegClass.contains(Reg) ||
4386 X86::GR16RegClass.contains(Reg) ||
4387 X86::GR8RegClass.contains(Reg);
4388 }
4389 static
copyPhysRegOpcode_AVX512_DQ(unsigned & DestReg,unsigned & SrcReg)4390 unsigned copyPhysRegOpcode_AVX512_DQ(unsigned& DestReg, unsigned& SrcReg) {
4391 if (MaskRegClassContains(SrcReg) && X86::GR8RegClass.contains(DestReg)) {
4392 DestReg = getX86SubSuperRegister(DestReg, 32);
4393 return X86::KMOVBrk;
4394 }
4395 if (MaskRegClassContains(DestReg) && X86::GR8RegClass.contains(SrcReg)) {
4396 SrcReg = getX86SubSuperRegister(SrcReg, 32);
4397 return X86::KMOVBkr;
4398 }
4399 return 0;
4400 }
4401
4402 static
copyPhysRegOpcode_AVX512_BW(unsigned & DestReg,unsigned & SrcReg)4403 unsigned copyPhysRegOpcode_AVX512_BW(unsigned& DestReg, unsigned& SrcReg) {
4404 if (MaskRegClassContains(SrcReg) && MaskRegClassContains(DestReg))
4405 return X86::KMOVQkk;
4406 if (MaskRegClassContains(SrcReg) && X86::GR32RegClass.contains(DestReg))
4407 return X86::KMOVDrk;
4408 if (MaskRegClassContains(SrcReg) && X86::GR64RegClass.contains(DestReg))
4409 return X86::KMOVQrk;
4410 if (MaskRegClassContains(DestReg) && X86::GR32RegClass.contains(SrcReg))
4411 return X86::KMOVDkr;
4412 if (MaskRegClassContains(DestReg) && X86::GR64RegClass.contains(SrcReg))
4413 return X86::KMOVQkr;
4414 return 0;
4415 }
4416
4417 static
copyPhysRegOpcode_AVX512(unsigned & DestReg,unsigned & SrcReg,const X86Subtarget & Subtarget)4418 unsigned copyPhysRegOpcode_AVX512(unsigned& DestReg, unsigned& SrcReg,
4419 const X86Subtarget &Subtarget)
4420 {
4421 if (Subtarget.hasDQI())
4422 if (auto Opc = copyPhysRegOpcode_AVX512_DQ(DestReg, SrcReg))
4423 return Opc;
4424 if (Subtarget.hasBWI())
4425 if (auto Opc = copyPhysRegOpcode_AVX512_BW(DestReg, SrcReg))
4426 return Opc;
4427 if (X86::VR128XRegClass.contains(DestReg, SrcReg) ||
4428 X86::VR256XRegClass.contains(DestReg, SrcReg) ||
4429 X86::VR512RegClass.contains(DestReg, SrcReg)) {
4430 DestReg = get512BitSuperRegister(DestReg);
4431 SrcReg = get512BitSuperRegister(SrcReg);
4432 return X86::VMOVAPSZrr;
4433 }
4434 if (MaskRegClassContains(DestReg) && MaskRegClassContains(SrcReg))
4435 return X86::KMOVWkk;
4436 if (MaskRegClassContains(DestReg) && GRRegClassContains(SrcReg)) {
4437 SrcReg = getX86SubSuperRegister(SrcReg, 32);
4438 return X86::KMOVWkr;
4439 }
4440 if (GRRegClassContains(DestReg) && MaskRegClassContains(SrcReg)) {
4441 DestReg = getX86SubSuperRegister(DestReg, 32);
4442 return X86::KMOVWrk;
4443 }
4444 return 0;
4445 }
4446
copyPhysReg(MachineBasicBlock & MBB,MachineBasicBlock::iterator MI,const DebugLoc & DL,unsigned DestReg,unsigned SrcReg,bool KillSrc) const4447 void X86InstrInfo::copyPhysReg(MachineBasicBlock &MBB,
4448 MachineBasicBlock::iterator MI,
4449 const DebugLoc &DL, unsigned DestReg,
4450 unsigned SrcReg, bool KillSrc) const {
4451 // First deal with the normal symmetric copies.
4452 bool HasAVX = Subtarget.hasAVX();
4453 bool HasAVX512 = Subtarget.hasAVX512();
4454 unsigned Opc = 0;
4455 if (X86::GR64RegClass.contains(DestReg, SrcReg))
4456 Opc = X86::MOV64rr;
4457 else if (X86::GR32RegClass.contains(DestReg, SrcReg))
4458 Opc = X86::MOV32rr;
4459 else if (X86::GR16RegClass.contains(DestReg, SrcReg))
4460 Opc = X86::MOV16rr;
4461 else if (X86::GR8RegClass.contains(DestReg, SrcReg)) {
4462 // Copying to or from a physical H register on x86-64 requires a NOREX
4463 // move. Otherwise use a normal move.
4464 if ((isHReg(DestReg) || isHReg(SrcReg)) &&
4465 Subtarget.is64Bit()) {
4466 Opc = X86::MOV8rr_NOREX;
4467 // Both operands must be encodable without an REX prefix.
4468 assert(X86::GR8_NOREXRegClass.contains(SrcReg, DestReg) &&
4469 "8-bit H register can not be copied outside GR8_NOREX");
4470 } else
4471 Opc = X86::MOV8rr;
4472 }
4473 else if (X86::VR64RegClass.contains(DestReg, SrcReg))
4474 Opc = X86::MMX_MOVQ64rr;
4475 else if (HasAVX512)
4476 Opc = copyPhysRegOpcode_AVX512(DestReg, SrcReg, Subtarget);
4477 else if (X86::VR128RegClass.contains(DestReg, SrcReg))
4478 Opc = HasAVX ? X86::VMOVAPSrr : X86::MOVAPSrr;
4479 else if (X86::VR256RegClass.contains(DestReg, SrcReg))
4480 Opc = X86::VMOVAPSYrr;
4481 if (!Opc)
4482 Opc = CopyToFromAsymmetricReg(DestReg, SrcReg, Subtarget);
4483
4484 if (Opc) {
4485 BuildMI(MBB, MI, DL, get(Opc), DestReg)
4486 .addReg(SrcReg, getKillRegState(KillSrc));
4487 return;
4488 }
4489
4490 bool FromEFLAGS = SrcReg == X86::EFLAGS;
4491 bool ToEFLAGS = DestReg == X86::EFLAGS;
4492 int Reg = FromEFLAGS ? DestReg : SrcReg;
4493 bool is32 = X86::GR32RegClass.contains(Reg);
4494 bool is64 = X86::GR64RegClass.contains(Reg);
4495
4496 if ((FromEFLAGS || ToEFLAGS) && (is32 || is64)) {
4497 int Mov = is64 ? X86::MOV64rr : X86::MOV32rr;
4498 int Push = is64 ? X86::PUSH64r : X86::PUSH32r;
4499 int PushF = is64 ? X86::PUSHF64 : X86::PUSHF32;
4500 int Pop = is64 ? X86::POP64r : X86::POP32r;
4501 int PopF = is64 ? X86::POPF64 : X86::POPF32;
4502 int AX = is64 ? X86::RAX : X86::EAX;
4503
4504 if (!Subtarget.hasLAHFSAHF()) {
4505 assert(Subtarget.is64Bit() &&
4506 "Not having LAHF/SAHF only happens on 64-bit.");
4507 // Moving EFLAGS to / from another register requires a push and a pop.
4508 // Notice that we have to adjust the stack if we don't want to clobber the
4509 // first frame index. See X86FrameLowering.cpp - usesTheStack.
4510 if (FromEFLAGS) {
4511 BuildMI(MBB, MI, DL, get(PushF));
4512 BuildMI(MBB, MI, DL, get(Pop), DestReg);
4513 }
4514 if (ToEFLAGS) {
4515 BuildMI(MBB, MI, DL, get(Push))
4516 .addReg(SrcReg, getKillRegState(KillSrc));
4517 BuildMI(MBB, MI, DL, get(PopF));
4518 }
4519 return;
4520 }
4521
4522 // The flags need to be saved, but saving EFLAGS with PUSHF/POPF is
4523 // inefficient. Instead:
4524 // - Save the overflow flag OF into AL using SETO, and restore it using a
4525 // signed 8-bit addition of AL and INT8_MAX.
4526 // - Save/restore the bottom 8 EFLAGS bits (CF, PF, AF, ZF, SF) to/from AH
4527 // using LAHF/SAHF.
4528 // - When RAX/EAX is live and isn't the destination register, make sure it
4529 // isn't clobbered by PUSH/POP'ing it before and after saving/restoring
4530 // the flags.
4531 // This approach is ~2.25x faster than using PUSHF/POPF.
4532 //
4533 // This is still somewhat inefficient because we don't know which flags are
4534 // actually live inside EFLAGS. Were we able to do a single SETcc instead of
4535 // SETO+LAHF / ADDB+SAHF the code could be 1.02x faster.
4536 //
4537 // PUSHF/POPF is also potentially incorrect because it affects other flags
4538 // such as TF/IF/DF, which LLVM doesn't model.
4539 //
4540 // Notice that we have to adjust the stack if we don't want to clobber the
4541 // first frame index.
4542 // See X86ISelLowering.cpp - X86::hasCopyImplyingStackAdjustment.
4543
4544 const TargetRegisterInfo *TRI = &getRegisterInfo();
4545 MachineBasicBlock::LivenessQueryResult LQR =
4546 MBB.computeRegisterLiveness(TRI, AX, MI);
4547 // We do not want to save and restore AX if we do not have to.
4548 // Moreover, if we do so whereas AX is dead, we would need to set
4549 // an undef flag on the use of AX, otherwise the verifier will
4550 // complain that we read an undef value.
4551 // We do not want to change the behavior of the machine verifier
4552 // as this is usually wrong to read an undef value.
4553 if (MachineBasicBlock::LQR_Unknown == LQR) {
4554 LivePhysRegs LPR(TRI);
4555 LPR.addLiveOuts(MBB);
4556 MachineBasicBlock::iterator I = MBB.end();
4557 while (I != MI) {
4558 --I;
4559 LPR.stepBackward(*I);
4560 }
4561 // AX contains the top most register in the aliasing hierarchy.
4562 // It may not be live, but one of its aliases may be.
4563 for (MCRegAliasIterator AI(AX, TRI, true);
4564 AI.isValid() && LQR != MachineBasicBlock::LQR_Live; ++AI)
4565 LQR = LPR.contains(*AI) ? MachineBasicBlock::LQR_Live
4566 : MachineBasicBlock::LQR_Dead;
4567 }
4568 bool AXDead = (Reg == AX) || (MachineBasicBlock::LQR_Dead == LQR);
4569 if (!AXDead)
4570 BuildMI(MBB, MI, DL, get(Push)).addReg(AX, getKillRegState(true));
4571 if (FromEFLAGS) {
4572 BuildMI(MBB, MI, DL, get(X86::SETOr), X86::AL);
4573 BuildMI(MBB, MI, DL, get(X86::LAHF));
4574 BuildMI(MBB, MI, DL, get(Mov), Reg).addReg(AX);
4575 }
4576 if (ToEFLAGS) {
4577 BuildMI(MBB, MI, DL, get(Mov), AX).addReg(Reg, getKillRegState(KillSrc));
4578 BuildMI(MBB, MI, DL, get(X86::ADD8ri), X86::AL)
4579 .addReg(X86::AL)
4580 .addImm(INT8_MAX);
4581 BuildMI(MBB, MI, DL, get(X86::SAHF));
4582 }
4583 if (!AXDead)
4584 BuildMI(MBB, MI, DL, get(Pop), AX);
4585 return;
4586 }
4587
4588 DEBUG(dbgs() << "Cannot copy " << RI.getName(SrcReg)
4589 << " to " << RI.getName(DestReg) << '\n');
4590 llvm_unreachable("Cannot emit physreg copy instruction");
4591 }
4592
getLoadStoreMaskRegOpcode(const TargetRegisterClass * RC,bool load)4593 static unsigned getLoadStoreMaskRegOpcode(const TargetRegisterClass *RC,
4594 bool load) {
4595 switch (RC->getSize()) {
4596 default:
4597 llvm_unreachable("Unknown spill size");
4598 case 2:
4599 return load ? X86::KMOVWkm : X86::KMOVWmk;
4600 case 4:
4601 return load ? X86::KMOVDkm : X86::KMOVDmk;
4602 case 8:
4603 return load ? X86::KMOVQkm : X86::KMOVQmk;
4604 }
4605 }
4606
getLoadStoreRegOpcode(unsigned Reg,const TargetRegisterClass * RC,bool isStackAligned,const X86Subtarget & STI,bool load)4607 static unsigned getLoadStoreRegOpcode(unsigned Reg,
4608 const TargetRegisterClass *RC,
4609 bool isStackAligned,
4610 const X86Subtarget &STI,
4611 bool load) {
4612 if (STI.hasAVX512()) {
4613 if (isMaskRegClass(RC))
4614 return getLoadStoreMaskRegOpcode(RC, load);
4615 if (RC->getSize() == 4 && X86::FR32XRegClass.hasSubClassEq(RC))
4616 return load ? X86::VMOVSSZrm : X86::VMOVSSZmr;
4617 if (RC->getSize() == 8 && X86::FR64XRegClass.hasSubClassEq(RC))
4618 return load ? X86::VMOVSDZrm : X86::VMOVSDZmr;
4619 if (X86::VR512RegClass.hasSubClassEq(RC))
4620 return load ? X86::VMOVUPSZrm : X86::VMOVUPSZmr;
4621 }
4622
4623 bool HasAVX = STI.hasAVX();
4624 switch (RC->getSize()) {
4625 default:
4626 llvm_unreachable("Unknown spill size");
4627 case 1:
4628 assert(X86::GR8RegClass.hasSubClassEq(RC) && "Unknown 1-byte regclass");
4629 if (STI.is64Bit())
4630 // Copying to or from a physical H register on x86-64 requires a NOREX
4631 // move. Otherwise use a normal move.
4632 if (isHReg(Reg) || X86::GR8_ABCD_HRegClass.hasSubClassEq(RC))
4633 return load ? X86::MOV8rm_NOREX : X86::MOV8mr_NOREX;
4634 return load ? X86::MOV8rm : X86::MOV8mr;
4635 case 2:
4636 assert(X86::GR16RegClass.hasSubClassEq(RC) && "Unknown 2-byte regclass");
4637 return load ? X86::MOV16rm : X86::MOV16mr;
4638 case 4:
4639 if (X86::GR32RegClass.hasSubClassEq(RC))
4640 return load ? X86::MOV32rm : X86::MOV32mr;
4641 if (X86::FR32RegClass.hasSubClassEq(RC))
4642 return load ?
4643 (HasAVX ? X86::VMOVSSrm : X86::MOVSSrm) :
4644 (HasAVX ? X86::VMOVSSmr : X86::MOVSSmr);
4645 if (X86::RFP32RegClass.hasSubClassEq(RC))
4646 return load ? X86::LD_Fp32m : X86::ST_Fp32m;
4647 llvm_unreachable("Unknown 4-byte regclass");
4648 case 8:
4649 if (X86::GR64RegClass.hasSubClassEq(RC))
4650 return load ? X86::MOV64rm : X86::MOV64mr;
4651 if (X86::FR64RegClass.hasSubClassEq(RC))
4652 return load ?
4653 (HasAVX ? X86::VMOVSDrm : X86::MOVSDrm) :
4654 (HasAVX ? X86::VMOVSDmr : X86::MOVSDmr);
4655 if (X86::VR64RegClass.hasSubClassEq(RC))
4656 return load ? X86::MMX_MOVQ64rm : X86::MMX_MOVQ64mr;
4657 if (X86::RFP64RegClass.hasSubClassEq(RC))
4658 return load ? X86::LD_Fp64m : X86::ST_Fp64m;
4659 llvm_unreachable("Unknown 8-byte regclass");
4660 case 10:
4661 assert(X86::RFP80RegClass.hasSubClassEq(RC) && "Unknown 10-byte regclass");
4662 return load ? X86::LD_Fp80m : X86::ST_FpP80m;
4663 case 16: {
4664 assert((X86::VR128RegClass.hasSubClassEq(RC) ||
4665 X86::VR128XRegClass.hasSubClassEq(RC))&& "Unknown 16-byte regclass");
4666 // If stack is realigned we can use aligned stores.
4667 if (X86::VR128RegClass.hasSubClassEq(RC)) {
4668 if (isStackAligned)
4669 return load ? (HasAVX ? X86::VMOVAPSrm : X86::MOVAPSrm)
4670 : (HasAVX ? X86::VMOVAPSmr : X86::MOVAPSmr);
4671 else
4672 return load ? (HasAVX ? X86::VMOVUPSrm : X86::MOVUPSrm)
4673 : (HasAVX ? X86::VMOVUPSmr : X86::MOVUPSmr);
4674 }
4675 assert(STI.hasVLX() && "Using extended register requires VLX");
4676 if (isStackAligned)
4677 return load ? X86::VMOVAPSZ128rm : X86::VMOVAPSZ128mr;
4678 else
4679 return load ? X86::VMOVUPSZ128rm : X86::VMOVUPSZ128mr;
4680 }
4681 case 32:
4682 assert((X86::VR256RegClass.hasSubClassEq(RC) ||
4683 X86::VR256XRegClass.hasSubClassEq(RC)) && "Unknown 32-byte regclass");
4684 // If stack is realigned we can use aligned stores.
4685 if (X86::VR256RegClass.hasSubClassEq(RC)) {
4686 if (isStackAligned)
4687 return load ? X86::VMOVAPSYrm : X86::VMOVAPSYmr;
4688 else
4689 return load ? X86::VMOVUPSYrm : X86::VMOVUPSYmr;
4690 }
4691 assert(STI.hasVLX() && "Using extended register requires VLX");
4692 if (isStackAligned)
4693 return load ? X86::VMOVAPSZ256rm : X86::VMOVAPSZ256mr;
4694 else
4695 return load ? X86::VMOVUPSZ256rm : X86::VMOVUPSZ256mr;
4696 case 64:
4697 assert(X86::VR512RegClass.hasSubClassEq(RC) && "Unknown 64-byte regclass");
4698 assert(STI.hasVLX() && "Using 512-bit register requires AVX512");
4699 if (isStackAligned)
4700 return load ? X86::VMOVAPSZrm : X86::VMOVAPSZmr;
4701 else
4702 return load ? X86::VMOVUPSZrm : X86::VMOVUPSZmr;
4703 }
4704 }
4705
getMemOpBaseRegImmOfs(MachineInstr & MemOp,unsigned & BaseReg,int64_t & Offset,const TargetRegisterInfo * TRI) const4706 bool X86InstrInfo::getMemOpBaseRegImmOfs(MachineInstr &MemOp, unsigned &BaseReg,
4707 int64_t &Offset,
4708 const TargetRegisterInfo *TRI) const {
4709 const MCInstrDesc &Desc = MemOp.getDesc();
4710 int MemRefBegin = X86II::getMemoryOperandNo(Desc.TSFlags);
4711 if (MemRefBegin < 0)
4712 return false;
4713
4714 MemRefBegin += X86II::getOperandBias(Desc);
4715
4716 MachineOperand &BaseMO = MemOp.getOperand(MemRefBegin + X86::AddrBaseReg);
4717 if (!BaseMO.isReg()) // Can be an MO_FrameIndex
4718 return false;
4719
4720 BaseReg = BaseMO.getReg();
4721 if (MemOp.getOperand(MemRefBegin + X86::AddrScaleAmt).getImm() != 1)
4722 return false;
4723
4724 if (MemOp.getOperand(MemRefBegin + X86::AddrIndexReg).getReg() !=
4725 X86::NoRegister)
4726 return false;
4727
4728 const MachineOperand &DispMO = MemOp.getOperand(MemRefBegin + X86::AddrDisp);
4729
4730 // Displacement can be symbolic
4731 if (!DispMO.isImm())
4732 return false;
4733
4734 Offset = DispMO.getImm();
4735
4736 return MemOp.getOperand(MemRefBegin + X86::AddrIndexReg).getReg() ==
4737 X86::NoRegister;
4738 }
4739
getStoreRegOpcode(unsigned SrcReg,const TargetRegisterClass * RC,bool isStackAligned,const X86Subtarget & STI)4740 static unsigned getStoreRegOpcode(unsigned SrcReg,
4741 const TargetRegisterClass *RC,
4742 bool isStackAligned,
4743 const X86Subtarget &STI) {
4744 return getLoadStoreRegOpcode(SrcReg, RC, isStackAligned, STI, false);
4745 }
4746
4747
getLoadRegOpcode(unsigned DestReg,const TargetRegisterClass * RC,bool isStackAligned,const X86Subtarget & STI)4748 static unsigned getLoadRegOpcode(unsigned DestReg,
4749 const TargetRegisterClass *RC,
4750 bool isStackAligned,
4751 const X86Subtarget &STI) {
4752 return getLoadStoreRegOpcode(DestReg, RC, isStackAligned, STI, true);
4753 }
4754
storeRegToStackSlot(MachineBasicBlock & MBB,MachineBasicBlock::iterator MI,unsigned SrcReg,bool isKill,int FrameIdx,const TargetRegisterClass * RC,const TargetRegisterInfo * TRI) const4755 void X86InstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
4756 MachineBasicBlock::iterator MI,
4757 unsigned SrcReg, bool isKill, int FrameIdx,
4758 const TargetRegisterClass *RC,
4759 const TargetRegisterInfo *TRI) const {
4760 const MachineFunction &MF = *MBB.getParent();
4761 assert(MF.getFrameInfo()->getObjectSize(FrameIdx) >= RC->getSize() &&
4762 "Stack slot too small for store");
4763 unsigned Alignment = std::max<uint32_t>(RC->getSize(), 16);
4764 bool isAligned =
4765 (Subtarget.getFrameLowering()->getStackAlignment() >= Alignment) ||
4766 RI.canRealignStack(MF);
4767 unsigned Opc = getStoreRegOpcode(SrcReg, RC, isAligned, Subtarget);
4768 DebugLoc DL = MBB.findDebugLoc(MI);
4769 addFrameReference(BuildMI(MBB, MI, DL, get(Opc)), FrameIdx)
4770 .addReg(SrcReg, getKillRegState(isKill));
4771 }
4772
storeRegToAddr(MachineFunction & MF,unsigned SrcReg,bool isKill,SmallVectorImpl<MachineOperand> & Addr,const TargetRegisterClass * RC,MachineInstr::mmo_iterator MMOBegin,MachineInstr::mmo_iterator MMOEnd,SmallVectorImpl<MachineInstr * > & NewMIs) const4773 void X86InstrInfo::storeRegToAddr(MachineFunction &MF, unsigned SrcReg,
4774 bool isKill,
4775 SmallVectorImpl<MachineOperand> &Addr,
4776 const TargetRegisterClass *RC,
4777 MachineInstr::mmo_iterator MMOBegin,
4778 MachineInstr::mmo_iterator MMOEnd,
4779 SmallVectorImpl<MachineInstr*> &NewMIs) const {
4780 unsigned Alignment = std::max<uint32_t>(RC->getSize(), 16);
4781 bool isAligned = MMOBegin != MMOEnd &&
4782 (*MMOBegin)->getAlignment() >= Alignment;
4783 unsigned Opc = getStoreRegOpcode(SrcReg, RC, isAligned, Subtarget);
4784 DebugLoc DL;
4785 MachineInstrBuilder MIB = BuildMI(MF, DL, get(Opc));
4786 for (unsigned i = 0, e = Addr.size(); i != e; ++i)
4787 MIB.addOperand(Addr[i]);
4788 MIB.addReg(SrcReg, getKillRegState(isKill));
4789 (*MIB).setMemRefs(MMOBegin, MMOEnd);
4790 NewMIs.push_back(MIB);
4791 }
4792
4793
loadRegFromStackSlot(MachineBasicBlock & MBB,MachineBasicBlock::iterator MI,unsigned DestReg,int FrameIdx,const TargetRegisterClass * RC,const TargetRegisterInfo * TRI) const4794 void X86InstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
4795 MachineBasicBlock::iterator MI,
4796 unsigned DestReg, int FrameIdx,
4797 const TargetRegisterClass *RC,
4798 const TargetRegisterInfo *TRI) const {
4799 const MachineFunction &MF = *MBB.getParent();
4800 unsigned Alignment = std::max<uint32_t>(RC->getSize(), 16);
4801 bool isAligned =
4802 (Subtarget.getFrameLowering()->getStackAlignment() >= Alignment) ||
4803 RI.canRealignStack(MF);
4804 unsigned Opc = getLoadRegOpcode(DestReg, RC, isAligned, Subtarget);
4805 DebugLoc DL = MBB.findDebugLoc(MI);
4806 addFrameReference(BuildMI(MBB, MI, DL, get(Opc), DestReg), FrameIdx);
4807 }
4808
loadRegFromAddr(MachineFunction & MF,unsigned DestReg,SmallVectorImpl<MachineOperand> & Addr,const TargetRegisterClass * RC,MachineInstr::mmo_iterator MMOBegin,MachineInstr::mmo_iterator MMOEnd,SmallVectorImpl<MachineInstr * > & NewMIs) const4809 void X86InstrInfo::loadRegFromAddr(MachineFunction &MF, unsigned DestReg,
4810 SmallVectorImpl<MachineOperand> &Addr,
4811 const TargetRegisterClass *RC,
4812 MachineInstr::mmo_iterator MMOBegin,
4813 MachineInstr::mmo_iterator MMOEnd,
4814 SmallVectorImpl<MachineInstr*> &NewMIs) const {
4815 unsigned Alignment = std::max<uint32_t>(RC->getSize(), 16);
4816 bool isAligned = MMOBegin != MMOEnd &&
4817 (*MMOBegin)->getAlignment() >= Alignment;
4818 unsigned Opc = getLoadRegOpcode(DestReg, RC, isAligned, Subtarget);
4819 DebugLoc DL;
4820 MachineInstrBuilder MIB = BuildMI(MF, DL, get(Opc), DestReg);
4821 for (unsigned i = 0, e = Addr.size(); i != e; ++i)
4822 MIB.addOperand(Addr[i]);
4823 (*MIB).setMemRefs(MMOBegin, MMOEnd);
4824 NewMIs.push_back(MIB);
4825 }
4826
analyzeCompare(const MachineInstr & MI,unsigned & SrcReg,unsigned & SrcReg2,int & CmpMask,int & CmpValue) const4827 bool X86InstrInfo::analyzeCompare(const MachineInstr &MI, unsigned &SrcReg,
4828 unsigned &SrcReg2, int &CmpMask,
4829 int &CmpValue) const {
4830 switch (MI.getOpcode()) {
4831 default: break;
4832 case X86::CMP64ri32:
4833 case X86::CMP64ri8:
4834 case X86::CMP32ri:
4835 case X86::CMP32ri8:
4836 case X86::CMP16ri:
4837 case X86::CMP16ri8:
4838 case X86::CMP8ri:
4839 SrcReg = MI.getOperand(0).getReg();
4840 SrcReg2 = 0;
4841 CmpMask = ~0;
4842 CmpValue = MI.getOperand(1).getImm();
4843 return true;
4844 // A SUB can be used to perform comparison.
4845 case X86::SUB64rm:
4846 case X86::SUB32rm:
4847 case X86::SUB16rm:
4848 case X86::SUB8rm:
4849 SrcReg = MI.getOperand(1).getReg();
4850 SrcReg2 = 0;
4851 CmpMask = ~0;
4852 CmpValue = 0;
4853 return true;
4854 case X86::SUB64rr:
4855 case X86::SUB32rr:
4856 case X86::SUB16rr:
4857 case X86::SUB8rr:
4858 SrcReg = MI.getOperand(1).getReg();
4859 SrcReg2 = MI.getOperand(2).getReg();
4860 CmpMask = ~0;
4861 CmpValue = 0;
4862 return true;
4863 case X86::SUB64ri32:
4864 case X86::SUB64ri8:
4865 case X86::SUB32ri:
4866 case X86::SUB32ri8:
4867 case X86::SUB16ri:
4868 case X86::SUB16ri8:
4869 case X86::SUB8ri:
4870 SrcReg = MI.getOperand(1).getReg();
4871 SrcReg2 = 0;
4872 CmpMask = ~0;
4873 CmpValue = MI.getOperand(2).getImm();
4874 return true;
4875 case X86::CMP64rr:
4876 case X86::CMP32rr:
4877 case X86::CMP16rr:
4878 case X86::CMP8rr:
4879 SrcReg = MI.getOperand(0).getReg();
4880 SrcReg2 = MI.getOperand(1).getReg();
4881 CmpMask = ~0;
4882 CmpValue = 0;
4883 return true;
4884 case X86::TEST8rr:
4885 case X86::TEST16rr:
4886 case X86::TEST32rr:
4887 case X86::TEST64rr:
4888 SrcReg = MI.getOperand(0).getReg();
4889 if (MI.getOperand(1).getReg() != SrcReg)
4890 return false;
4891 // Compare against zero.
4892 SrcReg2 = 0;
4893 CmpMask = ~0;
4894 CmpValue = 0;
4895 return true;
4896 }
4897 return false;
4898 }
4899
4900 /// Check whether the first instruction, whose only
4901 /// purpose is to update flags, can be made redundant.
4902 /// CMPrr can be made redundant by SUBrr if the operands are the same.
4903 /// This function can be extended later on.
4904 /// SrcReg, SrcRegs: register operands for FlagI.
4905 /// ImmValue: immediate for FlagI if it takes an immediate.
isRedundantFlagInstr(MachineInstr & FlagI,unsigned SrcReg,unsigned SrcReg2,int ImmValue,MachineInstr & OI)4906 inline static bool isRedundantFlagInstr(MachineInstr &FlagI, unsigned SrcReg,
4907 unsigned SrcReg2, int ImmValue,
4908 MachineInstr &OI) {
4909 if (((FlagI.getOpcode() == X86::CMP64rr && OI.getOpcode() == X86::SUB64rr) ||
4910 (FlagI.getOpcode() == X86::CMP32rr && OI.getOpcode() == X86::SUB32rr) ||
4911 (FlagI.getOpcode() == X86::CMP16rr && OI.getOpcode() == X86::SUB16rr) ||
4912 (FlagI.getOpcode() == X86::CMP8rr && OI.getOpcode() == X86::SUB8rr)) &&
4913 ((OI.getOperand(1).getReg() == SrcReg &&
4914 OI.getOperand(2).getReg() == SrcReg2) ||
4915 (OI.getOperand(1).getReg() == SrcReg2 &&
4916 OI.getOperand(2).getReg() == SrcReg)))
4917 return true;
4918
4919 if (((FlagI.getOpcode() == X86::CMP64ri32 &&
4920 OI.getOpcode() == X86::SUB64ri32) ||
4921 (FlagI.getOpcode() == X86::CMP64ri8 &&
4922 OI.getOpcode() == X86::SUB64ri8) ||
4923 (FlagI.getOpcode() == X86::CMP32ri && OI.getOpcode() == X86::SUB32ri) ||
4924 (FlagI.getOpcode() == X86::CMP32ri8 &&
4925 OI.getOpcode() == X86::SUB32ri8) ||
4926 (FlagI.getOpcode() == X86::CMP16ri && OI.getOpcode() == X86::SUB16ri) ||
4927 (FlagI.getOpcode() == X86::CMP16ri8 &&
4928 OI.getOpcode() == X86::SUB16ri8) ||
4929 (FlagI.getOpcode() == X86::CMP8ri && OI.getOpcode() == X86::SUB8ri)) &&
4930 OI.getOperand(1).getReg() == SrcReg &&
4931 OI.getOperand(2).getImm() == ImmValue)
4932 return true;
4933 return false;
4934 }
4935
4936 /// Check whether the definition can be converted
4937 /// to remove a comparison against zero.
isDefConvertible(MachineInstr & MI)4938 inline static bool isDefConvertible(MachineInstr &MI) {
4939 switch (MI.getOpcode()) {
4940 default: return false;
4941
4942 // The shift instructions only modify ZF if their shift count is non-zero.
4943 // N.B.: The processor truncates the shift count depending on the encoding.
4944 case X86::SAR8ri: case X86::SAR16ri: case X86::SAR32ri:case X86::SAR64ri:
4945 case X86::SHR8ri: case X86::SHR16ri: case X86::SHR32ri:case X86::SHR64ri:
4946 return getTruncatedShiftCount(MI, 2) != 0;
4947
4948 // Some left shift instructions can be turned into LEA instructions but only
4949 // if their flags aren't used. Avoid transforming such instructions.
4950 case X86::SHL8ri: case X86::SHL16ri: case X86::SHL32ri:case X86::SHL64ri:{
4951 unsigned ShAmt = getTruncatedShiftCount(MI, 2);
4952 if (isTruncatedShiftCountForLEA(ShAmt)) return false;
4953 return ShAmt != 0;
4954 }
4955
4956 case X86::SHRD16rri8:case X86::SHRD32rri8:case X86::SHRD64rri8:
4957 case X86::SHLD16rri8:case X86::SHLD32rri8:case X86::SHLD64rri8:
4958 return getTruncatedShiftCount(MI, 3) != 0;
4959
4960 case X86::SUB64ri32: case X86::SUB64ri8: case X86::SUB32ri:
4961 case X86::SUB32ri8: case X86::SUB16ri: case X86::SUB16ri8:
4962 case X86::SUB8ri: case X86::SUB64rr: case X86::SUB32rr:
4963 case X86::SUB16rr: case X86::SUB8rr: case X86::SUB64rm:
4964 case X86::SUB32rm: case X86::SUB16rm: case X86::SUB8rm:
4965 case X86::DEC64r: case X86::DEC32r: case X86::DEC16r: case X86::DEC8r:
4966 case X86::ADD64ri32: case X86::ADD64ri8: case X86::ADD32ri:
4967 case X86::ADD32ri8: case X86::ADD16ri: case X86::ADD16ri8:
4968 case X86::ADD8ri: case X86::ADD64rr: case X86::ADD32rr:
4969 case X86::ADD16rr: case X86::ADD8rr: case X86::ADD64rm:
4970 case X86::ADD32rm: case X86::ADD16rm: case X86::ADD8rm:
4971 case X86::INC64r: case X86::INC32r: case X86::INC16r: case X86::INC8r:
4972 case X86::AND64ri32: case X86::AND64ri8: case X86::AND32ri:
4973 case X86::AND32ri8: case X86::AND16ri: case X86::AND16ri8:
4974 case X86::AND8ri: case X86::AND64rr: case X86::AND32rr:
4975 case X86::AND16rr: case X86::AND8rr: case X86::AND64rm:
4976 case X86::AND32rm: case X86::AND16rm: case X86::AND8rm:
4977 case X86::XOR64ri32: case X86::XOR64ri8: case X86::XOR32ri:
4978 case X86::XOR32ri8: case X86::XOR16ri: case X86::XOR16ri8:
4979 case X86::XOR8ri: case X86::XOR64rr: case X86::XOR32rr:
4980 case X86::XOR16rr: case X86::XOR8rr: case X86::XOR64rm:
4981 case X86::XOR32rm: case X86::XOR16rm: case X86::XOR8rm:
4982 case X86::OR64ri32: case X86::OR64ri8: case X86::OR32ri:
4983 case X86::OR32ri8: case X86::OR16ri: case X86::OR16ri8:
4984 case X86::OR8ri: case X86::OR64rr: case X86::OR32rr:
4985 case X86::OR16rr: case X86::OR8rr: case X86::OR64rm:
4986 case X86::OR32rm: case X86::OR16rm: case X86::OR8rm:
4987 case X86::NEG8r: case X86::NEG16r: case X86::NEG32r: case X86::NEG64r:
4988 case X86::SAR8r1: case X86::SAR16r1: case X86::SAR32r1:case X86::SAR64r1:
4989 case X86::SHR8r1: case X86::SHR16r1: case X86::SHR32r1:case X86::SHR64r1:
4990 case X86::SHL8r1: case X86::SHL16r1: case X86::SHL32r1:case X86::SHL64r1:
4991 case X86::ADC32ri: case X86::ADC32ri8:
4992 case X86::ADC32rr: case X86::ADC64ri32:
4993 case X86::ADC64ri8: case X86::ADC64rr:
4994 case X86::SBB32ri: case X86::SBB32ri8:
4995 case X86::SBB32rr: case X86::SBB64ri32:
4996 case X86::SBB64ri8: case X86::SBB64rr:
4997 case X86::ANDN32rr: case X86::ANDN32rm:
4998 case X86::ANDN64rr: case X86::ANDN64rm:
4999 case X86::BEXTR32rr: case X86::BEXTR64rr:
5000 case X86::BEXTR32rm: case X86::BEXTR64rm:
5001 case X86::BLSI32rr: case X86::BLSI32rm:
5002 case X86::BLSI64rr: case X86::BLSI64rm:
5003 case X86::BLSMSK32rr:case X86::BLSMSK32rm:
5004 case X86::BLSMSK64rr:case X86::BLSMSK64rm:
5005 case X86::BLSR32rr: case X86::BLSR32rm:
5006 case X86::BLSR64rr: case X86::BLSR64rm:
5007 case X86::BZHI32rr: case X86::BZHI32rm:
5008 case X86::BZHI64rr: case X86::BZHI64rm:
5009 case X86::LZCNT16rr: case X86::LZCNT16rm:
5010 case X86::LZCNT32rr: case X86::LZCNT32rm:
5011 case X86::LZCNT64rr: case X86::LZCNT64rm:
5012 case X86::POPCNT16rr:case X86::POPCNT16rm:
5013 case X86::POPCNT32rr:case X86::POPCNT32rm:
5014 case X86::POPCNT64rr:case X86::POPCNT64rm:
5015 case X86::TZCNT16rr: case X86::TZCNT16rm:
5016 case X86::TZCNT32rr: case X86::TZCNT32rm:
5017 case X86::TZCNT64rr: case X86::TZCNT64rm:
5018 return true;
5019 }
5020 }
5021
5022 /// Check whether the use can be converted to remove a comparison against zero.
isUseDefConvertible(MachineInstr & MI)5023 static X86::CondCode isUseDefConvertible(MachineInstr &MI) {
5024 switch (MI.getOpcode()) {
5025 default: return X86::COND_INVALID;
5026 case X86::LZCNT16rr: case X86::LZCNT16rm:
5027 case X86::LZCNT32rr: case X86::LZCNT32rm:
5028 case X86::LZCNT64rr: case X86::LZCNT64rm:
5029 return X86::COND_B;
5030 case X86::POPCNT16rr:case X86::POPCNT16rm:
5031 case X86::POPCNT32rr:case X86::POPCNT32rm:
5032 case X86::POPCNT64rr:case X86::POPCNT64rm:
5033 return X86::COND_E;
5034 case X86::TZCNT16rr: case X86::TZCNT16rm:
5035 case X86::TZCNT32rr: case X86::TZCNT32rm:
5036 case X86::TZCNT64rr: case X86::TZCNT64rm:
5037 return X86::COND_B;
5038 }
5039 }
5040
5041 /// Check if there exists an earlier instruction that
5042 /// operates on the same source operands and sets flags in the same way as
5043 /// Compare; remove Compare if possible.
optimizeCompareInstr(MachineInstr & CmpInstr,unsigned SrcReg,unsigned SrcReg2,int CmpMask,int CmpValue,const MachineRegisterInfo * MRI) const5044 bool X86InstrInfo::optimizeCompareInstr(MachineInstr &CmpInstr, unsigned SrcReg,
5045 unsigned SrcReg2, int CmpMask,
5046 int CmpValue,
5047 const MachineRegisterInfo *MRI) const {
5048 // Check whether we can replace SUB with CMP.
5049 unsigned NewOpcode = 0;
5050 switch (CmpInstr.getOpcode()) {
5051 default: break;
5052 case X86::SUB64ri32:
5053 case X86::SUB64ri8:
5054 case X86::SUB32ri:
5055 case X86::SUB32ri8:
5056 case X86::SUB16ri:
5057 case X86::SUB16ri8:
5058 case X86::SUB8ri:
5059 case X86::SUB64rm:
5060 case X86::SUB32rm:
5061 case X86::SUB16rm:
5062 case X86::SUB8rm:
5063 case X86::SUB64rr:
5064 case X86::SUB32rr:
5065 case X86::SUB16rr:
5066 case X86::SUB8rr: {
5067 if (!MRI->use_nodbg_empty(CmpInstr.getOperand(0).getReg()))
5068 return false;
5069 // There is no use of the destination register, we can replace SUB with CMP.
5070 switch (CmpInstr.getOpcode()) {
5071 default: llvm_unreachable("Unreachable!");
5072 case X86::SUB64rm: NewOpcode = X86::CMP64rm; break;
5073 case X86::SUB32rm: NewOpcode = X86::CMP32rm; break;
5074 case X86::SUB16rm: NewOpcode = X86::CMP16rm; break;
5075 case X86::SUB8rm: NewOpcode = X86::CMP8rm; break;
5076 case X86::SUB64rr: NewOpcode = X86::CMP64rr; break;
5077 case X86::SUB32rr: NewOpcode = X86::CMP32rr; break;
5078 case X86::SUB16rr: NewOpcode = X86::CMP16rr; break;
5079 case X86::SUB8rr: NewOpcode = X86::CMP8rr; break;
5080 case X86::SUB64ri32: NewOpcode = X86::CMP64ri32; break;
5081 case X86::SUB64ri8: NewOpcode = X86::CMP64ri8; break;
5082 case X86::SUB32ri: NewOpcode = X86::CMP32ri; break;
5083 case X86::SUB32ri8: NewOpcode = X86::CMP32ri8; break;
5084 case X86::SUB16ri: NewOpcode = X86::CMP16ri; break;
5085 case X86::SUB16ri8: NewOpcode = X86::CMP16ri8; break;
5086 case X86::SUB8ri: NewOpcode = X86::CMP8ri; break;
5087 }
5088 CmpInstr.setDesc(get(NewOpcode));
5089 CmpInstr.RemoveOperand(0);
5090 // Fall through to optimize Cmp if Cmp is CMPrr or CMPri.
5091 if (NewOpcode == X86::CMP64rm || NewOpcode == X86::CMP32rm ||
5092 NewOpcode == X86::CMP16rm || NewOpcode == X86::CMP8rm)
5093 return false;
5094 }
5095 }
5096
5097 // Get the unique definition of SrcReg.
5098 MachineInstr *MI = MRI->getUniqueVRegDef(SrcReg);
5099 if (!MI) return false;
5100
5101 // CmpInstr is the first instruction of the BB.
5102 MachineBasicBlock::iterator I = CmpInstr, Def = MI;
5103
5104 // If we are comparing against zero, check whether we can use MI to update
5105 // EFLAGS. If MI is not in the same BB as CmpInstr, do not optimize.
5106 bool IsCmpZero = (SrcReg2 == 0 && CmpValue == 0);
5107 if (IsCmpZero && MI->getParent() != CmpInstr.getParent())
5108 return false;
5109
5110 // If we have a use of the source register between the def and our compare
5111 // instruction we can eliminate the compare iff the use sets EFLAGS in the
5112 // right way.
5113 bool ShouldUpdateCC = false;
5114 X86::CondCode NewCC = X86::COND_INVALID;
5115 if (IsCmpZero && !isDefConvertible(*MI)) {
5116 // Scan forward from the use until we hit the use we're looking for or the
5117 // compare instruction.
5118 for (MachineBasicBlock::iterator J = MI;; ++J) {
5119 // Do we have a convertible instruction?
5120 NewCC = isUseDefConvertible(*J);
5121 if (NewCC != X86::COND_INVALID && J->getOperand(1).isReg() &&
5122 J->getOperand(1).getReg() == SrcReg) {
5123 assert(J->definesRegister(X86::EFLAGS) && "Must be an EFLAGS def!");
5124 ShouldUpdateCC = true; // Update CC later on.
5125 // This is not a def of SrcReg, but still a def of EFLAGS. Keep going
5126 // with the new def.
5127 Def = J;
5128 MI = &*Def;
5129 break;
5130 }
5131
5132 if (J == I)
5133 return false;
5134 }
5135 }
5136
5137 // We are searching for an earlier instruction that can make CmpInstr
5138 // redundant and that instruction will be saved in Sub.
5139 MachineInstr *Sub = nullptr;
5140 const TargetRegisterInfo *TRI = &getRegisterInfo();
5141
5142 // We iterate backward, starting from the instruction before CmpInstr and
5143 // stop when reaching the definition of a source register or done with the BB.
5144 // RI points to the instruction before CmpInstr.
5145 // If the definition is in this basic block, RE points to the definition;
5146 // otherwise, RE is the rend of the basic block.
5147 MachineBasicBlock::reverse_iterator
5148 RI = MachineBasicBlock::reverse_iterator(I),
5149 RE = CmpInstr.getParent() == MI->getParent()
5150 ? MachineBasicBlock::reverse_iterator(++Def) /* points to MI */
5151 : CmpInstr.getParent()->rend();
5152 MachineInstr *Movr0Inst = nullptr;
5153 for (; RI != RE; ++RI) {
5154 MachineInstr &Instr = *RI;
5155 // Check whether CmpInstr can be made redundant by the current instruction.
5156 if (!IsCmpZero &&
5157 isRedundantFlagInstr(CmpInstr, SrcReg, SrcReg2, CmpValue, Instr)) {
5158 Sub = &Instr;
5159 break;
5160 }
5161
5162 if (Instr.modifiesRegister(X86::EFLAGS, TRI) ||
5163 Instr.readsRegister(X86::EFLAGS, TRI)) {
5164 // This instruction modifies or uses EFLAGS.
5165
5166 // MOV32r0 etc. are implemented with xor which clobbers condition code.
5167 // They are safe to move up, if the definition to EFLAGS is dead and
5168 // earlier instructions do not read or write EFLAGS.
5169 if (!Movr0Inst && Instr.getOpcode() == X86::MOV32r0 &&
5170 Instr.registerDefIsDead(X86::EFLAGS, TRI)) {
5171 Movr0Inst = &Instr;
5172 continue;
5173 }
5174
5175 // We can't remove CmpInstr.
5176 return false;
5177 }
5178 }
5179
5180 // Return false if no candidates exist.
5181 if (!IsCmpZero && !Sub)
5182 return false;
5183
5184 bool IsSwapped = (SrcReg2 != 0 && Sub->getOperand(1).getReg() == SrcReg2 &&
5185 Sub->getOperand(2).getReg() == SrcReg);
5186
5187 // Scan forward from the instruction after CmpInstr for uses of EFLAGS.
5188 // It is safe to remove CmpInstr if EFLAGS is redefined or killed.
5189 // If we are done with the basic block, we need to check whether EFLAGS is
5190 // live-out.
5191 bool IsSafe = false;
5192 SmallVector<std::pair<MachineInstr*, unsigned /*NewOpc*/>, 4> OpsToUpdate;
5193 MachineBasicBlock::iterator E = CmpInstr.getParent()->end();
5194 for (++I; I != E; ++I) {
5195 const MachineInstr &Instr = *I;
5196 bool ModifyEFLAGS = Instr.modifiesRegister(X86::EFLAGS, TRI);
5197 bool UseEFLAGS = Instr.readsRegister(X86::EFLAGS, TRI);
5198 // We should check the usage if this instruction uses and updates EFLAGS.
5199 if (!UseEFLAGS && ModifyEFLAGS) {
5200 // It is safe to remove CmpInstr if EFLAGS is updated again.
5201 IsSafe = true;
5202 break;
5203 }
5204 if (!UseEFLAGS && !ModifyEFLAGS)
5205 continue;
5206
5207 // EFLAGS is used by this instruction.
5208 X86::CondCode OldCC = X86::COND_INVALID;
5209 bool OpcIsSET = false;
5210 if (IsCmpZero || IsSwapped) {
5211 // We decode the condition code from opcode.
5212 if (Instr.isBranch())
5213 OldCC = getCondFromBranchOpc(Instr.getOpcode());
5214 else {
5215 OldCC = getCondFromSETOpc(Instr.getOpcode());
5216 if (OldCC != X86::COND_INVALID)
5217 OpcIsSET = true;
5218 else
5219 OldCC = X86::getCondFromCMovOpc(Instr.getOpcode());
5220 }
5221 if (OldCC == X86::COND_INVALID) return false;
5222 }
5223 if (IsCmpZero) {
5224 switch (OldCC) {
5225 default: break;
5226 case X86::COND_A: case X86::COND_AE:
5227 case X86::COND_B: case X86::COND_BE:
5228 case X86::COND_G: case X86::COND_GE:
5229 case X86::COND_L: case X86::COND_LE:
5230 case X86::COND_O: case X86::COND_NO:
5231 // CF and OF are used, we can't perform this optimization.
5232 return false;
5233 }
5234
5235 // If we're updating the condition code check if we have to reverse the
5236 // condition.
5237 if (ShouldUpdateCC)
5238 switch (OldCC) {
5239 default:
5240 return false;
5241 case X86::COND_E:
5242 break;
5243 case X86::COND_NE:
5244 NewCC = GetOppositeBranchCondition(NewCC);
5245 break;
5246 }
5247 } else if (IsSwapped) {
5248 // If we have SUB(r1, r2) and CMP(r2, r1), the condition code needs
5249 // to be changed from r2 > r1 to r1 < r2, from r2 < r1 to r1 > r2, etc.
5250 // We swap the condition code and synthesize the new opcode.
5251 NewCC = getSwappedCondition(OldCC);
5252 if (NewCC == X86::COND_INVALID) return false;
5253 }
5254
5255 if ((ShouldUpdateCC || IsSwapped) && NewCC != OldCC) {
5256 // Synthesize the new opcode.
5257 bool HasMemoryOperand = Instr.hasOneMemOperand();
5258 unsigned NewOpc;
5259 if (Instr.isBranch())
5260 NewOpc = GetCondBranchFromCond(NewCC);
5261 else if(OpcIsSET)
5262 NewOpc = getSETFromCond(NewCC, HasMemoryOperand);
5263 else {
5264 unsigned DstReg = Instr.getOperand(0).getReg();
5265 NewOpc = getCMovFromCond(NewCC, MRI->getRegClass(DstReg)->getSize(),
5266 HasMemoryOperand);
5267 }
5268
5269 // Push the MachineInstr to OpsToUpdate.
5270 // If it is safe to remove CmpInstr, the condition code of these
5271 // instructions will be modified.
5272 OpsToUpdate.push_back(std::make_pair(&*I, NewOpc));
5273 }
5274 if (ModifyEFLAGS || Instr.killsRegister(X86::EFLAGS, TRI)) {
5275 // It is safe to remove CmpInstr if EFLAGS is updated again or killed.
5276 IsSafe = true;
5277 break;
5278 }
5279 }
5280
5281 // If EFLAGS is not killed nor re-defined, we should check whether it is
5282 // live-out. If it is live-out, do not optimize.
5283 if ((IsCmpZero || IsSwapped) && !IsSafe) {
5284 MachineBasicBlock *MBB = CmpInstr.getParent();
5285 for (MachineBasicBlock *Successor : MBB->successors())
5286 if (Successor->isLiveIn(X86::EFLAGS))
5287 return false;
5288 }
5289
5290 // The instruction to be updated is either Sub or MI.
5291 Sub = IsCmpZero ? MI : Sub;
5292 // Move Movr0Inst to the appropriate place before Sub.
5293 if (Movr0Inst) {
5294 // Look backwards until we find a def that doesn't use the current EFLAGS.
5295 Def = Sub;
5296 MachineBasicBlock::reverse_iterator
5297 InsertI = MachineBasicBlock::reverse_iterator(++Def),
5298 InsertE = Sub->getParent()->rend();
5299 for (; InsertI != InsertE; ++InsertI) {
5300 MachineInstr *Instr = &*InsertI;
5301 if (!Instr->readsRegister(X86::EFLAGS, TRI) &&
5302 Instr->modifiesRegister(X86::EFLAGS, TRI)) {
5303 Sub->getParent()->remove(Movr0Inst);
5304 Instr->getParent()->insert(MachineBasicBlock::iterator(Instr),
5305 Movr0Inst);
5306 break;
5307 }
5308 }
5309 if (InsertI == InsertE)
5310 return false;
5311 }
5312
5313 // Make sure Sub instruction defines EFLAGS and mark the def live.
5314 unsigned i = 0, e = Sub->getNumOperands();
5315 for (; i != e; ++i) {
5316 MachineOperand &MO = Sub->getOperand(i);
5317 if (MO.isReg() && MO.isDef() && MO.getReg() == X86::EFLAGS) {
5318 MO.setIsDead(false);
5319 break;
5320 }
5321 }
5322 assert(i != e && "Unable to locate a def EFLAGS operand");
5323
5324 CmpInstr.eraseFromParent();
5325
5326 // Modify the condition code of instructions in OpsToUpdate.
5327 for (auto &Op : OpsToUpdate)
5328 Op.first->setDesc(get(Op.second));
5329 return true;
5330 }
5331
5332 /// Try to remove the load by folding it to a register
5333 /// operand at the use. We fold the load instructions if load defines a virtual
5334 /// register, the virtual register is used once in the same BB, and the
5335 /// instructions in-between do not load or store, and have no side effects.
optimizeLoadInstr(MachineInstr & MI,const MachineRegisterInfo * MRI,unsigned & FoldAsLoadDefReg,MachineInstr * & DefMI) const5336 MachineInstr *X86InstrInfo::optimizeLoadInstr(MachineInstr &MI,
5337 const MachineRegisterInfo *MRI,
5338 unsigned &FoldAsLoadDefReg,
5339 MachineInstr *&DefMI) const {
5340 if (FoldAsLoadDefReg == 0)
5341 return nullptr;
5342 // To be conservative, if there exists another load, clear the load candidate.
5343 if (MI.mayLoad()) {
5344 FoldAsLoadDefReg = 0;
5345 return nullptr;
5346 }
5347
5348 // Check whether we can move DefMI here.
5349 DefMI = MRI->getVRegDef(FoldAsLoadDefReg);
5350 assert(DefMI);
5351 bool SawStore = false;
5352 if (!DefMI->isSafeToMove(nullptr, SawStore))
5353 return nullptr;
5354
5355 // Collect information about virtual register operands of MI.
5356 unsigned SrcOperandId = 0;
5357 bool FoundSrcOperand = false;
5358 for (unsigned i = 0, e = MI.getDesc().getNumOperands(); i != e; ++i) {
5359 MachineOperand &MO = MI.getOperand(i);
5360 if (!MO.isReg())
5361 continue;
5362 unsigned Reg = MO.getReg();
5363 if (Reg != FoldAsLoadDefReg)
5364 continue;
5365 // Do not fold if we have a subreg use or a def or multiple uses.
5366 if (MO.getSubReg() || MO.isDef() || FoundSrcOperand)
5367 return nullptr;
5368
5369 SrcOperandId = i;
5370 FoundSrcOperand = true;
5371 }
5372 if (!FoundSrcOperand)
5373 return nullptr;
5374
5375 // Check whether we can fold the def into SrcOperandId.
5376 if (MachineInstr *FoldMI = foldMemoryOperand(MI, SrcOperandId, *DefMI)) {
5377 FoldAsLoadDefReg = 0;
5378 return FoldMI;
5379 }
5380
5381 return nullptr;
5382 }
5383
5384 /// Expand a single-def pseudo instruction to a two-addr
5385 /// instruction with two undef reads of the register being defined.
5386 /// This is used for mapping:
5387 /// %xmm4 = V_SET0
5388 /// to:
5389 /// %xmm4 = PXORrr %xmm4<undef>, %xmm4<undef>
5390 ///
Expand2AddrUndef(MachineInstrBuilder & MIB,const MCInstrDesc & Desc)5391 static bool Expand2AddrUndef(MachineInstrBuilder &MIB,
5392 const MCInstrDesc &Desc) {
5393 assert(Desc.getNumOperands() == 3 && "Expected two-addr instruction.");
5394 unsigned Reg = MIB->getOperand(0).getReg();
5395 MIB->setDesc(Desc);
5396
5397 // MachineInstr::addOperand() will insert explicit operands before any
5398 // implicit operands.
5399 MIB.addReg(Reg, RegState::Undef).addReg(Reg, RegState::Undef);
5400 // But we don't trust that.
5401 assert(MIB->getOperand(1).getReg() == Reg &&
5402 MIB->getOperand(2).getReg() == Reg && "Misplaced operand");
5403 return true;
5404 }
5405
5406 /// Expand a single-def pseudo instruction to a two-addr
5407 /// instruction with two %k0 reads.
5408 /// This is used for mapping:
5409 /// %k4 = K_SET1
5410 /// to:
5411 /// %k4 = KXNORrr %k0, %k0
Expand2AddrKreg(MachineInstrBuilder & MIB,const MCInstrDesc & Desc,unsigned Reg)5412 static bool Expand2AddrKreg(MachineInstrBuilder &MIB,
5413 const MCInstrDesc &Desc, unsigned Reg) {
5414 assert(Desc.getNumOperands() == 3 && "Expected two-addr instruction.");
5415 MIB->setDesc(Desc);
5416 MIB.addReg(Reg, RegState::Undef).addReg(Reg, RegState::Undef);
5417 return true;
5418 }
5419
expandMOV32r1(MachineInstrBuilder & MIB,const TargetInstrInfo & TII,bool MinusOne)5420 static bool expandMOV32r1(MachineInstrBuilder &MIB, const TargetInstrInfo &TII,
5421 bool MinusOne) {
5422 MachineBasicBlock &MBB = *MIB->getParent();
5423 DebugLoc DL = MIB->getDebugLoc();
5424 unsigned Reg = MIB->getOperand(0).getReg();
5425
5426 // Insert the XOR.
5427 BuildMI(MBB, MIB.getInstr(), DL, TII.get(X86::XOR32rr), Reg)
5428 .addReg(Reg, RegState::Undef)
5429 .addReg(Reg, RegState::Undef);
5430
5431 // Turn the pseudo into an INC or DEC.
5432 MIB->setDesc(TII.get(MinusOne ? X86::DEC32r : X86::INC32r));
5433 MIB.addReg(Reg);
5434
5435 return true;
5436 }
5437
ExpandMOVImmSExti8(MachineInstrBuilder & MIB) const5438 bool X86InstrInfo::ExpandMOVImmSExti8(MachineInstrBuilder &MIB) const {
5439 MachineBasicBlock &MBB = *MIB->getParent();
5440 DebugLoc DL = MIB->getDebugLoc();
5441 int64_t Imm = MIB->getOperand(1).getImm();
5442 assert(Imm != 0 && "Using push/pop for 0 is not efficient.");
5443 MachineBasicBlock::iterator I = MIB.getInstr();
5444
5445 int StackAdjustment;
5446
5447 if (Subtarget.is64Bit()) {
5448 assert(MIB->getOpcode() == X86::MOV64ImmSExti8 ||
5449 MIB->getOpcode() == X86::MOV32ImmSExti8);
5450
5451 // Can't use push/pop lowering if the function might write to the red zone.
5452 X86MachineFunctionInfo *X86FI =
5453 MBB.getParent()->getInfo<X86MachineFunctionInfo>();
5454 if (X86FI->getUsesRedZone()) {
5455 MIB->setDesc(get(MIB->getOpcode() == X86::MOV32ImmSExti8 ? X86::MOV32ri
5456 : X86::MOV64ri));
5457 return true;
5458 }
5459
5460 // 64-bit mode doesn't have 32-bit push/pop, so use 64-bit operations and
5461 // widen the register if necessary.
5462 StackAdjustment = 8;
5463 BuildMI(MBB, I, DL, get(X86::PUSH64i8)).addImm(Imm);
5464 MIB->setDesc(get(X86::POP64r));
5465 MIB->getOperand(0)
5466 .setReg(getX86SubSuperRegister(MIB->getOperand(0).getReg(), 64));
5467 } else {
5468 assert(MIB->getOpcode() == X86::MOV32ImmSExti8);
5469 StackAdjustment = 4;
5470 BuildMI(MBB, I, DL, get(X86::PUSH32i8)).addImm(Imm);
5471 MIB->setDesc(get(X86::POP32r));
5472 }
5473
5474 // Build CFI if necessary.
5475 MachineFunction &MF = *MBB.getParent();
5476 const X86FrameLowering *TFL = Subtarget.getFrameLowering();
5477 bool IsWin64Prologue = MF.getTarget().getMCAsmInfo()->usesWindowsCFI();
5478 bool NeedsDwarfCFI =
5479 !IsWin64Prologue &&
5480 (MF.getMMI().hasDebugInfo() || MF.getFunction()->needsUnwindTableEntry());
5481 bool EmitCFI = !TFL->hasFP(MF) && NeedsDwarfCFI;
5482 if (EmitCFI) {
5483 TFL->BuildCFI(MBB, I, DL,
5484 MCCFIInstruction::createAdjustCfaOffset(nullptr, StackAdjustment));
5485 TFL->BuildCFI(MBB, std::next(I), DL,
5486 MCCFIInstruction::createAdjustCfaOffset(nullptr, -StackAdjustment));
5487 }
5488
5489 return true;
5490 }
5491
5492 // LoadStackGuard has so far only been implemented for 64-bit MachO. Different
5493 // code sequence is needed for other targets.
expandLoadStackGuard(MachineInstrBuilder & MIB,const TargetInstrInfo & TII)5494 static void expandLoadStackGuard(MachineInstrBuilder &MIB,
5495 const TargetInstrInfo &TII) {
5496 MachineBasicBlock &MBB = *MIB->getParent();
5497 DebugLoc DL = MIB->getDebugLoc();
5498 unsigned Reg = MIB->getOperand(0).getReg();
5499 const GlobalValue *GV =
5500 cast<GlobalValue>((*MIB->memoperands_begin())->getValue());
5501 unsigned Flag = MachineMemOperand::MOLoad | MachineMemOperand::MOInvariant;
5502 MachineMemOperand *MMO = MBB.getParent()->getMachineMemOperand(
5503 MachinePointerInfo::getGOT(*MBB.getParent()), Flag, 8, 8);
5504 MachineBasicBlock::iterator I = MIB.getInstr();
5505
5506 BuildMI(MBB, I, DL, TII.get(X86::MOV64rm), Reg).addReg(X86::RIP).addImm(1)
5507 .addReg(0).addGlobalAddress(GV, 0, X86II::MO_GOTPCREL).addReg(0)
5508 .addMemOperand(MMO);
5509 MIB->setDebugLoc(DL);
5510 MIB->setDesc(TII.get(X86::MOV64rm));
5511 MIB.addReg(Reg, RegState::Kill).addImm(1).addReg(0).addImm(0).addReg(0);
5512 }
5513
expandPostRAPseudo(MachineInstr & MI) const5514 bool X86InstrInfo::expandPostRAPseudo(MachineInstr &MI) const {
5515 bool HasAVX = Subtarget.hasAVX();
5516 MachineInstrBuilder MIB(*MI.getParent()->getParent(), MI);
5517 switch (MI.getOpcode()) {
5518 case X86::MOV32r0:
5519 return Expand2AddrUndef(MIB, get(X86::XOR32rr));
5520 case X86::MOV32r1:
5521 return expandMOV32r1(MIB, *this, /*MinusOne=*/ false);
5522 case X86::MOV32r_1:
5523 return expandMOV32r1(MIB, *this, /*MinusOne=*/ true);
5524 case X86::MOV32ImmSExti8:
5525 case X86::MOV64ImmSExti8:
5526 return ExpandMOVImmSExti8(MIB);
5527 case X86::SETB_C8r:
5528 return Expand2AddrUndef(MIB, get(X86::SBB8rr));
5529 case X86::SETB_C16r:
5530 return Expand2AddrUndef(MIB, get(X86::SBB16rr));
5531 case X86::SETB_C32r:
5532 return Expand2AddrUndef(MIB, get(X86::SBB32rr));
5533 case X86::SETB_C64r:
5534 return Expand2AddrUndef(MIB, get(X86::SBB64rr));
5535 case X86::V_SET0:
5536 case X86::FsFLD0SS:
5537 case X86::FsFLD0SD:
5538 return Expand2AddrUndef(MIB, get(HasAVX ? X86::VXORPSrr : X86::XORPSrr));
5539 case X86::AVX_SET0:
5540 assert(HasAVX && "AVX not supported");
5541 return Expand2AddrUndef(MIB, get(X86::VXORPSYrr));
5542 case X86::AVX512_128_SET0:
5543 return Expand2AddrUndef(MIB, get(X86::VPXORDZ128rr));
5544 case X86::AVX512_256_SET0:
5545 return Expand2AddrUndef(MIB, get(X86::VPXORDZ256rr));
5546 case X86::AVX512_512_SET0:
5547 return Expand2AddrUndef(MIB, get(X86::VPXORDZrr));
5548 case X86::V_SETALLONES:
5549 return Expand2AddrUndef(MIB, get(HasAVX ? X86::VPCMPEQDrr : X86::PCMPEQDrr));
5550 case X86::AVX2_SETALLONES:
5551 return Expand2AddrUndef(MIB, get(X86::VPCMPEQDYrr));
5552 case X86::AVX512_512_SETALLONES: {
5553 unsigned Reg = MIB->getOperand(0).getReg();
5554 MIB->setDesc(get(X86::VPTERNLOGDZrri));
5555 // VPTERNLOGD needs 3 register inputs and an immediate.
5556 // 0xff will return 1s for any input.
5557 MIB.addReg(Reg, RegState::Undef).addReg(Reg, RegState::Undef)
5558 .addReg(Reg, RegState::Undef).addImm(0xff);
5559 return true;
5560 }
5561 case X86::TEST8ri_NOREX:
5562 MI.setDesc(get(X86::TEST8ri));
5563 return true;
5564 case X86::MOV32ri64:
5565 MI.setDesc(get(X86::MOV32ri));
5566 return true;
5567
5568 // KNL does not recognize dependency-breaking idioms for mask registers,
5569 // so kxnor %k1, %k1, %k2 has a RAW dependence on %k1.
5570 // Using %k0 as the undef input register is a performance heuristic based
5571 // on the assumption that %k0 is used less frequently than the other mask
5572 // registers, since it is not usable as a write mask.
5573 // FIXME: A more advanced approach would be to choose the best input mask
5574 // register based on context.
5575 case X86::KSET0B:
5576 case X86::KSET0W: return Expand2AddrKreg(MIB, get(X86::KXORWrr), X86::K0);
5577 case X86::KSET0D: return Expand2AddrKreg(MIB, get(X86::KXORDrr), X86::K0);
5578 case X86::KSET0Q: return Expand2AddrKreg(MIB, get(X86::KXORQrr), X86::K0);
5579 case X86::KSET1B:
5580 case X86::KSET1W: return Expand2AddrKreg(MIB, get(X86::KXNORWrr), X86::K0);
5581 case X86::KSET1D: return Expand2AddrKreg(MIB, get(X86::KXNORDrr), X86::K0);
5582 case X86::KSET1Q: return Expand2AddrKreg(MIB, get(X86::KXNORQrr), X86::K0);
5583 case TargetOpcode::LOAD_STACK_GUARD:
5584 expandLoadStackGuard(MIB, *this);
5585 return true;
5586 }
5587 return false;
5588 }
5589
addOperands(MachineInstrBuilder & MIB,ArrayRef<MachineOperand> MOs,int PtrOffset=0)5590 static void addOperands(MachineInstrBuilder &MIB, ArrayRef<MachineOperand> MOs,
5591 int PtrOffset = 0) {
5592 unsigned NumAddrOps = MOs.size();
5593
5594 if (NumAddrOps < 4) {
5595 // FrameIndex only - add an immediate offset (whether its zero or not).
5596 for (unsigned i = 0; i != NumAddrOps; ++i)
5597 MIB.addOperand(MOs[i]);
5598 addOffset(MIB, PtrOffset);
5599 } else {
5600 // General Memory Addressing - we need to add any offset to an existing
5601 // offset.
5602 assert(MOs.size() == 5 && "Unexpected memory operand list length");
5603 for (unsigned i = 0; i != NumAddrOps; ++i) {
5604 const MachineOperand &MO = MOs[i];
5605 if (i == 3 && PtrOffset != 0) {
5606 MIB.addDisp(MO, PtrOffset);
5607 } else {
5608 MIB.addOperand(MO);
5609 }
5610 }
5611 }
5612 }
5613
FuseTwoAddrInst(MachineFunction & MF,unsigned Opcode,ArrayRef<MachineOperand> MOs,MachineBasicBlock::iterator InsertPt,MachineInstr & MI,const TargetInstrInfo & TII)5614 static MachineInstr *FuseTwoAddrInst(MachineFunction &MF, unsigned Opcode,
5615 ArrayRef<MachineOperand> MOs,
5616 MachineBasicBlock::iterator InsertPt,
5617 MachineInstr &MI,
5618 const TargetInstrInfo &TII) {
5619 // Create the base instruction with the memory operand as the first part.
5620 // Omit the implicit operands, something BuildMI can't do.
5621 MachineInstr *NewMI =
5622 MF.CreateMachineInstr(TII.get(Opcode), MI.getDebugLoc(), true);
5623 MachineInstrBuilder MIB(MF, NewMI);
5624 addOperands(MIB, MOs);
5625
5626 // Loop over the rest of the ri operands, converting them over.
5627 unsigned NumOps = MI.getDesc().getNumOperands() - 2;
5628 for (unsigned i = 0; i != NumOps; ++i) {
5629 MachineOperand &MO = MI.getOperand(i + 2);
5630 MIB.addOperand(MO);
5631 }
5632 for (unsigned i = NumOps + 2, e = MI.getNumOperands(); i != e; ++i) {
5633 MachineOperand &MO = MI.getOperand(i);
5634 MIB.addOperand(MO);
5635 }
5636
5637 MachineBasicBlock *MBB = InsertPt->getParent();
5638 MBB->insert(InsertPt, NewMI);
5639
5640 return MIB;
5641 }
5642
FuseInst(MachineFunction & MF,unsigned Opcode,unsigned OpNo,ArrayRef<MachineOperand> MOs,MachineBasicBlock::iterator InsertPt,MachineInstr & MI,const TargetInstrInfo & TII,int PtrOffset=0)5643 static MachineInstr *FuseInst(MachineFunction &MF, unsigned Opcode,
5644 unsigned OpNo, ArrayRef<MachineOperand> MOs,
5645 MachineBasicBlock::iterator InsertPt,
5646 MachineInstr &MI, const TargetInstrInfo &TII,
5647 int PtrOffset = 0) {
5648 // Omit the implicit operands, something BuildMI can't do.
5649 MachineInstr *NewMI =
5650 MF.CreateMachineInstr(TII.get(Opcode), MI.getDebugLoc(), true);
5651 MachineInstrBuilder MIB(MF, NewMI);
5652
5653 for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) {
5654 MachineOperand &MO = MI.getOperand(i);
5655 if (i == OpNo) {
5656 assert(MO.isReg() && "Expected to fold into reg operand!");
5657 addOperands(MIB, MOs, PtrOffset);
5658 } else {
5659 MIB.addOperand(MO);
5660 }
5661 }
5662
5663 MachineBasicBlock *MBB = InsertPt->getParent();
5664 MBB->insert(InsertPt, NewMI);
5665
5666 return MIB;
5667 }
5668
MakeM0Inst(const TargetInstrInfo & TII,unsigned Opcode,ArrayRef<MachineOperand> MOs,MachineBasicBlock::iterator InsertPt,MachineInstr & MI)5669 static MachineInstr *MakeM0Inst(const TargetInstrInfo &TII, unsigned Opcode,
5670 ArrayRef<MachineOperand> MOs,
5671 MachineBasicBlock::iterator InsertPt,
5672 MachineInstr &MI) {
5673 MachineInstrBuilder MIB = BuildMI(*InsertPt->getParent(), InsertPt,
5674 MI.getDebugLoc(), TII.get(Opcode));
5675 addOperands(MIB, MOs);
5676 return MIB.addImm(0);
5677 }
5678
foldMemoryOperandCustom(MachineFunction & MF,MachineInstr & MI,unsigned OpNum,ArrayRef<MachineOperand> MOs,MachineBasicBlock::iterator InsertPt,unsigned Size,unsigned Align) const5679 MachineInstr *X86InstrInfo::foldMemoryOperandCustom(
5680 MachineFunction &MF, MachineInstr &MI, unsigned OpNum,
5681 ArrayRef<MachineOperand> MOs, MachineBasicBlock::iterator InsertPt,
5682 unsigned Size, unsigned Align) const {
5683 switch (MI.getOpcode()) {
5684 case X86::INSERTPSrr:
5685 case X86::VINSERTPSrr:
5686 // Attempt to convert the load of inserted vector into a fold load
5687 // of a single float.
5688 if (OpNum == 2) {
5689 unsigned Imm = MI.getOperand(MI.getNumOperands() - 1).getImm();
5690 unsigned ZMask = Imm & 15;
5691 unsigned DstIdx = (Imm >> 4) & 3;
5692 unsigned SrcIdx = (Imm >> 6) & 3;
5693
5694 unsigned RCSize = getRegClass(MI.getDesc(), OpNum, &RI, MF)->getSize();
5695 if (Size <= RCSize && 4 <= Align) {
5696 int PtrOffset = SrcIdx * 4;
5697 unsigned NewImm = (DstIdx << 4) | ZMask;
5698 unsigned NewOpCode =
5699 (MI.getOpcode() == X86::VINSERTPSrr ? X86::VINSERTPSrm
5700 : X86::INSERTPSrm);
5701 MachineInstr *NewMI =
5702 FuseInst(MF, NewOpCode, OpNum, MOs, InsertPt, MI, *this, PtrOffset);
5703 NewMI->getOperand(NewMI->getNumOperands() - 1).setImm(NewImm);
5704 return NewMI;
5705 }
5706 }
5707 break;
5708 case X86::MOVHLPSrr:
5709 case X86::VMOVHLPSrr:
5710 // Move the upper 64-bits of the second operand to the lower 64-bits.
5711 // To fold the load, adjust the pointer to the upper and use (V)MOVLPS.
5712 // TODO: In most cases AVX doesn't have a 8-byte alignment requirement.
5713 if (OpNum == 2) {
5714 unsigned RCSize = getRegClass(MI.getDesc(), OpNum, &RI, MF)->getSize();
5715 if (Size <= RCSize && 8 <= Align) {
5716 unsigned NewOpCode =
5717 (MI.getOpcode() == X86::VMOVHLPSrr ? X86::VMOVLPSrm
5718 : X86::MOVLPSrm);
5719 MachineInstr *NewMI =
5720 FuseInst(MF, NewOpCode, OpNum, MOs, InsertPt, MI, *this, 8);
5721 return NewMI;
5722 }
5723 }
5724 break;
5725 };
5726
5727 return nullptr;
5728 }
5729
foldMemoryOperandImpl(MachineFunction & MF,MachineInstr & MI,unsigned OpNum,ArrayRef<MachineOperand> MOs,MachineBasicBlock::iterator InsertPt,unsigned Size,unsigned Align,bool AllowCommute) const5730 MachineInstr *X86InstrInfo::foldMemoryOperandImpl(
5731 MachineFunction &MF, MachineInstr &MI, unsigned OpNum,
5732 ArrayRef<MachineOperand> MOs, MachineBasicBlock::iterator InsertPt,
5733 unsigned Size, unsigned Align, bool AllowCommute) const {
5734 const DenseMap<unsigned,
5735 std::pair<uint16_t, uint16_t> > *OpcodeTablePtr = nullptr;
5736 bool isCallRegIndirect = Subtarget.callRegIndirect();
5737 bool isTwoAddrFold = false;
5738
5739 // For CPUs that favor the register form of a call or push,
5740 // do not fold loads into calls or pushes, unless optimizing for size
5741 // aggressively.
5742 if (isCallRegIndirect && !MF.getFunction()->optForMinSize() &&
5743 (MI.getOpcode() == X86::CALL32r || MI.getOpcode() == X86::CALL64r ||
5744 MI.getOpcode() == X86::PUSH16r || MI.getOpcode() == X86::PUSH32r ||
5745 MI.getOpcode() == X86::PUSH64r))
5746 return nullptr;
5747
5748 unsigned NumOps = MI.getDesc().getNumOperands();
5749 bool isTwoAddr =
5750 NumOps > 1 && MI.getDesc().getOperandConstraint(1, MCOI::TIED_TO) != -1;
5751
5752 // FIXME: AsmPrinter doesn't know how to handle
5753 // X86II::MO_GOT_ABSOLUTE_ADDRESS after folding.
5754 if (MI.getOpcode() == X86::ADD32ri &&
5755 MI.getOperand(2).getTargetFlags() == X86II::MO_GOT_ABSOLUTE_ADDRESS)
5756 return nullptr;
5757
5758 MachineInstr *NewMI = nullptr;
5759
5760 // Attempt to fold any custom cases we have.
5761 if (MachineInstr *CustomMI =
5762 foldMemoryOperandCustom(MF, MI, OpNum, MOs, InsertPt, Size, Align))
5763 return CustomMI;
5764
5765 // Folding a memory location into the two-address part of a two-address
5766 // instruction is different than folding it other places. It requires
5767 // replacing the *two* registers with the memory location.
5768 if (isTwoAddr && NumOps >= 2 && OpNum < 2 && MI.getOperand(0).isReg() &&
5769 MI.getOperand(1).isReg() &&
5770 MI.getOperand(0).getReg() == MI.getOperand(1).getReg()) {
5771 OpcodeTablePtr = &RegOp2MemOpTable2Addr;
5772 isTwoAddrFold = true;
5773 } else if (OpNum == 0) {
5774 if (MI.getOpcode() == X86::MOV32r0) {
5775 NewMI = MakeM0Inst(*this, X86::MOV32mi, MOs, InsertPt, MI);
5776 if (NewMI)
5777 return NewMI;
5778 }
5779
5780 OpcodeTablePtr = &RegOp2MemOpTable0;
5781 } else if (OpNum == 1) {
5782 OpcodeTablePtr = &RegOp2MemOpTable1;
5783 } else if (OpNum == 2) {
5784 OpcodeTablePtr = &RegOp2MemOpTable2;
5785 } else if (OpNum == 3) {
5786 OpcodeTablePtr = &RegOp2MemOpTable3;
5787 } else if (OpNum == 4) {
5788 OpcodeTablePtr = &RegOp2MemOpTable4;
5789 }
5790
5791 // If table selected...
5792 if (OpcodeTablePtr) {
5793 // Find the Opcode to fuse
5794 auto I = OpcodeTablePtr->find(MI.getOpcode());
5795 if (I != OpcodeTablePtr->end()) {
5796 unsigned Opcode = I->second.first;
5797 unsigned MinAlign = (I->second.second & TB_ALIGN_MASK) >> TB_ALIGN_SHIFT;
5798 if (Align < MinAlign)
5799 return nullptr;
5800 bool NarrowToMOV32rm = false;
5801 if (Size) {
5802 unsigned RCSize = getRegClass(MI.getDesc(), OpNum, &RI, MF)->getSize();
5803 if (Size < RCSize) {
5804 // Check if it's safe to fold the load. If the size of the object is
5805 // narrower than the load width, then it's not.
5806 if (Opcode != X86::MOV64rm || RCSize != 8 || Size != 4)
5807 return nullptr;
5808 // If this is a 64-bit load, but the spill slot is 32, then we can do
5809 // a 32-bit load which is implicitly zero-extended. This likely is
5810 // due to live interval analysis remat'ing a load from stack slot.
5811 if (MI.getOperand(0).getSubReg() || MI.getOperand(1).getSubReg())
5812 return nullptr;
5813 Opcode = X86::MOV32rm;
5814 NarrowToMOV32rm = true;
5815 }
5816 }
5817
5818 if (isTwoAddrFold)
5819 NewMI = FuseTwoAddrInst(MF, Opcode, MOs, InsertPt, MI, *this);
5820 else
5821 NewMI = FuseInst(MF, Opcode, OpNum, MOs, InsertPt, MI, *this);
5822
5823 if (NarrowToMOV32rm) {
5824 // If this is the special case where we use a MOV32rm to load a 32-bit
5825 // value and zero-extend the top bits. Change the destination register
5826 // to a 32-bit one.
5827 unsigned DstReg = NewMI->getOperand(0).getReg();
5828 if (TargetRegisterInfo::isPhysicalRegister(DstReg))
5829 NewMI->getOperand(0).setReg(RI.getSubReg(DstReg, X86::sub_32bit));
5830 else
5831 NewMI->getOperand(0).setSubReg(X86::sub_32bit);
5832 }
5833 return NewMI;
5834 }
5835 }
5836
5837 // If the instruction and target operand are commutable, commute the
5838 // instruction and try again.
5839 if (AllowCommute) {
5840 unsigned CommuteOpIdx1 = OpNum, CommuteOpIdx2 = CommuteAnyOperandIndex;
5841 if (findCommutedOpIndices(MI, CommuteOpIdx1, CommuteOpIdx2)) {
5842 bool HasDef = MI.getDesc().getNumDefs();
5843 unsigned Reg0 = HasDef ? MI.getOperand(0).getReg() : 0;
5844 unsigned Reg1 = MI.getOperand(CommuteOpIdx1).getReg();
5845 unsigned Reg2 = MI.getOperand(CommuteOpIdx2).getReg();
5846 bool Tied1 =
5847 0 == MI.getDesc().getOperandConstraint(CommuteOpIdx1, MCOI::TIED_TO);
5848 bool Tied2 =
5849 0 == MI.getDesc().getOperandConstraint(CommuteOpIdx2, MCOI::TIED_TO);
5850
5851 // If either of the commutable operands are tied to the destination
5852 // then we can not commute + fold.
5853 if ((HasDef && Reg0 == Reg1 && Tied1) ||
5854 (HasDef && Reg0 == Reg2 && Tied2))
5855 return nullptr;
5856
5857 MachineInstr *CommutedMI =
5858 commuteInstruction(MI, false, CommuteOpIdx1, CommuteOpIdx2);
5859 if (!CommutedMI) {
5860 // Unable to commute.
5861 return nullptr;
5862 }
5863 if (CommutedMI != &MI) {
5864 // New instruction. We can't fold from this.
5865 CommutedMI->eraseFromParent();
5866 return nullptr;
5867 }
5868
5869 // Attempt to fold with the commuted version of the instruction.
5870 NewMI = foldMemoryOperandImpl(MF, MI, CommuteOpIdx2, MOs, InsertPt,
5871 Size, Align, /*AllowCommute=*/false);
5872 if (NewMI)
5873 return NewMI;
5874
5875 // Folding failed again - undo the commute before returning.
5876 MachineInstr *UncommutedMI =
5877 commuteInstruction(MI, false, CommuteOpIdx1, CommuteOpIdx2);
5878 if (!UncommutedMI) {
5879 // Unable to commute.
5880 return nullptr;
5881 }
5882 if (UncommutedMI != &MI) {
5883 // New instruction. It doesn't need to be kept.
5884 UncommutedMI->eraseFromParent();
5885 return nullptr;
5886 }
5887
5888 // Return here to prevent duplicate fuse failure report.
5889 return nullptr;
5890 }
5891 }
5892
5893 // No fusion
5894 if (PrintFailedFusing && !MI.isCopy())
5895 dbgs() << "We failed to fuse operand " << OpNum << " in " << MI;
5896 return nullptr;
5897 }
5898
5899 /// Return true for all instructions that only update
5900 /// the first 32 or 64-bits of the destination register and leave the rest
5901 /// unmodified. This can be used to avoid folding loads if the instructions
5902 /// only update part of the destination register, and the non-updated part is
5903 /// not needed. e.g. cvtss2sd, sqrtss. Unfolding the load from these
5904 /// instructions breaks the partial register dependency and it can improve
5905 /// performance. e.g.:
5906 ///
5907 /// movss (%rdi), %xmm0
5908 /// cvtss2sd %xmm0, %xmm0
5909 ///
5910 /// Instead of
5911 /// cvtss2sd (%rdi), %xmm0
5912 ///
5913 /// FIXME: This should be turned into a TSFlags.
5914 ///
hasPartialRegUpdate(unsigned Opcode)5915 static bool hasPartialRegUpdate(unsigned Opcode) {
5916 switch (Opcode) {
5917 case X86::CVTSI2SSrr:
5918 case X86::CVTSI2SSrm:
5919 case X86::CVTSI2SS64rr:
5920 case X86::CVTSI2SS64rm:
5921 case X86::CVTSI2SDrr:
5922 case X86::CVTSI2SDrm:
5923 case X86::CVTSI2SD64rr:
5924 case X86::CVTSI2SD64rm:
5925 case X86::CVTSD2SSrr:
5926 case X86::CVTSD2SSrm:
5927 case X86::Int_CVTSD2SSrr:
5928 case X86::Int_CVTSD2SSrm:
5929 case X86::CVTSS2SDrr:
5930 case X86::CVTSS2SDrm:
5931 case X86::Int_CVTSS2SDrr:
5932 case X86::Int_CVTSS2SDrm:
5933 case X86::MOVHPDrm:
5934 case X86::MOVHPSrm:
5935 case X86::MOVLPDrm:
5936 case X86::MOVLPSrm:
5937 case X86::RCPSSr:
5938 case X86::RCPSSm:
5939 case X86::RCPSSr_Int:
5940 case X86::RCPSSm_Int:
5941 case X86::ROUNDSDr:
5942 case X86::ROUNDSDm:
5943 case X86::ROUNDSDr_Int:
5944 case X86::ROUNDSSr:
5945 case X86::ROUNDSSm:
5946 case X86::ROUNDSSr_Int:
5947 case X86::RSQRTSSr:
5948 case X86::RSQRTSSm:
5949 case X86::RSQRTSSr_Int:
5950 case X86::RSQRTSSm_Int:
5951 case X86::SQRTSSr:
5952 case X86::SQRTSSm:
5953 case X86::SQRTSSr_Int:
5954 case X86::SQRTSSm_Int:
5955 case X86::SQRTSDr:
5956 case X86::SQRTSDm:
5957 case X86::SQRTSDr_Int:
5958 case X86::SQRTSDm_Int:
5959 return true;
5960 }
5961
5962 return false;
5963 }
5964
5965 /// Inform the ExeDepsFix pass how many idle
5966 /// instructions we would like before a partial register update.
getPartialRegUpdateClearance(const MachineInstr & MI,unsigned OpNum,const TargetRegisterInfo * TRI) const5967 unsigned X86InstrInfo::getPartialRegUpdateClearance(
5968 const MachineInstr &MI, unsigned OpNum,
5969 const TargetRegisterInfo *TRI) const {
5970 if (OpNum != 0 || !hasPartialRegUpdate(MI.getOpcode()))
5971 return 0;
5972
5973 // If MI is marked as reading Reg, the partial register update is wanted.
5974 const MachineOperand &MO = MI.getOperand(0);
5975 unsigned Reg = MO.getReg();
5976 if (TargetRegisterInfo::isVirtualRegister(Reg)) {
5977 if (MO.readsReg() || MI.readsVirtualRegister(Reg))
5978 return 0;
5979 } else {
5980 if (MI.readsRegister(Reg, TRI))
5981 return 0;
5982 }
5983
5984 // If any instructions in the clearance range are reading Reg, insert a
5985 // dependency breaking instruction, which is inexpensive and is likely to
5986 // be hidden in other instruction's cycles.
5987 return PartialRegUpdateClearance;
5988 }
5989
5990 // Return true for any instruction the copies the high bits of the first source
5991 // operand into the unused high bits of the destination operand.
hasUndefRegUpdate(unsigned Opcode)5992 static bool hasUndefRegUpdate(unsigned Opcode) {
5993 switch (Opcode) {
5994 case X86::VCVTSI2SSrr:
5995 case X86::VCVTSI2SSrm:
5996 case X86::Int_VCVTSI2SSrr:
5997 case X86::Int_VCVTSI2SSrm:
5998 case X86::VCVTSI2SS64rr:
5999 case X86::VCVTSI2SS64rm:
6000 case X86::Int_VCVTSI2SS64rr:
6001 case X86::Int_VCVTSI2SS64rm:
6002 case X86::VCVTSI2SDrr:
6003 case X86::VCVTSI2SDrm:
6004 case X86::Int_VCVTSI2SDrr:
6005 case X86::Int_VCVTSI2SDrm:
6006 case X86::VCVTSI2SD64rr:
6007 case X86::VCVTSI2SD64rm:
6008 case X86::Int_VCVTSI2SD64rr:
6009 case X86::Int_VCVTSI2SD64rm:
6010 case X86::VCVTSD2SSrr:
6011 case X86::VCVTSD2SSrm:
6012 case X86::Int_VCVTSD2SSrr:
6013 case X86::Int_VCVTSD2SSrm:
6014 case X86::VCVTSS2SDrr:
6015 case X86::VCVTSS2SDrm:
6016 case X86::Int_VCVTSS2SDrr:
6017 case X86::Int_VCVTSS2SDrm:
6018 case X86::VRCPSSr:
6019 case X86::VRCPSSm:
6020 case X86::VRCPSSm_Int:
6021 case X86::VROUNDSDr:
6022 case X86::VROUNDSDm:
6023 case X86::VROUNDSDr_Int:
6024 case X86::VROUNDSSr:
6025 case X86::VROUNDSSm:
6026 case X86::VROUNDSSr_Int:
6027 case X86::VRSQRTSSr:
6028 case X86::VRSQRTSSm:
6029 case X86::VRSQRTSSm_Int:
6030 case X86::VSQRTSSr:
6031 case X86::VSQRTSSm:
6032 case X86::VSQRTSSm_Int:
6033 case X86::VSQRTSDr:
6034 case X86::VSQRTSDm:
6035 case X86::VSQRTSDm_Int:
6036 // AVX-512
6037 case X86::VCVTSD2SSZrr:
6038 case X86::VCVTSD2SSZrm:
6039 case X86::VCVTSS2SDZrr:
6040 case X86::VCVTSS2SDZrm:
6041 return true;
6042 }
6043
6044 return false;
6045 }
6046
6047 /// Inform the ExeDepsFix pass how many idle instructions we would like before
6048 /// certain undef register reads.
6049 ///
6050 /// This catches the VCVTSI2SD family of instructions:
6051 ///
6052 /// vcvtsi2sdq %rax, %xmm0<undef>, %xmm14
6053 ///
6054 /// We should to be careful *not* to catch VXOR idioms which are presumably
6055 /// handled specially in the pipeline:
6056 ///
6057 /// vxorps %xmm1<undef>, %xmm1<undef>, %xmm1
6058 ///
6059 /// Like getPartialRegUpdateClearance, this makes a strong assumption that the
6060 /// high bits that are passed-through are not live.
6061 unsigned
getUndefRegClearance(const MachineInstr & MI,unsigned & OpNum,const TargetRegisterInfo * TRI) const6062 X86InstrInfo::getUndefRegClearance(const MachineInstr &MI, unsigned &OpNum,
6063 const TargetRegisterInfo *TRI) const {
6064 if (!hasUndefRegUpdate(MI.getOpcode()))
6065 return 0;
6066
6067 // Set the OpNum parameter to the first source operand.
6068 OpNum = 1;
6069
6070 const MachineOperand &MO = MI.getOperand(OpNum);
6071 if (MO.isUndef() && TargetRegisterInfo::isPhysicalRegister(MO.getReg())) {
6072 return UndefRegClearance;
6073 }
6074 return 0;
6075 }
6076
breakPartialRegDependency(MachineInstr & MI,unsigned OpNum,const TargetRegisterInfo * TRI) const6077 void X86InstrInfo::breakPartialRegDependency(
6078 MachineInstr &MI, unsigned OpNum, const TargetRegisterInfo *TRI) const {
6079 unsigned Reg = MI.getOperand(OpNum).getReg();
6080 // If MI kills this register, the false dependence is already broken.
6081 if (MI.killsRegister(Reg, TRI))
6082 return;
6083
6084 if (X86::VR128RegClass.contains(Reg)) {
6085 // These instructions are all floating point domain, so xorps is the best
6086 // choice.
6087 unsigned Opc = Subtarget.hasAVX() ? X86::VXORPSrr : X86::XORPSrr;
6088 BuildMI(*MI.getParent(), MI, MI.getDebugLoc(), get(Opc), Reg)
6089 .addReg(Reg, RegState::Undef)
6090 .addReg(Reg, RegState::Undef);
6091 MI.addRegisterKilled(Reg, TRI, true);
6092 } else if (X86::VR256RegClass.contains(Reg)) {
6093 // Use vxorps to clear the full ymm register.
6094 // It wants to read and write the xmm sub-register.
6095 unsigned XReg = TRI->getSubReg(Reg, X86::sub_xmm);
6096 BuildMI(*MI.getParent(), MI, MI.getDebugLoc(), get(X86::VXORPSrr), XReg)
6097 .addReg(XReg, RegState::Undef)
6098 .addReg(XReg, RegState::Undef)
6099 .addReg(Reg, RegState::ImplicitDefine);
6100 MI.addRegisterKilled(Reg, TRI, true);
6101 }
6102 }
6103
6104 MachineInstr *
foldMemoryOperandImpl(MachineFunction & MF,MachineInstr & MI,ArrayRef<unsigned> Ops,MachineBasicBlock::iterator InsertPt,int FrameIndex,LiveIntervals * LIS) const6105 X86InstrInfo::foldMemoryOperandImpl(MachineFunction &MF, MachineInstr &MI,
6106 ArrayRef<unsigned> Ops,
6107 MachineBasicBlock::iterator InsertPt,
6108 int FrameIndex, LiveIntervals *LIS) const {
6109 // Check switch flag
6110 if (NoFusing)
6111 return nullptr;
6112
6113 // Unless optimizing for size, don't fold to avoid partial
6114 // register update stalls
6115 if (!MF.getFunction()->optForSize() && hasPartialRegUpdate(MI.getOpcode()))
6116 return nullptr;
6117
6118 const MachineFrameInfo *MFI = MF.getFrameInfo();
6119 unsigned Size = MFI->getObjectSize(FrameIndex);
6120 unsigned Alignment = MFI->getObjectAlignment(FrameIndex);
6121 // If the function stack isn't realigned we don't want to fold instructions
6122 // that need increased alignment.
6123 if (!RI.needsStackRealignment(MF))
6124 Alignment =
6125 std::min(Alignment, Subtarget.getFrameLowering()->getStackAlignment());
6126 if (Ops.size() == 2 && Ops[0] == 0 && Ops[1] == 1) {
6127 unsigned NewOpc = 0;
6128 unsigned RCSize = 0;
6129 switch (MI.getOpcode()) {
6130 default: return nullptr;
6131 case X86::TEST8rr: NewOpc = X86::CMP8ri; RCSize = 1; break;
6132 case X86::TEST16rr: NewOpc = X86::CMP16ri8; RCSize = 2; break;
6133 case X86::TEST32rr: NewOpc = X86::CMP32ri8; RCSize = 4; break;
6134 case X86::TEST64rr: NewOpc = X86::CMP64ri8; RCSize = 8; break;
6135 }
6136 // Check if it's safe to fold the load. If the size of the object is
6137 // narrower than the load width, then it's not.
6138 if (Size < RCSize)
6139 return nullptr;
6140 // Change to CMPXXri r, 0 first.
6141 MI.setDesc(get(NewOpc));
6142 MI.getOperand(1).ChangeToImmediate(0);
6143 } else if (Ops.size() != 1)
6144 return nullptr;
6145
6146 return foldMemoryOperandImpl(MF, MI, Ops[0],
6147 MachineOperand::CreateFI(FrameIndex), InsertPt,
6148 Size, Alignment, /*AllowCommute=*/true);
6149 }
6150
6151 /// Check if \p LoadMI is a partial register load that we can't fold into \p MI
6152 /// because the latter uses contents that wouldn't be defined in the folded
6153 /// version. For instance, this transformation isn't legal:
6154 /// movss (%rdi), %xmm0
6155 /// addps %xmm0, %xmm0
6156 /// ->
6157 /// addps (%rdi), %xmm0
6158 ///
6159 /// But this one is:
6160 /// movss (%rdi), %xmm0
6161 /// addss %xmm0, %xmm0
6162 /// ->
6163 /// addss (%rdi), %xmm0
6164 ///
isNonFoldablePartialRegisterLoad(const MachineInstr & LoadMI,const MachineInstr & UserMI,const MachineFunction & MF)6165 static bool isNonFoldablePartialRegisterLoad(const MachineInstr &LoadMI,
6166 const MachineInstr &UserMI,
6167 const MachineFunction &MF) {
6168 unsigned Opc = LoadMI.getOpcode();
6169 unsigned UserOpc = UserMI.getOpcode();
6170 unsigned RegSize =
6171 MF.getRegInfo().getRegClass(LoadMI.getOperand(0).getReg())->getSize();
6172
6173 if ((Opc == X86::MOVSSrm || Opc == X86::VMOVSSrm) && RegSize > 4) {
6174 // These instructions only load 32 bits, we can't fold them if the
6175 // destination register is wider than 32 bits (4 bytes), and its user
6176 // instruction isn't scalar (SS).
6177 switch (UserOpc) {
6178 case X86::ADDSSrr_Int: case X86::VADDSSrr_Int:
6179 case X86::DIVSSrr_Int: case X86::VDIVSSrr_Int:
6180 case X86::MULSSrr_Int: case X86::VMULSSrr_Int:
6181 case X86::SUBSSrr_Int: case X86::VSUBSSrr_Int:
6182 case X86::VFMADDSSr132r_Int: case X86::VFNMADDSSr132r_Int:
6183 case X86::VFMADDSSr213r_Int: case X86::VFNMADDSSr213r_Int:
6184 case X86::VFMADDSSr231r_Int: case X86::VFNMADDSSr231r_Int:
6185 case X86::VFMSUBSSr132r_Int: case X86::VFNMSUBSSr132r_Int:
6186 case X86::VFMSUBSSr213r_Int: case X86::VFNMSUBSSr213r_Int:
6187 case X86::VFMSUBSSr231r_Int: case X86::VFNMSUBSSr231r_Int:
6188 return false;
6189 default:
6190 return true;
6191 }
6192 }
6193
6194 if ((Opc == X86::MOVSDrm || Opc == X86::VMOVSDrm) && RegSize > 8) {
6195 // These instructions only load 64 bits, we can't fold them if the
6196 // destination register is wider than 64 bits (8 bytes), and its user
6197 // instruction isn't scalar (SD).
6198 switch (UserOpc) {
6199 case X86::ADDSDrr_Int: case X86::VADDSDrr_Int:
6200 case X86::DIVSDrr_Int: case X86::VDIVSDrr_Int:
6201 case X86::MULSDrr_Int: case X86::VMULSDrr_Int:
6202 case X86::SUBSDrr_Int: case X86::VSUBSDrr_Int:
6203 case X86::VFMADDSDr132r_Int: case X86::VFNMADDSDr132r_Int:
6204 case X86::VFMADDSDr213r_Int: case X86::VFNMADDSDr213r_Int:
6205 case X86::VFMADDSDr231r_Int: case X86::VFNMADDSDr231r_Int:
6206 case X86::VFMSUBSDr132r_Int: case X86::VFNMSUBSDr132r_Int:
6207 case X86::VFMSUBSDr213r_Int: case X86::VFNMSUBSDr213r_Int:
6208 case X86::VFMSUBSDr231r_Int: case X86::VFNMSUBSDr231r_Int:
6209 return false;
6210 default:
6211 return true;
6212 }
6213 }
6214
6215 return false;
6216 }
6217
foldMemoryOperandImpl(MachineFunction & MF,MachineInstr & MI,ArrayRef<unsigned> Ops,MachineBasicBlock::iterator InsertPt,MachineInstr & LoadMI,LiveIntervals * LIS) const6218 MachineInstr *X86InstrInfo::foldMemoryOperandImpl(
6219 MachineFunction &MF, MachineInstr &MI, ArrayRef<unsigned> Ops,
6220 MachineBasicBlock::iterator InsertPt, MachineInstr &LoadMI,
6221 LiveIntervals *LIS) const {
6222 // If loading from a FrameIndex, fold directly from the FrameIndex.
6223 unsigned NumOps = LoadMI.getDesc().getNumOperands();
6224 int FrameIndex;
6225 if (isLoadFromStackSlot(LoadMI, FrameIndex)) {
6226 if (isNonFoldablePartialRegisterLoad(LoadMI, MI, MF))
6227 return nullptr;
6228 return foldMemoryOperandImpl(MF, MI, Ops, InsertPt, FrameIndex, LIS);
6229 }
6230
6231 // Check switch flag
6232 if (NoFusing) return nullptr;
6233
6234 // Avoid partial register update stalls unless optimizing for size.
6235 if (!MF.getFunction()->optForSize() && hasPartialRegUpdate(MI.getOpcode()))
6236 return nullptr;
6237
6238 // Determine the alignment of the load.
6239 unsigned Alignment = 0;
6240 if (LoadMI.hasOneMemOperand())
6241 Alignment = (*LoadMI.memoperands_begin())->getAlignment();
6242 else
6243 switch (LoadMI.getOpcode()) {
6244 case X86::AVX512_512_SET0:
6245 case X86::AVX512_512_SETALLONES:
6246 Alignment = 64;
6247 break;
6248 case X86::AVX2_SETALLONES:
6249 case X86::AVX_SET0:
6250 case X86::AVX512_256_SET0:
6251 Alignment = 32;
6252 break;
6253 case X86::V_SET0:
6254 case X86::V_SETALLONES:
6255 case X86::AVX512_128_SET0:
6256 Alignment = 16;
6257 break;
6258 case X86::FsFLD0SD:
6259 Alignment = 8;
6260 break;
6261 case X86::FsFLD0SS:
6262 Alignment = 4;
6263 break;
6264 default:
6265 return nullptr;
6266 }
6267 if (Ops.size() == 2 && Ops[0] == 0 && Ops[1] == 1) {
6268 unsigned NewOpc = 0;
6269 switch (MI.getOpcode()) {
6270 default: return nullptr;
6271 case X86::TEST8rr: NewOpc = X86::CMP8ri; break;
6272 case X86::TEST16rr: NewOpc = X86::CMP16ri8; break;
6273 case X86::TEST32rr: NewOpc = X86::CMP32ri8; break;
6274 case X86::TEST64rr: NewOpc = X86::CMP64ri8; break;
6275 }
6276 // Change to CMPXXri r, 0 first.
6277 MI.setDesc(get(NewOpc));
6278 MI.getOperand(1).ChangeToImmediate(0);
6279 } else if (Ops.size() != 1)
6280 return nullptr;
6281
6282 // Make sure the subregisters match.
6283 // Otherwise we risk changing the size of the load.
6284 if (LoadMI.getOperand(0).getSubReg() != MI.getOperand(Ops[0]).getSubReg())
6285 return nullptr;
6286
6287 SmallVector<MachineOperand,X86::AddrNumOperands> MOs;
6288 switch (LoadMI.getOpcode()) {
6289 case X86::V_SET0:
6290 case X86::V_SETALLONES:
6291 case X86::AVX2_SETALLONES:
6292 case X86::AVX_SET0:
6293 case X86::AVX512_128_SET0:
6294 case X86::AVX512_256_SET0:
6295 case X86::AVX512_512_SET0:
6296 case X86::AVX512_512_SETALLONES:
6297 case X86::FsFLD0SD:
6298 case X86::FsFLD0SS: {
6299 // Folding a V_SET0 or V_SETALLONES as a load, to ease register pressure.
6300 // Create a constant-pool entry and operands to load from it.
6301
6302 // Medium and large mode can't fold loads this way.
6303 if (MF.getTarget().getCodeModel() != CodeModel::Small &&
6304 MF.getTarget().getCodeModel() != CodeModel::Kernel)
6305 return nullptr;
6306
6307 // x86-32 PIC requires a PIC base register for constant pools.
6308 unsigned PICBase = 0;
6309 if (MF.getTarget().isPositionIndependent()) {
6310 if (Subtarget.is64Bit())
6311 PICBase = X86::RIP;
6312 else
6313 // FIXME: PICBase = getGlobalBaseReg(&MF);
6314 // This doesn't work for several reasons.
6315 // 1. GlobalBaseReg may have been spilled.
6316 // 2. It may not be live at MI.
6317 return nullptr;
6318 }
6319
6320 // Create a constant-pool entry.
6321 MachineConstantPool &MCP = *MF.getConstantPool();
6322 Type *Ty;
6323 unsigned Opc = LoadMI.getOpcode();
6324 if (Opc == X86::FsFLD0SS)
6325 Ty = Type::getFloatTy(MF.getFunction()->getContext());
6326 else if (Opc == X86::FsFLD0SD)
6327 Ty = Type::getDoubleTy(MF.getFunction()->getContext());
6328 else if (Opc == X86::AVX512_512_SET0 || Opc == X86::AVX512_512_SETALLONES)
6329 Ty = VectorType::get(Type::getInt32Ty(MF.getFunction()->getContext()),16);
6330 else if (Opc == X86::AVX2_SETALLONES || Opc == X86::AVX_SET0 ||
6331 Opc == X86::AVX512_256_SET0)
6332 Ty = VectorType::get(Type::getInt32Ty(MF.getFunction()->getContext()), 8);
6333 else
6334 Ty = VectorType::get(Type::getInt32Ty(MF.getFunction()->getContext()), 4);
6335
6336 bool IsAllOnes = (Opc == X86::V_SETALLONES || Opc == X86::AVX2_SETALLONES ||
6337 Opc == X86::AVX512_512_SETALLONES);
6338 const Constant *C = IsAllOnes ? Constant::getAllOnesValue(Ty) :
6339 Constant::getNullValue(Ty);
6340 unsigned CPI = MCP.getConstantPoolIndex(C, Alignment);
6341
6342 // Create operands to load from the constant pool entry.
6343 MOs.push_back(MachineOperand::CreateReg(PICBase, false));
6344 MOs.push_back(MachineOperand::CreateImm(1));
6345 MOs.push_back(MachineOperand::CreateReg(0, false));
6346 MOs.push_back(MachineOperand::CreateCPI(CPI, 0));
6347 MOs.push_back(MachineOperand::CreateReg(0, false));
6348 break;
6349 }
6350 default: {
6351 if (isNonFoldablePartialRegisterLoad(LoadMI, MI, MF))
6352 return nullptr;
6353
6354 // Folding a normal load. Just copy the load's address operands.
6355 MOs.append(LoadMI.operands_begin() + NumOps - X86::AddrNumOperands,
6356 LoadMI.operands_begin() + NumOps);
6357 break;
6358 }
6359 }
6360 return foldMemoryOperandImpl(MF, MI, Ops[0], MOs, InsertPt,
6361 /*Size=*/0, Alignment, /*AllowCommute=*/true);
6362 }
6363
unfoldMemoryOperand(MachineFunction & MF,MachineInstr & MI,unsigned Reg,bool UnfoldLoad,bool UnfoldStore,SmallVectorImpl<MachineInstr * > & NewMIs) const6364 bool X86InstrInfo::unfoldMemoryOperand(
6365 MachineFunction &MF, MachineInstr &MI, unsigned Reg, bool UnfoldLoad,
6366 bool UnfoldStore, SmallVectorImpl<MachineInstr *> &NewMIs) const {
6367 auto I = MemOp2RegOpTable.find(MI.getOpcode());
6368 if (I == MemOp2RegOpTable.end())
6369 return false;
6370 unsigned Opc = I->second.first;
6371 unsigned Index = I->second.second & TB_INDEX_MASK;
6372 bool FoldedLoad = I->second.second & TB_FOLDED_LOAD;
6373 bool FoldedStore = I->second.second & TB_FOLDED_STORE;
6374 if (UnfoldLoad && !FoldedLoad)
6375 return false;
6376 UnfoldLoad &= FoldedLoad;
6377 if (UnfoldStore && !FoldedStore)
6378 return false;
6379 UnfoldStore &= FoldedStore;
6380
6381 const MCInstrDesc &MCID = get(Opc);
6382 const TargetRegisterClass *RC = getRegClass(MCID, Index, &RI, MF);
6383 // TODO: Check if 32-byte or greater accesses are slow too?
6384 if (!MI.hasOneMemOperand() && RC == &X86::VR128RegClass &&
6385 Subtarget.isUnalignedMem16Slow())
6386 // Without memoperands, loadRegFromAddr and storeRegToStackSlot will
6387 // conservatively assume the address is unaligned. That's bad for
6388 // performance.
6389 return false;
6390 SmallVector<MachineOperand, X86::AddrNumOperands> AddrOps;
6391 SmallVector<MachineOperand,2> BeforeOps;
6392 SmallVector<MachineOperand,2> AfterOps;
6393 SmallVector<MachineOperand,4> ImpOps;
6394 for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) {
6395 MachineOperand &Op = MI.getOperand(i);
6396 if (i >= Index && i < Index + X86::AddrNumOperands)
6397 AddrOps.push_back(Op);
6398 else if (Op.isReg() && Op.isImplicit())
6399 ImpOps.push_back(Op);
6400 else if (i < Index)
6401 BeforeOps.push_back(Op);
6402 else if (i > Index)
6403 AfterOps.push_back(Op);
6404 }
6405
6406 // Emit the load instruction.
6407 if (UnfoldLoad) {
6408 std::pair<MachineInstr::mmo_iterator, MachineInstr::mmo_iterator> MMOs =
6409 MF.extractLoadMemRefs(MI.memoperands_begin(), MI.memoperands_end());
6410 loadRegFromAddr(MF, Reg, AddrOps, RC, MMOs.first, MMOs.second, NewMIs);
6411 if (UnfoldStore) {
6412 // Address operands cannot be marked isKill.
6413 for (unsigned i = 1; i != 1 + X86::AddrNumOperands; ++i) {
6414 MachineOperand &MO = NewMIs[0]->getOperand(i);
6415 if (MO.isReg())
6416 MO.setIsKill(false);
6417 }
6418 }
6419 }
6420
6421 // Emit the data processing instruction.
6422 MachineInstr *DataMI = MF.CreateMachineInstr(MCID, MI.getDebugLoc(), true);
6423 MachineInstrBuilder MIB(MF, DataMI);
6424
6425 if (FoldedStore)
6426 MIB.addReg(Reg, RegState::Define);
6427 for (MachineOperand &BeforeOp : BeforeOps)
6428 MIB.addOperand(BeforeOp);
6429 if (FoldedLoad)
6430 MIB.addReg(Reg);
6431 for (MachineOperand &AfterOp : AfterOps)
6432 MIB.addOperand(AfterOp);
6433 for (MachineOperand &ImpOp : ImpOps) {
6434 MIB.addReg(ImpOp.getReg(),
6435 getDefRegState(ImpOp.isDef()) |
6436 RegState::Implicit |
6437 getKillRegState(ImpOp.isKill()) |
6438 getDeadRegState(ImpOp.isDead()) |
6439 getUndefRegState(ImpOp.isUndef()));
6440 }
6441 // Change CMP32ri r, 0 back to TEST32rr r, r, etc.
6442 switch (DataMI->getOpcode()) {
6443 default: break;
6444 case X86::CMP64ri32:
6445 case X86::CMP64ri8:
6446 case X86::CMP32ri:
6447 case X86::CMP32ri8:
6448 case X86::CMP16ri:
6449 case X86::CMP16ri8:
6450 case X86::CMP8ri: {
6451 MachineOperand &MO0 = DataMI->getOperand(0);
6452 MachineOperand &MO1 = DataMI->getOperand(1);
6453 if (MO1.getImm() == 0) {
6454 unsigned NewOpc;
6455 switch (DataMI->getOpcode()) {
6456 default: llvm_unreachable("Unreachable!");
6457 case X86::CMP64ri8:
6458 case X86::CMP64ri32: NewOpc = X86::TEST64rr; break;
6459 case X86::CMP32ri8:
6460 case X86::CMP32ri: NewOpc = X86::TEST32rr; break;
6461 case X86::CMP16ri8:
6462 case X86::CMP16ri: NewOpc = X86::TEST16rr; break;
6463 case X86::CMP8ri: NewOpc = X86::TEST8rr; break;
6464 }
6465 DataMI->setDesc(get(NewOpc));
6466 MO1.ChangeToRegister(MO0.getReg(), false);
6467 }
6468 }
6469 }
6470 NewMIs.push_back(DataMI);
6471
6472 // Emit the store instruction.
6473 if (UnfoldStore) {
6474 const TargetRegisterClass *DstRC = getRegClass(MCID, 0, &RI, MF);
6475 std::pair<MachineInstr::mmo_iterator, MachineInstr::mmo_iterator> MMOs =
6476 MF.extractStoreMemRefs(MI.memoperands_begin(), MI.memoperands_end());
6477 storeRegToAddr(MF, Reg, true, AddrOps, DstRC, MMOs.first, MMOs.second, NewMIs);
6478 }
6479
6480 return true;
6481 }
6482
6483 bool
unfoldMemoryOperand(SelectionDAG & DAG,SDNode * N,SmallVectorImpl<SDNode * > & NewNodes) const6484 X86InstrInfo::unfoldMemoryOperand(SelectionDAG &DAG, SDNode *N,
6485 SmallVectorImpl<SDNode*> &NewNodes) const {
6486 if (!N->isMachineOpcode())
6487 return false;
6488
6489 auto I = MemOp2RegOpTable.find(N->getMachineOpcode());
6490 if (I == MemOp2RegOpTable.end())
6491 return false;
6492 unsigned Opc = I->second.first;
6493 unsigned Index = I->second.second & TB_INDEX_MASK;
6494 bool FoldedLoad = I->second.second & TB_FOLDED_LOAD;
6495 bool FoldedStore = I->second.second & TB_FOLDED_STORE;
6496 const MCInstrDesc &MCID = get(Opc);
6497 MachineFunction &MF = DAG.getMachineFunction();
6498 const TargetRegisterClass *RC = getRegClass(MCID, Index, &RI, MF);
6499 unsigned NumDefs = MCID.NumDefs;
6500 std::vector<SDValue> AddrOps;
6501 std::vector<SDValue> BeforeOps;
6502 std::vector<SDValue> AfterOps;
6503 SDLoc dl(N);
6504 unsigned NumOps = N->getNumOperands();
6505 for (unsigned i = 0; i != NumOps-1; ++i) {
6506 SDValue Op = N->getOperand(i);
6507 if (i >= Index-NumDefs && i < Index-NumDefs + X86::AddrNumOperands)
6508 AddrOps.push_back(Op);
6509 else if (i < Index-NumDefs)
6510 BeforeOps.push_back(Op);
6511 else if (i > Index-NumDefs)
6512 AfterOps.push_back(Op);
6513 }
6514 SDValue Chain = N->getOperand(NumOps-1);
6515 AddrOps.push_back(Chain);
6516
6517 // Emit the load instruction.
6518 SDNode *Load = nullptr;
6519 if (FoldedLoad) {
6520 EVT VT = *RC->vt_begin();
6521 std::pair<MachineInstr::mmo_iterator,
6522 MachineInstr::mmo_iterator> MMOs =
6523 MF.extractLoadMemRefs(cast<MachineSDNode>(N)->memoperands_begin(),
6524 cast<MachineSDNode>(N)->memoperands_end());
6525 if (!(*MMOs.first) &&
6526 RC == &X86::VR128RegClass &&
6527 Subtarget.isUnalignedMem16Slow())
6528 // Do not introduce a slow unaligned load.
6529 return false;
6530 // FIXME: If a VR128 can have size 32, we should be checking if a 32-byte
6531 // memory access is slow above.
6532 unsigned Alignment = RC->getSize() == 32 ? 32 : 16;
6533 bool isAligned = (*MMOs.first) &&
6534 (*MMOs.first)->getAlignment() >= Alignment;
6535 Load = DAG.getMachineNode(getLoadRegOpcode(0, RC, isAligned, Subtarget), dl,
6536 VT, MVT::Other, AddrOps);
6537 NewNodes.push_back(Load);
6538
6539 // Preserve memory reference information.
6540 cast<MachineSDNode>(Load)->setMemRefs(MMOs.first, MMOs.second);
6541 }
6542
6543 // Emit the data processing instruction.
6544 std::vector<EVT> VTs;
6545 const TargetRegisterClass *DstRC = nullptr;
6546 if (MCID.getNumDefs() > 0) {
6547 DstRC = getRegClass(MCID, 0, &RI, MF);
6548 VTs.push_back(*DstRC->vt_begin());
6549 }
6550 for (unsigned i = 0, e = N->getNumValues(); i != e; ++i) {
6551 EVT VT = N->getValueType(i);
6552 if (VT != MVT::Other && i >= (unsigned)MCID.getNumDefs())
6553 VTs.push_back(VT);
6554 }
6555 if (Load)
6556 BeforeOps.push_back(SDValue(Load, 0));
6557 BeforeOps.insert(BeforeOps.end(), AfterOps.begin(), AfterOps.end());
6558 SDNode *NewNode= DAG.getMachineNode(Opc, dl, VTs, BeforeOps);
6559 NewNodes.push_back(NewNode);
6560
6561 // Emit the store instruction.
6562 if (FoldedStore) {
6563 AddrOps.pop_back();
6564 AddrOps.push_back(SDValue(NewNode, 0));
6565 AddrOps.push_back(Chain);
6566 std::pair<MachineInstr::mmo_iterator,
6567 MachineInstr::mmo_iterator> MMOs =
6568 MF.extractStoreMemRefs(cast<MachineSDNode>(N)->memoperands_begin(),
6569 cast<MachineSDNode>(N)->memoperands_end());
6570 if (!(*MMOs.first) &&
6571 RC == &X86::VR128RegClass &&
6572 Subtarget.isUnalignedMem16Slow())
6573 // Do not introduce a slow unaligned store.
6574 return false;
6575 // FIXME: If a VR128 can have size 32, we should be checking if a 32-byte
6576 // memory access is slow above.
6577 unsigned Alignment = RC->getSize() == 32 ? 32 : 16;
6578 bool isAligned = (*MMOs.first) &&
6579 (*MMOs.first)->getAlignment() >= Alignment;
6580 SDNode *Store =
6581 DAG.getMachineNode(getStoreRegOpcode(0, DstRC, isAligned, Subtarget),
6582 dl, MVT::Other, AddrOps);
6583 NewNodes.push_back(Store);
6584
6585 // Preserve memory reference information.
6586 cast<MachineSDNode>(Store)->setMemRefs(MMOs.first, MMOs.second);
6587 }
6588
6589 return true;
6590 }
6591
getOpcodeAfterMemoryUnfold(unsigned Opc,bool UnfoldLoad,bool UnfoldStore,unsigned * LoadRegIndex) const6592 unsigned X86InstrInfo::getOpcodeAfterMemoryUnfold(unsigned Opc,
6593 bool UnfoldLoad, bool UnfoldStore,
6594 unsigned *LoadRegIndex) const {
6595 auto I = MemOp2RegOpTable.find(Opc);
6596 if (I == MemOp2RegOpTable.end())
6597 return 0;
6598 bool FoldedLoad = I->second.second & TB_FOLDED_LOAD;
6599 bool FoldedStore = I->second.second & TB_FOLDED_STORE;
6600 if (UnfoldLoad && !FoldedLoad)
6601 return 0;
6602 if (UnfoldStore && !FoldedStore)
6603 return 0;
6604 if (LoadRegIndex)
6605 *LoadRegIndex = I->second.second & TB_INDEX_MASK;
6606 return I->second.first;
6607 }
6608
6609 bool
areLoadsFromSameBasePtr(SDNode * Load1,SDNode * Load2,int64_t & Offset1,int64_t & Offset2) const6610 X86InstrInfo::areLoadsFromSameBasePtr(SDNode *Load1, SDNode *Load2,
6611 int64_t &Offset1, int64_t &Offset2) const {
6612 if (!Load1->isMachineOpcode() || !Load2->isMachineOpcode())
6613 return false;
6614 unsigned Opc1 = Load1->getMachineOpcode();
6615 unsigned Opc2 = Load2->getMachineOpcode();
6616 switch (Opc1) {
6617 default: return false;
6618 case X86::MOV8rm:
6619 case X86::MOV16rm:
6620 case X86::MOV32rm:
6621 case X86::MOV64rm:
6622 case X86::LD_Fp32m:
6623 case X86::LD_Fp64m:
6624 case X86::LD_Fp80m:
6625 case X86::MOVSSrm:
6626 case X86::MOVSDrm:
6627 case X86::MMX_MOVD64rm:
6628 case X86::MMX_MOVQ64rm:
6629 case X86::FsMOVAPSrm:
6630 case X86::FsMOVAPDrm:
6631 case X86::MOVAPSrm:
6632 case X86::MOVUPSrm:
6633 case X86::MOVAPDrm:
6634 case X86::MOVDQArm:
6635 case X86::MOVDQUrm:
6636 // AVX load instructions
6637 case X86::VMOVSSrm:
6638 case X86::VMOVSDrm:
6639 case X86::FsVMOVAPSrm:
6640 case X86::FsVMOVAPDrm:
6641 case X86::VMOVAPSrm:
6642 case X86::VMOVUPSrm:
6643 case X86::VMOVAPDrm:
6644 case X86::VMOVDQArm:
6645 case X86::VMOVDQUrm:
6646 case X86::VMOVAPSYrm:
6647 case X86::VMOVUPSYrm:
6648 case X86::VMOVAPDYrm:
6649 case X86::VMOVDQAYrm:
6650 case X86::VMOVDQUYrm:
6651 break;
6652 }
6653 switch (Opc2) {
6654 default: return false;
6655 case X86::MOV8rm:
6656 case X86::MOV16rm:
6657 case X86::MOV32rm:
6658 case X86::MOV64rm:
6659 case X86::LD_Fp32m:
6660 case X86::LD_Fp64m:
6661 case X86::LD_Fp80m:
6662 case X86::MOVSSrm:
6663 case X86::MOVSDrm:
6664 case X86::MMX_MOVD64rm:
6665 case X86::MMX_MOVQ64rm:
6666 case X86::FsMOVAPSrm:
6667 case X86::FsMOVAPDrm:
6668 case X86::MOVAPSrm:
6669 case X86::MOVUPSrm:
6670 case X86::MOVAPDrm:
6671 case X86::MOVDQArm:
6672 case X86::MOVDQUrm:
6673 // AVX load instructions
6674 case X86::VMOVSSrm:
6675 case X86::VMOVSDrm:
6676 case X86::FsVMOVAPSrm:
6677 case X86::FsVMOVAPDrm:
6678 case X86::VMOVAPSrm:
6679 case X86::VMOVUPSrm:
6680 case X86::VMOVAPDrm:
6681 case X86::VMOVDQArm:
6682 case X86::VMOVDQUrm:
6683 case X86::VMOVAPSYrm:
6684 case X86::VMOVUPSYrm:
6685 case X86::VMOVAPDYrm:
6686 case X86::VMOVDQAYrm:
6687 case X86::VMOVDQUYrm:
6688 break;
6689 }
6690
6691 // Check if chain operands and base addresses match.
6692 if (Load1->getOperand(0) != Load2->getOperand(0) ||
6693 Load1->getOperand(5) != Load2->getOperand(5))
6694 return false;
6695 // Segment operands should match as well.
6696 if (Load1->getOperand(4) != Load2->getOperand(4))
6697 return false;
6698 // Scale should be 1, Index should be Reg0.
6699 if (Load1->getOperand(1) == Load2->getOperand(1) &&
6700 Load1->getOperand(2) == Load2->getOperand(2)) {
6701 if (cast<ConstantSDNode>(Load1->getOperand(1))->getZExtValue() != 1)
6702 return false;
6703
6704 // Now let's examine the displacements.
6705 if (isa<ConstantSDNode>(Load1->getOperand(3)) &&
6706 isa<ConstantSDNode>(Load2->getOperand(3))) {
6707 Offset1 = cast<ConstantSDNode>(Load1->getOperand(3))->getSExtValue();
6708 Offset2 = cast<ConstantSDNode>(Load2->getOperand(3))->getSExtValue();
6709 return true;
6710 }
6711 }
6712 return false;
6713 }
6714
shouldScheduleLoadsNear(SDNode * Load1,SDNode * Load2,int64_t Offset1,int64_t Offset2,unsigned NumLoads) const6715 bool X86InstrInfo::shouldScheduleLoadsNear(SDNode *Load1, SDNode *Load2,
6716 int64_t Offset1, int64_t Offset2,
6717 unsigned NumLoads) const {
6718 assert(Offset2 > Offset1);
6719 if ((Offset2 - Offset1) / 8 > 64)
6720 return false;
6721
6722 unsigned Opc1 = Load1->getMachineOpcode();
6723 unsigned Opc2 = Load2->getMachineOpcode();
6724 if (Opc1 != Opc2)
6725 return false; // FIXME: overly conservative?
6726
6727 switch (Opc1) {
6728 default: break;
6729 case X86::LD_Fp32m:
6730 case X86::LD_Fp64m:
6731 case X86::LD_Fp80m:
6732 case X86::MMX_MOVD64rm:
6733 case X86::MMX_MOVQ64rm:
6734 return false;
6735 }
6736
6737 EVT VT = Load1->getValueType(0);
6738 switch (VT.getSimpleVT().SimpleTy) {
6739 default:
6740 // XMM registers. In 64-bit mode we can be a bit more aggressive since we
6741 // have 16 of them to play with.
6742 if (Subtarget.is64Bit()) {
6743 if (NumLoads >= 3)
6744 return false;
6745 } else if (NumLoads) {
6746 return false;
6747 }
6748 break;
6749 case MVT::i8:
6750 case MVT::i16:
6751 case MVT::i32:
6752 case MVT::i64:
6753 case MVT::f32:
6754 case MVT::f64:
6755 if (NumLoads)
6756 return false;
6757 break;
6758 }
6759
6760 return true;
6761 }
6762
shouldScheduleAdjacent(MachineInstr & First,MachineInstr & Second) const6763 bool X86InstrInfo::shouldScheduleAdjacent(MachineInstr &First,
6764 MachineInstr &Second) const {
6765 // Check if this processor supports macro-fusion. Since this is a minor
6766 // heuristic, we haven't specifically reserved a feature. hasAVX is a decent
6767 // proxy for SandyBridge+.
6768 if (!Subtarget.hasAVX())
6769 return false;
6770
6771 enum {
6772 FuseTest,
6773 FuseCmp,
6774 FuseInc
6775 } FuseKind;
6776
6777 switch (Second.getOpcode()) {
6778 default:
6779 return false;
6780 case X86::JE_1:
6781 case X86::JNE_1:
6782 case X86::JL_1:
6783 case X86::JLE_1:
6784 case X86::JG_1:
6785 case X86::JGE_1:
6786 FuseKind = FuseInc;
6787 break;
6788 case X86::JB_1:
6789 case X86::JBE_1:
6790 case X86::JA_1:
6791 case X86::JAE_1:
6792 FuseKind = FuseCmp;
6793 break;
6794 case X86::JS_1:
6795 case X86::JNS_1:
6796 case X86::JP_1:
6797 case X86::JNP_1:
6798 case X86::JO_1:
6799 case X86::JNO_1:
6800 FuseKind = FuseTest;
6801 break;
6802 }
6803 switch (First.getOpcode()) {
6804 default:
6805 return false;
6806 case X86::TEST8rr:
6807 case X86::TEST16rr:
6808 case X86::TEST32rr:
6809 case X86::TEST64rr:
6810 case X86::TEST8ri:
6811 case X86::TEST16ri:
6812 case X86::TEST32ri:
6813 case X86::TEST32i32:
6814 case X86::TEST64i32:
6815 case X86::TEST64ri32:
6816 case X86::TEST8rm:
6817 case X86::TEST16rm:
6818 case X86::TEST32rm:
6819 case X86::TEST64rm:
6820 case X86::TEST8ri_NOREX:
6821 case X86::AND16i16:
6822 case X86::AND16ri:
6823 case X86::AND16ri8:
6824 case X86::AND16rm:
6825 case X86::AND16rr:
6826 case X86::AND32i32:
6827 case X86::AND32ri:
6828 case X86::AND32ri8:
6829 case X86::AND32rm:
6830 case X86::AND32rr:
6831 case X86::AND64i32:
6832 case X86::AND64ri32:
6833 case X86::AND64ri8:
6834 case X86::AND64rm:
6835 case X86::AND64rr:
6836 case X86::AND8i8:
6837 case X86::AND8ri:
6838 case X86::AND8rm:
6839 case X86::AND8rr:
6840 return true;
6841 case X86::CMP16i16:
6842 case X86::CMP16ri:
6843 case X86::CMP16ri8:
6844 case X86::CMP16rm:
6845 case X86::CMP16rr:
6846 case X86::CMP32i32:
6847 case X86::CMP32ri:
6848 case X86::CMP32ri8:
6849 case X86::CMP32rm:
6850 case X86::CMP32rr:
6851 case X86::CMP64i32:
6852 case X86::CMP64ri32:
6853 case X86::CMP64ri8:
6854 case X86::CMP64rm:
6855 case X86::CMP64rr:
6856 case X86::CMP8i8:
6857 case X86::CMP8ri:
6858 case X86::CMP8rm:
6859 case X86::CMP8rr:
6860 case X86::ADD16i16:
6861 case X86::ADD16ri:
6862 case X86::ADD16ri8:
6863 case X86::ADD16ri8_DB:
6864 case X86::ADD16ri_DB:
6865 case X86::ADD16rm:
6866 case X86::ADD16rr:
6867 case X86::ADD16rr_DB:
6868 case X86::ADD32i32:
6869 case X86::ADD32ri:
6870 case X86::ADD32ri8:
6871 case X86::ADD32ri8_DB:
6872 case X86::ADD32ri_DB:
6873 case X86::ADD32rm:
6874 case X86::ADD32rr:
6875 case X86::ADD32rr_DB:
6876 case X86::ADD64i32:
6877 case X86::ADD64ri32:
6878 case X86::ADD64ri32_DB:
6879 case X86::ADD64ri8:
6880 case X86::ADD64ri8_DB:
6881 case X86::ADD64rm:
6882 case X86::ADD64rr:
6883 case X86::ADD64rr_DB:
6884 case X86::ADD8i8:
6885 case X86::ADD8mi:
6886 case X86::ADD8mr:
6887 case X86::ADD8ri:
6888 case X86::ADD8rm:
6889 case X86::ADD8rr:
6890 case X86::SUB16i16:
6891 case X86::SUB16ri:
6892 case X86::SUB16ri8:
6893 case X86::SUB16rm:
6894 case X86::SUB16rr:
6895 case X86::SUB32i32:
6896 case X86::SUB32ri:
6897 case X86::SUB32ri8:
6898 case X86::SUB32rm:
6899 case X86::SUB32rr:
6900 case X86::SUB64i32:
6901 case X86::SUB64ri32:
6902 case X86::SUB64ri8:
6903 case X86::SUB64rm:
6904 case X86::SUB64rr:
6905 case X86::SUB8i8:
6906 case X86::SUB8ri:
6907 case X86::SUB8rm:
6908 case X86::SUB8rr:
6909 return FuseKind == FuseCmp || FuseKind == FuseInc;
6910 case X86::INC16r:
6911 case X86::INC32r:
6912 case X86::INC64r:
6913 case X86::INC8r:
6914 case X86::DEC16r:
6915 case X86::DEC32r:
6916 case X86::DEC64r:
6917 case X86::DEC8r:
6918 return FuseKind == FuseInc;
6919 }
6920 }
6921
6922 bool X86InstrInfo::
ReverseBranchCondition(SmallVectorImpl<MachineOperand> & Cond) const6923 ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const {
6924 assert(Cond.size() == 1 && "Invalid X86 branch condition!");
6925 X86::CondCode CC = static_cast<X86::CondCode>(Cond[0].getImm());
6926 Cond[0].setImm(GetOppositeBranchCondition(CC));
6927 return false;
6928 }
6929
6930 bool X86InstrInfo::
isSafeToMoveRegClassDefs(const TargetRegisterClass * RC) const6931 isSafeToMoveRegClassDefs(const TargetRegisterClass *RC) const {
6932 // FIXME: Return false for x87 stack register classes for now. We can't
6933 // allow any loads of these registers before FpGet_ST0_80.
6934 return !(RC == &X86::CCRRegClass || RC == &X86::RFP32RegClass ||
6935 RC == &X86::RFP64RegClass || RC == &X86::RFP80RegClass);
6936 }
6937
6938 /// Return a virtual register initialized with the
6939 /// the global base register value. Output instructions required to
6940 /// initialize the register in the function entry block, if necessary.
6941 ///
6942 /// TODO: Eliminate this and move the code to X86MachineFunctionInfo.
6943 ///
getGlobalBaseReg(MachineFunction * MF) const6944 unsigned X86InstrInfo::getGlobalBaseReg(MachineFunction *MF) const {
6945 assert(!Subtarget.is64Bit() &&
6946 "X86-64 PIC uses RIP relative addressing");
6947
6948 X86MachineFunctionInfo *X86FI = MF->getInfo<X86MachineFunctionInfo>();
6949 unsigned GlobalBaseReg = X86FI->getGlobalBaseReg();
6950 if (GlobalBaseReg != 0)
6951 return GlobalBaseReg;
6952
6953 // Create the register. The code to initialize it is inserted
6954 // later, by the CGBR pass (below).
6955 MachineRegisterInfo &RegInfo = MF->getRegInfo();
6956 GlobalBaseReg = RegInfo.createVirtualRegister(&X86::GR32_NOSPRegClass);
6957 X86FI->setGlobalBaseReg(GlobalBaseReg);
6958 return GlobalBaseReg;
6959 }
6960
6961 // These are the replaceable SSE instructions. Some of these have Int variants
6962 // that we don't include here. We don't want to replace instructions selected
6963 // by intrinsics.
6964 static const uint16_t ReplaceableInstrs[][3] = {
6965 //PackedSingle PackedDouble PackedInt
6966 { X86::MOVAPSmr, X86::MOVAPDmr, X86::MOVDQAmr },
6967 { X86::MOVAPSrm, X86::MOVAPDrm, X86::MOVDQArm },
6968 { X86::MOVAPSrr, X86::MOVAPDrr, X86::MOVDQArr },
6969 { X86::MOVUPSmr, X86::MOVUPDmr, X86::MOVDQUmr },
6970 { X86::MOVUPSrm, X86::MOVUPDrm, X86::MOVDQUrm },
6971 { X86::MOVLPSmr, X86::MOVLPDmr, X86::MOVPQI2QImr },
6972 { X86::MOVNTPSmr, X86::MOVNTPDmr, X86::MOVNTDQmr },
6973 { X86::ANDNPSrm, X86::ANDNPDrm, X86::PANDNrm },
6974 { X86::ANDNPSrr, X86::ANDNPDrr, X86::PANDNrr },
6975 { X86::ANDPSrm, X86::ANDPDrm, X86::PANDrm },
6976 { X86::ANDPSrr, X86::ANDPDrr, X86::PANDrr },
6977 { X86::ORPSrm, X86::ORPDrm, X86::PORrm },
6978 { X86::ORPSrr, X86::ORPDrr, X86::PORrr },
6979 { X86::XORPSrm, X86::XORPDrm, X86::PXORrm },
6980 { X86::XORPSrr, X86::XORPDrr, X86::PXORrr },
6981 // AVX 128-bit support
6982 { X86::VMOVAPSmr, X86::VMOVAPDmr, X86::VMOVDQAmr },
6983 { X86::VMOVAPSrm, X86::VMOVAPDrm, X86::VMOVDQArm },
6984 { X86::VMOVAPSrr, X86::VMOVAPDrr, X86::VMOVDQArr },
6985 { X86::VMOVUPSmr, X86::VMOVUPDmr, X86::VMOVDQUmr },
6986 { X86::VMOVUPSrm, X86::VMOVUPDrm, X86::VMOVDQUrm },
6987 { X86::VMOVLPSmr, X86::VMOVLPDmr, X86::VMOVPQI2QImr },
6988 { X86::VMOVNTPSmr, X86::VMOVNTPDmr, X86::VMOVNTDQmr },
6989 { X86::VANDNPSrm, X86::VANDNPDrm, X86::VPANDNrm },
6990 { X86::VANDNPSrr, X86::VANDNPDrr, X86::VPANDNrr },
6991 { X86::VANDPSrm, X86::VANDPDrm, X86::VPANDrm },
6992 { X86::VANDPSrr, X86::VANDPDrr, X86::VPANDrr },
6993 { X86::VORPSrm, X86::VORPDrm, X86::VPORrm },
6994 { X86::VORPSrr, X86::VORPDrr, X86::VPORrr },
6995 { X86::VXORPSrm, X86::VXORPDrm, X86::VPXORrm },
6996 { X86::VXORPSrr, X86::VXORPDrr, X86::VPXORrr },
6997 // AVX 256-bit support
6998 { X86::VMOVAPSYmr, X86::VMOVAPDYmr, X86::VMOVDQAYmr },
6999 { X86::VMOVAPSYrm, X86::VMOVAPDYrm, X86::VMOVDQAYrm },
7000 { X86::VMOVAPSYrr, X86::VMOVAPDYrr, X86::VMOVDQAYrr },
7001 { X86::VMOVUPSYmr, X86::VMOVUPDYmr, X86::VMOVDQUYmr },
7002 { X86::VMOVUPSYrm, X86::VMOVUPDYrm, X86::VMOVDQUYrm },
7003 { X86::VMOVNTPSYmr, X86::VMOVNTPDYmr, X86::VMOVNTDQYmr }
7004 };
7005
7006 static const uint16_t ReplaceableInstrsAVX2[][3] = {
7007 //PackedSingle PackedDouble PackedInt
7008 { X86::VANDNPSYrm, X86::VANDNPDYrm, X86::VPANDNYrm },
7009 { X86::VANDNPSYrr, X86::VANDNPDYrr, X86::VPANDNYrr },
7010 { X86::VANDPSYrm, X86::VANDPDYrm, X86::VPANDYrm },
7011 { X86::VANDPSYrr, X86::VANDPDYrr, X86::VPANDYrr },
7012 { X86::VORPSYrm, X86::VORPDYrm, X86::VPORYrm },
7013 { X86::VORPSYrr, X86::VORPDYrr, X86::VPORYrr },
7014 { X86::VXORPSYrm, X86::VXORPDYrm, X86::VPXORYrm },
7015 { X86::VXORPSYrr, X86::VXORPDYrr, X86::VPXORYrr },
7016 { X86::VEXTRACTF128mr, X86::VEXTRACTF128mr, X86::VEXTRACTI128mr },
7017 { X86::VEXTRACTF128rr, X86::VEXTRACTF128rr, X86::VEXTRACTI128rr },
7018 { X86::VINSERTF128rm, X86::VINSERTF128rm, X86::VINSERTI128rm },
7019 { X86::VINSERTF128rr, X86::VINSERTF128rr, X86::VINSERTI128rr },
7020 { X86::VPERM2F128rm, X86::VPERM2F128rm, X86::VPERM2I128rm },
7021 { X86::VPERM2F128rr, X86::VPERM2F128rr, X86::VPERM2I128rr },
7022 { X86::VBROADCASTSSrm, X86::VBROADCASTSSrm, X86::VPBROADCASTDrm},
7023 { X86::VBROADCASTSSrr, X86::VBROADCASTSSrr, X86::VPBROADCASTDrr},
7024 { X86::VBROADCASTSSYrr, X86::VBROADCASTSSYrr, X86::VPBROADCASTDYrr},
7025 { X86::VBROADCASTSSYrm, X86::VBROADCASTSSYrm, X86::VPBROADCASTDYrm},
7026 { X86::VBROADCASTSDYrr, X86::VBROADCASTSDYrr, X86::VPBROADCASTQYrr},
7027 { X86::VBROADCASTSDYrm, X86::VBROADCASTSDYrm, X86::VPBROADCASTQYrm}
7028 };
7029
7030 // FIXME: Some shuffle and unpack instructions have equivalents in different
7031 // domains, but they require a bit more work than just switching opcodes.
7032
lookup(unsigned opcode,unsigned domain)7033 static const uint16_t *lookup(unsigned opcode, unsigned domain) {
7034 for (const uint16_t (&Row)[3] : ReplaceableInstrs)
7035 if (Row[domain-1] == opcode)
7036 return Row;
7037 return nullptr;
7038 }
7039
lookupAVX2(unsigned opcode,unsigned domain)7040 static const uint16_t *lookupAVX2(unsigned opcode, unsigned domain) {
7041 for (const uint16_t (&Row)[3] : ReplaceableInstrsAVX2)
7042 if (Row[domain-1] == opcode)
7043 return Row;
7044 return nullptr;
7045 }
7046
7047 std::pair<uint16_t, uint16_t>
getExecutionDomain(const MachineInstr & MI) const7048 X86InstrInfo::getExecutionDomain(const MachineInstr &MI) const {
7049 uint16_t domain = (MI.getDesc().TSFlags >> X86II::SSEDomainShift) & 3;
7050 bool hasAVX2 = Subtarget.hasAVX2();
7051 uint16_t validDomains = 0;
7052 if (domain && lookup(MI.getOpcode(), domain))
7053 validDomains = 0xe;
7054 else if (domain && lookupAVX2(MI.getOpcode(), domain))
7055 validDomains = hasAVX2 ? 0xe : 0x6;
7056 return std::make_pair(domain, validDomains);
7057 }
7058
setExecutionDomain(MachineInstr & MI,unsigned Domain) const7059 void X86InstrInfo::setExecutionDomain(MachineInstr &MI, unsigned Domain) const {
7060 assert(Domain>0 && Domain<4 && "Invalid execution domain");
7061 uint16_t dom = (MI.getDesc().TSFlags >> X86II::SSEDomainShift) & 3;
7062 assert(dom && "Not an SSE instruction");
7063 const uint16_t *table = lookup(MI.getOpcode(), dom);
7064 if (!table) { // try the other table
7065 assert((Subtarget.hasAVX2() || Domain < 3) &&
7066 "256-bit vector operations only available in AVX2");
7067 table = lookupAVX2(MI.getOpcode(), dom);
7068 }
7069 assert(table && "Cannot change domain");
7070 MI.setDesc(get(table[Domain - 1]));
7071 }
7072
7073 /// Return the noop instruction to use for a noop.
getNoopForMachoTarget(MCInst & NopInst) const7074 void X86InstrInfo::getNoopForMachoTarget(MCInst &NopInst) const {
7075 NopInst.setOpcode(X86::NOOP);
7076 }
7077
7078 // This code must remain in sync with getJumpInstrTableEntryBound in this class!
7079 // In particular, getJumpInstrTableEntryBound must always return an upper bound
7080 // on the encoding lengths of the instructions generated by
7081 // getUnconditionalBranch and getTrap.
getUnconditionalBranch(MCInst & Branch,const MCSymbolRefExpr * BranchTarget) const7082 void X86InstrInfo::getUnconditionalBranch(
7083 MCInst &Branch, const MCSymbolRefExpr *BranchTarget) const {
7084 Branch.setOpcode(X86::JMP_1);
7085 Branch.addOperand(MCOperand::createExpr(BranchTarget));
7086 }
7087
7088 // This code must remain in sync with getJumpInstrTableEntryBound in this class!
7089 // In particular, getJumpInstrTableEntryBound must always return an upper bound
7090 // on the encoding lengths of the instructions generated by
7091 // getUnconditionalBranch and getTrap.
getTrap(MCInst & MI) const7092 void X86InstrInfo::getTrap(MCInst &MI) const {
7093 MI.setOpcode(X86::TRAP);
7094 }
7095
7096 // See getTrap and getUnconditionalBranch for conditions on the value returned
7097 // by this function.
getJumpInstrTableEntryBound() const7098 unsigned X86InstrInfo::getJumpInstrTableEntryBound() const {
7099 // 5 bytes suffice: JMP_4 Symbol@PLT is uses 1 byte (E9) for the JMP_4 and 4
7100 // bytes for the symbol offset. And TRAP is ud2, which is two bytes (0F 0B).
7101 return 5;
7102 }
7103
isHighLatencyDef(int opc) const7104 bool X86InstrInfo::isHighLatencyDef(int opc) const {
7105 switch (opc) {
7106 default: return false;
7107 case X86::DIVSDrm:
7108 case X86::DIVSDrm_Int:
7109 case X86::DIVSDrr:
7110 case X86::DIVSDrr_Int:
7111 case X86::DIVSSrm:
7112 case X86::DIVSSrm_Int:
7113 case X86::DIVSSrr:
7114 case X86::DIVSSrr_Int:
7115 case X86::SQRTPDm:
7116 case X86::SQRTPDr:
7117 case X86::SQRTPSm:
7118 case X86::SQRTPSr:
7119 case X86::SQRTSDm:
7120 case X86::SQRTSDm_Int:
7121 case X86::SQRTSDr:
7122 case X86::SQRTSDr_Int:
7123 case X86::SQRTSSm:
7124 case X86::SQRTSSm_Int:
7125 case X86::SQRTSSr:
7126 case X86::SQRTSSr_Int:
7127 // AVX instructions with high latency
7128 case X86::VDIVSDrm:
7129 case X86::VDIVSDrm_Int:
7130 case X86::VDIVSDrr:
7131 case X86::VDIVSDrr_Int:
7132 case X86::VDIVSSrm:
7133 case X86::VDIVSSrm_Int:
7134 case X86::VDIVSSrr:
7135 case X86::VDIVSSrr_Int:
7136 case X86::VSQRTPDm:
7137 case X86::VSQRTPDr:
7138 case X86::VSQRTPSm:
7139 case X86::VSQRTPSr:
7140 case X86::VSQRTSDm:
7141 case X86::VSQRTSDm_Int:
7142 case X86::VSQRTSDr:
7143 case X86::VSQRTSSm:
7144 case X86::VSQRTSSm_Int:
7145 case X86::VSQRTSSr:
7146 case X86::VSQRTPDZm:
7147 case X86::VSQRTPDZr:
7148 case X86::VSQRTPSZm:
7149 case X86::VSQRTPSZr:
7150 case X86::VSQRTSDZm:
7151 case X86::VSQRTSDZm_Int:
7152 case X86::VSQRTSDZr:
7153 case X86::VSQRTSSZm_Int:
7154 case X86::VSQRTSSZr:
7155 case X86::VSQRTSSZm:
7156 case X86::VDIVSDZrm:
7157 case X86::VDIVSDZrr:
7158 case X86::VDIVSSZrm:
7159 case X86::VDIVSSZrr:
7160
7161 case X86::VGATHERQPSZrm:
7162 case X86::VGATHERQPDZrm:
7163 case X86::VGATHERDPDZrm:
7164 case X86::VGATHERDPSZrm:
7165 case X86::VPGATHERQDZrm:
7166 case X86::VPGATHERQQZrm:
7167 case X86::VPGATHERDDZrm:
7168 case X86::VPGATHERDQZrm:
7169 case X86::VSCATTERQPDZmr:
7170 case X86::VSCATTERQPSZmr:
7171 case X86::VSCATTERDPDZmr:
7172 case X86::VSCATTERDPSZmr:
7173 case X86::VPSCATTERQDZmr:
7174 case X86::VPSCATTERQQZmr:
7175 case X86::VPSCATTERDDZmr:
7176 case X86::VPSCATTERDQZmr:
7177 return true;
7178 }
7179 }
7180
hasHighOperandLatency(const TargetSchedModel & SchedModel,const MachineRegisterInfo * MRI,const MachineInstr & DefMI,unsigned DefIdx,const MachineInstr & UseMI,unsigned UseIdx) const7181 bool X86InstrInfo::hasHighOperandLatency(const TargetSchedModel &SchedModel,
7182 const MachineRegisterInfo *MRI,
7183 const MachineInstr &DefMI,
7184 unsigned DefIdx,
7185 const MachineInstr &UseMI,
7186 unsigned UseIdx) const {
7187 return isHighLatencyDef(DefMI.getOpcode());
7188 }
7189
hasReassociableOperands(const MachineInstr & Inst,const MachineBasicBlock * MBB) const7190 bool X86InstrInfo::hasReassociableOperands(const MachineInstr &Inst,
7191 const MachineBasicBlock *MBB) const {
7192 assert((Inst.getNumOperands() == 3 || Inst.getNumOperands() == 4) &&
7193 "Reassociation needs binary operators");
7194
7195 // Integer binary math/logic instructions have a third source operand:
7196 // the EFLAGS register. That operand must be both defined here and never
7197 // used; ie, it must be dead. If the EFLAGS operand is live, then we can
7198 // not change anything because rearranging the operands could affect other
7199 // instructions that depend on the exact status flags (zero, sign, etc.)
7200 // that are set by using these particular operands with this operation.
7201 if (Inst.getNumOperands() == 4) {
7202 assert(Inst.getOperand(3).isReg() &&
7203 Inst.getOperand(3).getReg() == X86::EFLAGS &&
7204 "Unexpected operand in reassociable instruction");
7205 if (!Inst.getOperand(3).isDead())
7206 return false;
7207 }
7208
7209 return TargetInstrInfo::hasReassociableOperands(Inst, MBB);
7210 }
7211
7212 // TODO: There are many more machine instruction opcodes to match:
7213 // 1. Other data types (integer, vectors)
7214 // 2. Other math / logic operations (xor, or)
7215 // 3. Other forms of the same operation (intrinsics and other variants)
isAssociativeAndCommutative(const MachineInstr & Inst) const7216 bool X86InstrInfo::isAssociativeAndCommutative(const MachineInstr &Inst) const {
7217 switch (Inst.getOpcode()) {
7218 case X86::AND8rr:
7219 case X86::AND16rr:
7220 case X86::AND32rr:
7221 case X86::AND64rr:
7222 case X86::OR8rr:
7223 case X86::OR16rr:
7224 case X86::OR32rr:
7225 case X86::OR64rr:
7226 case X86::XOR8rr:
7227 case X86::XOR16rr:
7228 case X86::XOR32rr:
7229 case X86::XOR64rr:
7230 case X86::IMUL16rr:
7231 case X86::IMUL32rr:
7232 case X86::IMUL64rr:
7233 case X86::PANDrr:
7234 case X86::PORrr:
7235 case X86::PXORrr:
7236 case X86::VPANDrr:
7237 case X86::VPANDYrr:
7238 case X86::VPORrr:
7239 case X86::VPORYrr:
7240 case X86::VPXORrr:
7241 case X86::VPXORYrr:
7242 // Normal min/max instructions are not commutative because of NaN and signed
7243 // zero semantics, but these are. Thus, there's no need to check for global
7244 // relaxed math; the instructions themselves have the properties we need.
7245 case X86::MAXCPDrr:
7246 case X86::MAXCPSrr:
7247 case X86::MAXCSDrr:
7248 case X86::MAXCSSrr:
7249 case X86::MINCPDrr:
7250 case X86::MINCPSrr:
7251 case X86::MINCSDrr:
7252 case X86::MINCSSrr:
7253 case X86::VMAXCPDrr:
7254 case X86::VMAXCPSrr:
7255 case X86::VMAXCPDYrr:
7256 case X86::VMAXCPSYrr:
7257 case X86::VMAXCSDrr:
7258 case X86::VMAXCSSrr:
7259 case X86::VMINCPDrr:
7260 case X86::VMINCPSrr:
7261 case X86::VMINCPDYrr:
7262 case X86::VMINCPSYrr:
7263 case X86::VMINCSDrr:
7264 case X86::VMINCSSrr:
7265 return true;
7266 case X86::ADDPDrr:
7267 case X86::ADDPSrr:
7268 case X86::ADDSDrr:
7269 case X86::ADDSSrr:
7270 case X86::MULPDrr:
7271 case X86::MULPSrr:
7272 case X86::MULSDrr:
7273 case X86::MULSSrr:
7274 case X86::VADDPDrr:
7275 case X86::VADDPSrr:
7276 case X86::VADDPDYrr:
7277 case X86::VADDPSYrr:
7278 case X86::VADDSDrr:
7279 case X86::VADDSSrr:
7280 case X86::VMULPDrr:
7281 case X86::VMULPSrr:
7282 case X86::VMULPDYrr:
7283 case X86::VMULPSYrr:
7284 case X86::VMULSDrr:
7285 case X86::VMULSSrr:
7286 return Inst.getParent()->getParent()->getTarget().Options.UnsafeFPMath;
7287 default:
7288 return false;
7289 }
7290 }
7291
7292 /// This is an architecture-specific helper function of reassociateOps.
7293 /// Set special operand attributes for new instructions after reassociation.
setSpecialOperandAttr(MachineInstr & OldMI1,MachineInstr & OldMI2,MachineInstr & NewMI1,MachineInstr & NewMI2) const7294 void X86InstrInfo::setSpecialOperandAttr(MachineInstr &OldMI1,
7295 MachineInstr &OldMI2,
7296 MachineInstr &NewMI1,
7297 MachineInstr &NewMI2) const {
7298 // Integer instructions define an implicit EFLAGS source register operand as
7299 // the third source (fourth total) operand.
7300 if (OldMI1.getNumOperands() != 4 || OldMI2.getNumOperands() != 4)
7301 return;
7302
7303 assert(NewMI1.getNumOperands() == 4 && NewMI2.getNumOperands() == 4 &&
7304 "Unexpected instruction type for reassociation");
7305
7306 MachineOperand &OldOp1 = OldMI1.getOperand(3);
7307 MachineOperand &OldOp2 = OldMI2.getOperand(3);
7308 MachineOperand &NewOp1 = NewMI1.getOperand(3);
7309 MachineOperand &NewOp2 = NewMI2.getOperand(3);
7310
7311 assert(OldOp1.isReg() && OldOp1.getReg() == X86::EFLAGS && OldOp1.isDead() &&
7312 "Must have dead EFLAGS operand in reassociable instruction");
7313 assert(OldOp2.isReg() && OldOp2.getReg() == X86::EFLAGS && OldOp2.isDead() &&
7314 "Must have dead EFLAGS operand in reassociable instruction");
7315
7316 (void)OldOp1;
7317 (void)OldOp2;
7318
7319 assert(NewOp1.isReg() && NewOp1.getReg() == X86::EFLAGS &&
7320 "Unexpected operand in reassociable instruction");
7321 assert(NewOp2.isReg() && NewOp2.getReg() == X86::EFLAGS &&
7322 "Unexpected operand in reassociable instruction");
7323
7324 // Mark the new EFLAGS operands as dead to be helpful to subsequent iterations
7325 // of this pass or other passes. The EFLAGS operands must be dead in these new
7326 // instructions because the EFLAGS operands in the original instructions must
7327 // be dead in order for reassociation to occur.
7328 NewOp1.setIsDead();
7329 NewOp2.setIsDead();
7330 }
7331
7332 std::pair<unsigned, unsigned>
decomposeMachineOperandsTargetFlags(unsigned TF) const7333 X86InstrInfo::decomposeMachineOperandsTargetFlags(unsigned TF) const {
7334 return std::make_pair(TF, 0u);
7335 }
7336
7337 ArrayRef<std::pair<unsigned, const char *>>
getSerializableDirectMachineOperandTargetFlags() const7338 X86InstrInfo::getSerializableDirectMachineOperandTargetFlags() const {
7339 using namespace X86II;
7340 static const std::pair<unsigned, const char *> TargetFlags[] = {
7341 {MO_GOT_ABSOLUTE_ADDRESS, "x86-got-absolute-address"},
7342 {MO_PIC_BASE_OFFSET, "x86-pic-base-offset"},
7343 {MO_GOT, "x86-got"},
7344 {MO_GOTOFF, "x86-gotoff"},
7345 {MO_GOTPCREL, "x86-gotpcrel"},
7346 {MO_PLT, "x86-plt"},
7347 {MO_TLSGD, "x86-tlsgd"},
7348 {MO_TLSLD, "x86-tlsld"},
7349 {MO_TLSLDM, "x86-tlsldm"},
7350 {MO_GOTTPOFF, "x86-gottpoff"},
7351 {MO_INDNTPOFF, "x86-indntpoff"},
7352 {MO_TPOFF, "x86-tpoff"},
7353 {MO_DTPOFF, "x86-dtpoff"},
7354 {MO_NTPOFF, "x86-ntpoff"},
7355 {MO_GOTNTPOFF, "x86-gotntpoff"},
7356 {MO_DLLIMPORT, "x86-dllimport"},
7357 {MO_DARWIN_NONLAZY, "x86-darwin-nonlazy"},
7358 {MO_DARWIN_NONLAZY_PIC_BASE, "x86-darwin-nonlazy-pic-base"},
7359 {MO_TLVP, "x86-tlvp"},
7360 {MO_TLVP_PIC_BASE, "x86-tlvp-pic-base"},
7361 {MO_SECREL, "x86-secrel"}};
7362 return makeArrayRef(TargetFlags);
7363 }
7364
7365 namespace {
7366 /// Create Global Base Reg pass. This initializes the PIC
7367 /// global base register for x86-32.
7368 struct CGBR : public MachineFunctionPass {
7369 static char ID;
CGBR__anone124e5060411::CGBR7370 CGBR() : MachineFunctionPass(ID) {}
7371
runOnMachineFunction__anone124e5060411::CGBR7372 bool runOnMachineFunction(MachineFunction &MF) override {
7373 const X86TargetMachine *TM =
7374 static_cast<const X86TargetMachine *>(&MF.getTarget());
7375 const X86Subtarget &STI = MF.getSubtarget<X86Subtarget>();
7376
7377 // Don't do anything if this is 64-bit as 64-bit PIC
7378 // uses RIP relative addressing.
7379 if (STI.is64Bit())
7380 return false;
7381
7382 // Only emit a global base reg in PIC mode.
7383 if (!TM->isPositionIndependent())
7384 return false;
7385
7386 X86MachineFunctionInfo *X86FI = MF.getInfo<X86MachineFunctionInfo>();
7387 unsigned GlobalBaseReg = X86FI->getGlobalBaseReg();
7388
7389 // If we didn't need a GlobalBaseReg, don't insert code.
7390 if (GlobalBaseReg == 0)
7391 return false;
7392
7393 // Insert the set of GlobalBaseReg into the first MBB of the function
7394 MachineBasicBlock &FirstMBB = MF.front();
7395 MachineBasicBlock::iterator MBBI = FirstMBB.begin();
7396 DebugLoc DL = FirstMBB.findDebugLoc(MBBI);
7397 MachineRegisterInfo &RegInfo = MF.getRegInfo();
7398 const X86InstrInfo *TII = STI.getInstrInfo();
7399
7400 unsigned PC;
7401 if (STI.isPICStyleGOT())
7402 PC = RegInfo.createVirtualRegister(&X86::GR32RegClass);
7403 else
7404 PC = GlobalBaseReg;
7405
7406 // Operand of MovePCtoStack is completely ignored by asm printer. It's
7407 // only used in JIT code emission as displacement to pc.
7408 BuildMI(FirstMBB, MBBI, DL, TII->get(X86::MOVPC32r), PC).addImm(0);
7409
7410 // If we're using vanilla 'GOT' PIC style, we should use relative addressing
7411 // not to pc, but to _GLOBAL_OFFSET_TABLE_ external.
7412 if (STI.isPICStyleGOT()) {
7413 // Generate addl $__GLOBAL_OFFSET_TABLE_ + [.-piclabel], %some_register
7414 BuildMI(FirstMBB, MBBI, DL, TII->get(X86::ADD32ri), GlobalBaseReg)
7415 .addReg(PC).addExternalSymbol("_GLOBAL_OFFSET_TABLE_",
7416 X86II::MO_GOT_ABSOLUTE_ADDRESS);
7417 }
7418
7419 return true;
7420 }
7421
getPassName__anone124e5060411::CGBR7422 const char *getPassName() const override {
7423 return "X86 PIC Global Base Reg Initialization";
7424 }
7425
getAnalysisUsage__anone124e5060411::CGBR7426 void getAnalysisUsage(AnalysisUsage &AU) const override {
7427 AU.setPreservesCFG();
7428 MachineFunctionPass::getAnalysisUsage(AU);
7429 }
7430 };
7431 }
7432
7433 char CGBR::ID = 0;
7434 FunctionPass*
createX86GlobalBaseRegPass()7435 llvm::createX86GlobalBaseRegPass() { return new CGBR(); }
7436
7437 namespace {
7438 struct LDTLSCleanup : public MachineFunctionPass {
7439 static char ID;
LDTLSCleanup__anone124e5060511::LDTLSCleanup7440 LDTLSCleanup() : MachineFunctionPass(ID) {}
7441
runOnMachineFunction__anone124e5060511::LDTLSCleanup7442 bool runOnMachineFunction(MachineFunction &MF) override {
7443 if (skipFunction(*MF.getFunction()))
7444 return false;
7445
7446 X86MachineFunctionInfo *MFI = MF.getInfo<X86MachineFunctionInfo>();
7447 if (MFI->getNumLocalDynamicTLSAccesses() < 2) {
7448 // No point folding accesses if there isn't at least two.
7449 return false;
7450 }
7451
7452 MachineDominatorTree *DT = &getAnalysis<MachineDominatorTree>();
7453 return VisitNode(DT->getRootNode(), 0);
7454 }
7455
7456 // Visit the dominator subtree rooted at Node in pre-order.
7457 // If TLSBaseAddrReg is non-null, then use that to replace any
7458 // TLS_base_addr instructions. Otherwise, create the register
7459 // when the first such instruction is seen, and then use it
7460 // as we encounter more instructions.
VisitNode__anone124e5060511::LDTLSCleanup7461 bool VisitNode(MachineDomTreeNode *Node, unsigned TLSBaseAddrReg) {
7462 MachineBasicBlock *BB = Node->getBlock();
7463 bool Changed = false;
7464
7465 // Traverse the current block.
7466 for (MachineBasicBlock::iterator I = BB->begin(), E = BB->end(); I != E;
7467 ++I) {
7468 switch (I->getOpcode()) {
7469 case X86::TLS_base_addr32:
7470 case X86::TLS_base_addr64:
7471 if (TLSBaseAddrReg)
7472 I = ReplaceTLSBaseAddrCall(*I, TLSBaseAddrReg);
7473 else
7474 I = SetRegister(*I, &TLSBaseAddrReg);
7475 Changed = true;
7476 break;
7477 default:
7478 break;
7479 }
7480 }
7481
7482 // Visit the children of this block in the dominator tree.
7483 for (MachineDomTreeNode::iterator I = Node->begin(), E = Node->end();
7484 I != E; ++I) {
7485 Changed |= VisitNode(*I, TLSBaseAddrReg);
7486 }
7487
7488 return Changed;
7489 }
7490
7491 // Replace the TLS_base_addr instruction I with a copy from
7492 // TLSBaseAddrReg, returning the new instruction.
ReplaceTLSBaseAddrCall__anone124e5060511::LDTLSCleanup7493 MachineInstr *ReplaceTLSBaseAddrCall(MachineInstr &I,
7494 unsigned TLSBaseAddrReg) {
7495 MachineFunction *MF = I.getParent()->getParent();
7496 const X86Subtarget &STI = MF->getSubtarget<X86Subtarget>();
7497 const bool is64Bit = STI.is64Bit();
7498 const X86InstrInfo *TII = STI.getInstrInfo();
7499
7500 // Insert a Copy from TLSBaseAddrReg to RAX/EAX.
7501 MachineInstr *Copy =
7502 BuildMI(*I.getParent(), I, I.getDebugLoc(),
7503 TII->get(TargetOpcode::COPY), is64Bit ? X86::RAX : X86::EAX)
7504 .addReg(TLSBaseAddrReg);
7505
7506 // Erase the TLS_base_addr instruction.
7507 I.eraseFromParent();
7508
7509 return Copy;
7510 }
7511
7512 // Create a virtal register in *TLSBaseAddrReg, and populate it by
7513 // inserting a copy instruction after I. Returns the new instruction.
SetRegister__anone124e5060511::LDTLSCleanup7514 MachineInstr *SetRegister(MachineInstr &I, unsigned *TLSBaseAddrReg) {
7515 MachineFunction *MF = I.getParent()->getParent();
7516 const X86Subtarget &STI = MF->getSubtarget<X86Subtarget>();
7517 const bool is64Bit = STI.is64Bit();
7518 const X86InstrInfo *TII = STI.getInstrInfo();
7519
7520 // Create a virtual register for the TLS base address.
7521 MachineRegisterInfo &RegInfo = MF->getRegInfo();
7522 *TLSBaseAddrReg = RegInfo.createVirtualRegister(is64Bit
7523 ? &X86::GR64RegClass
7524 : &X86::GR32RegClass);
7525
7526 // Insert a copy from RAX/EAX to TLSBaseAddrReg.
7527 MachineInstr *Next = I.getNextNode();
7528 MachineInstr *Copy =
7529 BuildMI(*I.getParent(), Next, I.getDebugLoc(),
7530 TII->get(TargetOpcode::COPY), *TLSBaseAddrReg)
7531 .addReg(is64Bit ? X86::RAX : X86::EAX);
7532
7533 return Copy;
7534 }
7535
getPassName__anone124e5060511::LDTLSCleanup7536 const char *getPassName() const override {
7537 return "Local Dynamic TLS Access Clean-up";
7538 }
7539
getAnalysisUsage__anone124e5060511::LDTLSCleanup7540 void getAnalysisUsage(AnalysisUsage &AU) const override {
7541 AU.setPreservesCFG();
7542 AU.addRequired<MachineDominatorTree>();
7543 MachineFunctionPass::getAnalysisUsage(AU);
7544 }
7545 };
7546 }
7547
7548 char LDTLSCleanup::ID = 0;
7549 FunctionPass*
createCleanupLocalDynamicTLSPass()7550 llvm::createCleanupLocalDynamicTLSPass() { return new LDTLSCleanup(); }
7551