| /external/llvm-project/llvm/lib/Target/RISCV/ |
| D | RISCVExpandAtomicPseudoInsts.cpp | 223 Register AddrReg = MI.getOperand(2).getReg(); in doAtomicBinOpExpansion() local
285 Register AddrReg = MI.getOperand(2).getReg(); in doMaskedAtomicBinOpExpansion() local
425 Register AddrReg = MI.getOperand(3).getReg(); in expandAtomicMinMaxOp() local
537 Register AddrReg = MI.getOperand(2).getReg(); in expandAtomicCmpXchg() local
|
| /external/llvm-project/llvm/lib/Target/Mips/MCTargetDesc/ |
| D | MipsNaClELFStreamer.cpp | 101 void emitMask(unsigned AddrReg, unsigned MaskReg, in emitMask()
114 unsigned AddrReg = MI.getOperand(0).getReg(); in sandboxIndirectJump() local
|
| /external/llvm/lib/Target/Mips/MCTargetDesc/ |
| D | MipsNaClELFStreamer.cpp | 93 void emitMask(unsigned AddrReg, unsigned MaskReg, in emitMask()
106 unsigned AddrReg = MI.getOperand(0).getReg(); in sandboxIndirectJump() local
|
| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Mips/MCTargetDesc/ |
| D | MipsNaClELFStreamer.cpp | 101 void emitMask(unsigned AddrReg, unsigned MaskReg, in emitMask()
114 unsigned AddrReg = MI.getOperand(0).getReg(); in sandboxIndirectJump() local
|
| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/RISCV/ |
| D | RISCVExpandPseudoInsts.cpp | 240 Register AddrReg = MI.getOperand(2).getReg(); in doAtomicBinOpExpansion() local
302 Register AddrReg = MI.getOperand(2).getReg(); in doMaskedAtomicBinOpExpansion() local
442 Register AddrReg = MI.getOperand(3).getReg(); in expandAtomicMinMaxOp() local
554 Register AddrReg = MI.getOperand(2).getReg(); in expandAtomicCmpXchg() local
|
| /external/llvm-project/llvm/lib/Target/ARC/ |
| D | ARCExpandPseudos.cpp | 62 unsigned AddrReg = MF.getRegInfo().createVirtualRegister(&ARC::GPR32RegClass); in ExpandStore() local
|
| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARC/ |
| D | ARCExpandPseudos.cpp | 62 unsigned AddrReg = MF.getRegInfo().createVirtualRegister(&ARC::GPR32RegClass); in ExpandStore() local
|
| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/ |
| D | AArch64ExpandPseudoInsts.cpp | 186 Register AddrReg = MI.getOperand(2).getReg(); in expandCMP_SWAP() local
266 Register AddrReg = MI.getOperand(3).getReg(); in expandCMP_SWAP_128() local
|
| D | AArch64CallLowering.cpp | 65 Register AddrReg = MRI.createGenericVirtualRegister(LLT::pointer(0, 64)); in getStackAddress() local
162 Register AddrReg = MRI.createGenericVirtualRegister(p0); in getStackAddress() local
|
| D | AArch64SIMDInstrOpt.cpp | 504 unsigned SeqReg, AddrReg; in optimizeLdStInterleave() local
|
| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/X86/ |
| D | X86CallLowering.cpp | 117 Register AddrReg = MRI.createGenericVirtualRegister(p0); in getStackAddress() local
243 Register AddrReg = MRI.createGenericVirtualRegister( in getStackAddress() local
|
| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/ |
| D | ARMCallLowering.cpp | 108 Register AddrReg = MRI.createGenericVirtualRegister(p0); in getStackAddress() local
302 Register AddrReg = in getStackAddress() local
|
| D | ARMExpandPseudoInsts.cpp | 940 Register AddrReg = MI.getOperand(2).getReg(); in ExpandCMP_SWAP() local
1059 Register AddrReg = MI.getOperand(2).getReg(); in ExpandCMP_SWAP_64() local
|
| /external/llvm-project/llvm/lib/Target/AArch64/ |
| D | AArch64ExpandPseudoInsts.cpp | 191 Register AddrReg = MI.getOperand(2).getReg(); in expandCMP_SWAP() local
271 Register AddrReg = MI.getOperand(3).getReg(); in expandCMP_SWAP_128() local
|
| D | AArch64SIMDInstrOpt.cpp | 507 unsigned SeqReg, AddrReg; in optimizeLdStInterleave() local
|
| /external/llvm/lib/Target/AMDGPU/ |
| D | SILoadStoreOptimizer.cpp | 200 const MachineOperand *AddrReg = TII->getNamedOperand(*I, AMDGPU::OpName::addr); in mergeRead2Pair() local
|
| D | SIInstrInfo.cpp | 215 const MachineOperand *AddrReg = in getMemOpBaseRegImmOfs() local
250 const MachineOperand *AddrReg = in getMemOpBaseRegImmOfs() local
264 const MachineOperand *AddrReg = in getMemOpBaseRegImmOfs() local
290 const MachineOperand *AddrReg = getNamedOperand(LdSt, AMDGPU::OpName::addr); in getMemOpBaseRegImmOfs() local
|
| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Mips/ |
| D | MipsCallLowering.cpp | 195 Register AddrReg = MRI.createGenericVirtualRegister(LLT::pointer(0, 32)); in getStackAddress() local
301 Register AddrReg = MRI.createGenericVirtualRegister(p0); in getStackAddress() local
|
| /external/llvm-project/llvm/lib/Target/AArch64/GISel/ |
| D | AArch64CallLowering.cpp | 65 auto AddrReg = MIRBuilder.buildFrameIndex(LLT::pointer(0, 64), FI); in getStackAddress() local
160 auto AddrReg = MIRBuilder.buildPtrAdd(p0, SPReg, OffsetReg); in getStackAddress() local
|
| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/ |
| D | SILoadStoreOptimizer.cpp | 131 const MachineOperand *AddrReg[5]; member
958 const auto *AddrReg = TII->getNamedOperand(*CI.I, AMDGPU::OpName::addr); in mergeRead2Pair() local
1057 const MachineOperand *AddrReg = in mergeWrite2Pair() local
|
| D | R600InstrInfo.cpp | 1125 unsigned AddrReg; in buildIndirectWrite() local
1157 unsigned AddrReg; in buildIndirectRead() local
|
| /external/llvm-project/llvm/lib/Target/X86/ |
| D | X86CallLowering.cpp | 115 auto AddrReg = MIRBuilder.buildPtrAdd(p0, SPReg, OffsetReg); in getStackAddress() local
|
| /external/llvm-project/llvm/lib/Target/AMDGPU/ |
| D | SILoadStoreOptimizer.cpp | 134 const MachineOperand *AddrReg[MaxAddressRegs]; member
1015 const auto *AddrReg = TII->getNamedOperand(*CI.I, AMDGPU::OpName::addr); in mergeRead2Pair() local
1115 const MachineOperand *AddrReg = in mergeWrite2Pair() local
|
| D | AMDGPUCallLowering.cpp | 113 auto AddrReg = MIRBuilder.buildFrameIndex( in getStackAddress() local
226 auto AddrReg = MIRBuilder.buildPtrAdd(PtrTy, SPReg, OffsetReg); in getStackAddress() local
|
| /external/llvm-project/llvm/lib/Target/ARM/ |
| D | ARMCallLowering.cpp | 105 auto AddrReg = MIRBuilder.buildPtrAdd(p0, SPReg, OffsetReg); in getStackAddress() local
|