| /external/vixl/benchmarks/aarch64/ |
| D | bench-utils.cc | 196 __ Asr(PickR(size), PickR(size), 4); in GenerateTrivialSequence() local
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| /external/vixl/test/aarch64/ |
| D | test-assembler-aarch64.cc | 6280 __ Asr(x16, x0, x1); in TEST() local
6281 __ Asr(x17, x0, x2); in TEST() local
6282 __ Asr(x18, x0, x3); in TEST() local
6283 __ Asr(x19, x0, x4); in TEST() local
6284 __ Asr(x20, x0, x5); in TEST() local
6285 __ Asr(x21, x0, x6); in TEST() local
6287 __ Asr(w22, w0, w1); in TEST() local
6288 __ Asr(w23, w0, w2); in TEST() local
6289 __ Asr(w24, w0, w3); in TEST() local
6290 __ Asr(w25, w0, w4); in TEST() local
[all …]
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| D | test-assembler-sve-aarch64.cc | 12754 __ Asr(zd_asr, zn, shift); in BitwiseShiftImmHelper() local
13051 __ Asr(z4.VnB(), p0.Merging(), z31.VnB(), z1.VnB()); in TEST_SVE() local
13057 __ Asr(z7.VnH(), p0.Merging(), z31.VnH(), z1.VnH()); in TEST_SVE() local
13063 __ Asr(z10.VnS(), p4.Merging(), z31.VnS(), z1.VnS()); in TEST_SVE() local
13068 __ Asr(z13.VnD(), p0.Merging(), z31.VnD(), z1.VnD()); in TEST_SVE() local
13126 __ Asr(z4.VnB(), p0.Merging(), z31.VnB(), z1.VnD()); in TEST_SVE() local
13131 __ Asr(z7.VnH(), p0.Merging(), z31.VnH(), z1.VnD()); in TEST_SVE() local
13136 __ Asr(z10.VnS(), p4.Merging(), z31.VnS(), z1.VnD()); in TEST_SVE() local
13178 __ Asr(z2.VnB(), p0.Merging(), z1.VnB(), 2); in TEST_SVE() local
13183 __ Asr(z5.VnH(), p0.Merging(), z4.VnH(), 3); in TEST_SVE() local
[all …]
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| /external/vixl/src/aarch64/ |
| D | macro-assembler-aarch64.h | 1075 void Asr(const Register& rd, const Register& rn, unsigned shift) { in Asr() function
1082 void Asr(const Register& rd, const Register& rn, const Register& rm) { in Asr() function
3534 void Asr(const ZRegister& zd, in Asr() function
3546 void Asr(const ZRegister& zd, const ZRegister& zn, int shift) { in Asr() function
3551 void Asr(const ZRegister& zd, const ZRegister& zn, const ZRegister& zm) { in Asr() function
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| D | macro-assembler-sve-aarch64.cc | 565 void MacroAssembler::Asr(const ZRegister& zd, in Asr() function in vixl::aarch64::MacroAssembler
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| /external/swiftshader/third_party/subzero/src/ |
| D | IceInstARM32.h | 384 Asr, enumerator
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| /external/vixl/test/aarch32/ |
| D | test-assembler-aarch32.cc | 785 __ Asr(r5, r1, 16); in TEST() local
813 __ Asr(r5, r1, r9); in TEST() local
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| /external/vixl/src/aarch32/ |
| D | macro-assembler-aarch32.h | 1232 void Asr(Condition cond, Register rd, Register rm, const Operand& operand) { in Asr() function
1249 void Asr(Register rd, Register rm, const Operand& operand) { in Asr() function
1252 void Asr(FlagsUpdate flags, in Asr() function
1278 void Asr(FlagsUpdate flags, in Asr() function
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