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1VIXL Supported Instruction List
2===============================
3
4This is a list of the AArch64 instructions supported by the VIXL assembler,
5disassembler and simulator. The simulator may not support all floating point
6operations to the precision required by AArch64 - please check the simulator
7source code for details.
8
9AArch64 integer instructions
10----------------------------
11
12### ADC ###
13
14Add with carry bit.
15
16    void adc(const Register& rd, const Register& rn, const Operand& operand)
17
18
19### ADCS ###
20
21Add with carry bit and update status flags.
22
23    void adcs(const Register& rd, const Register& rn, const Operand& operand)
24
25
26### ADD ###
27
28Add.
29
30    void add(const Register& rd, const Register& rn, const Operand& operand)
31
32
33### ADDS ###
34
35Add and update status flags.
36
37    void adds(const Register& rd, const Register& rn, const Operand& operand)
38
39
40### ADR ###
41
42Calculate the address of a PC offset.
43
44    void adr(const Register& xd, int64_t imm21)
45
46
47### ADR ###
48
49Calculate the address of a label.
50
51    void adr(const Register& xd, Label* label)
52
53
54### ADRP ###
55
56Calculate the page address of a PC offset.
57
58    void adrp(const Register& xd, int64_t imm21)
59
60
61### ADRP ###
62
63Calculate the page address of a label.
64
65    void adrp(const Register& xd, Label* label)
66
67
68### AND ###
69
70Bitwise and (A & B).
71
72    void and_(const Register& rd, const Register& rn, const Operand& operand)
73
74
75### ANDS ###
76
77Bitwise and (A & B) and update status flags.
78
79    void ands(const Register& rd, const Register& rn, const Operand& operand)
80
81
82### ASR ###
83
84Arithmetic shift right.
85
86    void asr(const Register& rd, const Register& rn, unsigned shift)
87
88
89### ASRV ###
90
91Arithmetic shift right by variable.
92
93    void asrv(const Register& rd, const Register& rn, const Register& rm)
94
95
96### AUTDA ###
97
98Authenticate Data address, using key A _(Armv8.3)_.
99
100    void autda(const Register& xd, const Register& xn)
101
102
103### AUTDA1716 ###
104
105Authenticate Data address, using key A, with address in x17 and modifier in x16 _(Armv8.3)_.
106
107    void autda1716()
108
109
110### AUTDASP ###
111
112Authenticate Data address, using key A, with address in LR and modifier in SP _(Armv8.3)_.
113
114    void autdasp()
115
116
117### AUTDAZ ###
118
119Authenticate Data address, using key A, with address in LR and a modifier of zero _(Armv8.3)_.
120
121    void autdaz()
122
123
124### AUTDB ###
125
126Authenticate Data address, using key B _(Armv8.3)_.
127
128    void autdb(const Register& xd, const Register& xn)
129
130
131### AUTDB1716 ###
132
133Authenticate Data address, using key B, with address in x17 and modifier in x16 _(Armv8.3)_.
134
135    void autdb1716()
136
137
138### AUTDBSP ###
139
140Authenticate Data address, using key B, with address in LR and modifier in SP _(Armv8.3)_.
141
142    void autdbsp()
143
144
145### AUTDBZ ###
146
147Authenticate Data address, using key B, with address in LR and a modifier of zero _(Armv8.3)_.
148
149    void autdbz()
150
151
152### AUTDZA ###
153
154Authenticate Data address, using key A and a modifier of zero _(Armv8.3)_.
155
156    void autdza(const Register& xd)
157
158
159### AUTDZB ###
160
161Authenticate Data address, using key B and a modifier of zero _(Armv8.3)_.
162
163    void autdzb(const Register& xd)
164
165
166### AUTIA ###
167
168Authenticate Instruction address, using key A _(Armv8.3)_.
169
170    void autia(const Register& xd, const Register& xn)
171
172
173### AUTIA1716 ###
174
175Authenticate Instruction address, using key A, with address in x17 and modifier in x16 _(Armv8.3)_.
176
177    void autia1716()
178
179
180### AUTIASP ###
181
182Authenticate Instruction address, using key A, with address in LR and modifier in SP _(Armv8.3)_.
183
184    void autiasp()
185
186
187### AUTIAZ ###
188
189Authenticate Instruction address, using key A, with address in LR and a modifier of zero _(Armv8.3)_.
190
191    void autiaz()
192
193
194### AUTIB ###
195
196Authenticate Instruction address, using key B _(Armv8.3)_.
197
198    void autib(const Register& xd, const Register& xn)
199
200
201### AUTIB1716 ###
202
203Authenticate Instruction address, using key B, with address in x17 and modifier in x16 _(Armv8.3)_.
204
205    void autib1716()
206
207
208### AUTIBSP ###
209
210Authenticate Instruction address, using key B, with address in LR and modifier in SP _(Armv8.3)_.
211
212    void autibsp()
213
214
215### AUTIBZ ###
216
217Authenticate Instruction address, using key B, with address in LR and a modifier of zero _(Armv8.3)_.
218
219    void autibz()
220
221
222### AUTIZA ###
223
224Authenticate Instruction address, using key A and a modifier of zero _(Armv8.3)_.
225
226    void autiza(const Register& xd)
227
228
229### AUTIZB ###
230
231Authenticate Instruction address, using key B and a modifier of zero _(Armv8.3)_.
232
233    void autizb(const Register& xd)
234
235
236### AXFLAG ###
237
238Convert floating-point condition flags from Arm format to alternative format _(Armv8.5)_.
239
240    void axflag()
241
242
243### B ###
244
245Conditional branch to PC offset.
246
247    void b(int64_t imm19, Condition cond)
248
249
250### B ###
251
252Conditional branch to label.
253
254    void b(Label* label, Condition cond)
255
256
257### B ###
258
259Unconditional branch to PC offset.
260
261    void b(int64_t imm26)
262
263
264### B ###
265
266Unconditional branch to label.
267
268    void b(Label* label)
269
270
271### BFC ###
272
273Bitfield clear _(Armv8.2)_.
274
275    void bfc(const Register& rd, unsigned lsb, unsigned width)
276
277
278### BFI ###
279
280Bitfield insert.
281
282    void bfi(const Register& rd,
283             const Register& rn,
284             unsigned lsb,
285             unsigned width)
286
287
288### BFM ###
289
290Bitfield move.
291
292    void bfm(const Register& rd,
293             const Register& rn,
294             unsigned immr,
295             unsigned imms)
296
297
298### BFXIL ###
299
300Bitfield extract and insert low.
301
302    void bfxil(const Register& rd,
303               const Register& rn,
304               unsigned lsb,
305               unsigned width)
306
307
308### BIC ###
309
310Bit clear (A & ~B).
311
312    void bic(const Register& rd, const Register& rn, const Operand& operand)
313
314
315### BICS ###
316
317Bit clear (A & ~B) and update status flags.
318
319    void bics(const Register& rd, const Register& rn, const Operand& operand)
320
321
322### BL ###
323
324Branch with link to PC offset.
325
326    void bl(int64_t imm26)
327
328
329### BL ###
330
331Branch with link to label.
332
333    void bl(Label* label)
334
335
336### BLR ###
337
338Branch with link to register.
339
340    void blr(const Register& xn)
341
342
343### BLRAA ###
344
345Branch with link to register, with pointer authentication. Using key A _(Armv8.3)_.
346
347    void blraa(const Register& xn, const Register& xm)
348
349
350### BLRAAZ ###
351
352Branch with link to register, with pointer authentication. Using key A and a modifier of zero _(Armv8.3)_.
353
354    void blraaz(const Register& xn)
355
356
357### BLRAB ###
358
359Branch with link to register, with pointer authentication. Using key B _(Armv8.3)_.
360
361    void blrab(const Register& xn, const Register& xm)
362
363
364### BLRABZ ###
365
366Branch with link to register, with pointer authentication. Using key B and a modifier of zero _(Armv8.3)_.
367
368    void blrabz(const Register& xn)
369
370
371### BR ###
372
373Branch to register.
374
375    void br(const Register& xn)
376
377
378### BRAA ###
379
380Branch to register, with pointer authentication. Using key A _(Armv8.3)_.
381
382    void braa(const Register& xn, const Register& xm)
383
384
385### BRAAZ ###
386
387Branch to register, with pointer authentication. Using key A and a modifier of zero _(Armv8.3)_.
388
389    void braaz(const Register& xn)
390
391
392### BRAB ###
393
394Branch to register, with pointer authentication. Using key B _(Armv8.3)_.
395
396    void brab(const Register& xn, const Register& xm)
397
398
399### BRABZ ###
400
401Branch to register, with pointer authentication. Using key B and a modifier of zero _(Armv8.3)_.
402
403    void brabz(const Register& xn)
404
405
406### BRK ###
407
408Monitor debug-mode breakpoint.
409
410    void brk(int code)
411
412
413### BTI ###
414
415Branch target identification.
416
417    void bti(BranchTargetIdentifier id)
418
419
420### CAS ###
421
422Compare and Swap word or doubleword in memory _(Armv8.1)_.
423
424    void cas(const Register& rs, const Register& rt, const MemOperand& src)
425
426
427### CASA ###
428
429Compare and Swap word or doubleword in memory _(Armv8.1)_.
430
431    void casa(const Register& rs, const Register& rt, const MemOperand& src)
432
433
434### CASAB ###
435
436Compare and Swap byte in memory _(Armv8.1)_.
437
438    void casab(const Register& rs, const Register& rt, const MemOperand& src)
439
440
441### CASAH ###
442
443Compare and Swap halfword in memory _(Armv8.1)_.
444
445    void casah(const Register& rs, const Register& rt, const MemOperand& src)
446
447
448### CASAL ###
449
450Compare and Swap word or doubleword in memory _(Armv8.1)_.
451
452    void casal(const Register& rs, const Register& rt, const MemOperand& src)
453
454
455### CASALB ###
456
457Compare and Swap byte in memory _(Armv8.1)_.
458
459    void casalb(const Register& rs, const Register& rt, const MemOperand& src)
460
461
462### CASALH ###
463
464Compare and Swap halfword in memory _(Armv8.1)_.
465
466    void casalh(const Register& rs, const Register& rt, const MemOperand& src)
467
468
469### CASB ###
470
471Compare and Swap byte in memory _(Armv8.1)_.
472
473    void casb(const Register& rs, const Register& rt, const MemOperand& src)
474
475
476### CASH ###
477
478Compare and Swap halfword in memory _(Armv8.1)_.
479
480    void cash(const Register& rs, const Register& rt, const MemOperand& src)
481
482
483### CASL ###
484
485Compare and Swap word or doubleword in memory _(Armv8.1)_.
486
487    void casl(const Register& rs, const Register& rt, const MemOperand& src)
488
489
490### CASLB ###
491
492Compare and Swap byte in memory _(Armv8.1)_.
493
494    void caslb(const Register& rs, const Register& rt, const MemOperand& src)
495
496
497### CASLH ###
498
499Compare and Swap halfword in memory _(Armv8.1)_.
500
501    void caslh(const Register& rs, const Register& rt, const MemOperand& src)
502
503
504### CASP ###
505
506Compare and Swap Pair of words or doublewords in memory _(Armv8.1)_.
507
508    void casp(const Register& rs,
509              const Register& rs2,
510              const Register& rt,
511              const Register& rt2,
512              const MemOperand& src)
513
514
515### CASPA ###
516
517Compare and Swap Pair of words or doublewords in memory _(Armv8.1)_.
518
519    void caspa(const Register& rs,
520               const Register& rs2,
521               const Register& rt,
522               const Register& rt2,
523               const MemOperand& src)
524
525
526### CASPAL ###
527
528Compare and Swap Pair of words or doublewords in memory _(Armv8.1)_.
529
530    void caspal(const Register& rs,
531                const Register& rs2,
532                const Register& rt,
533                const Register& rt2,
534                const MemOperand& src)
535
536
537### CASPL ###
538
539Compare and Swap Pair of words or doublewords in memory _(Armv8.1)_.
540
541    void caspl(const Register& rs,
542               const Register& rs2,
543               const Register& rt,
544               const Register& rt2,
545               const MemOperand& src)
546
547
548### CBNZ ###
549
550Compare and branch to PC offset if not zero.
551
552    void cbnz(const Register& rt, int64_t imm19)
553
554
555### CBNZ ###
556
557Compare and branch to label if not zero.
558
559    void cbnz(const Register& rt, Label* label)
560
561
562### CBZ ###
563
564Compare and branch to PC offset if zero.
565
566    void cbz(const Register& rt, int64_t imm19)
567
568
569### CBZ ###
570
571Compare and branch to label if zero.
572
573    void cbz(const Register& rt, Label* label)
574
575
576### CCMN ###
577
578Conditional compare negative.
579
580    void ccmn(const Register& rn,
581              const Operand& operand,
582              StatusFlags nzcv,
583              Condition cond)
584
585
586### CCMP ###
587
588Conditional compare.
589
590    void ccmp(const Register& rn,
591              const Operand& operand,
592              StatusFlags nzcv,
593              Condition cond)
594
595
596### CFINV ###
597
598Invert carry flag _(Armv8.4)_.
599
600    void cfinv()
601
602
603### CINC ###
604
605Conditional increment: rd = cond ? rn + 1 : rn.
606
607    void cinc(const Register& rd, const Register& rn, Condition cond)
608
609
610### CINV ###
611
612Conditional invert: rd = cond ? ~rn : rn.
613
614    void cinv(const Register& rd, const Register& rn, Condition cond)
615
616
617### CLREX ###
618
619Clear exclusive monitor.
620
621    void clrex(int imm4 = 0xf)
622
623
624### CLS ###
625
626Count leading sign bits.
627
628    void cls(const Register& rd, const Register& rn)
629
630
631### CLZ ###
632
633Count leading zeroes.
634
635    void clz(const Register& rd, const Register& rn)
636
637
638### CMN ###
639
640Compare negative.
641
642    void cmn(const Register& rn, const Operand& operand)
643
644
645### CMP ###
646
647Compare.
648
649    void cmp(const Register& rn, const Operand& operand)
650
651
652### CNEG ###
653
654Conditional negate: rd = cond ? -rn : rn.
655
656    void cneg(const Register& rd, const Register& rn, Condition cond)
657
658
659### CRC32B ###
660
661CRC-32 checksum from byte.
662
663    void crc32b(const Register& wd, const Register& wn, const Register& wm)
664
665
666### CRC32CB ###
667
668CRC-32 C checksum from byte.
669
670    void crc32cb(const Register& wd, const Register& wn, const Register& wm)
671
672
673### CRC32CH ###
674
675CRC-32 C checksum from half-word.
676
677    void crc32ch(const Register& wd, const Register& wn, const Register& wm)
678
679
680### CRC32CW ###
681
682CRC-32 C checksum from word.
683
684    void crc32cw(const Register& wd, const Register& wn, const Register& wm)
685
686
687### CRC32CX ###
688
689CRC-32C checksum from double word.
690
691    void crc32cx(const Register& wd, const Register& wn, const Register& xm)
692
693
694### CRC32H ###
695
696CRC-32 checksum from half-word.
697
698    void crc32h(const Register& wd, const Register& wn, const Register& wm)
699
700
701### CRC32W ###
702
703CRC-32 checksum from word.
704
705    void crc32w(const Register& wd, const Register& wn, const Register& wm)
706
707
708### CRC32X ###
709
710CRC-32 checksum from double word.
711
712    void crc32x(const Register& wd, const Register& wn, const Register& xm)
713
714
715### CSDB ###
716
717Conditional speculation dependency barrier.
718
719    void csdb()
720
721
722### CSEL ###
723
724Conditional select: rd = cond ? rn : rm.
725
726    void csel(const Register& rd,
727              const Register& rn,
728              const Register& rm,
729              Condition cond)
730
731
732### CSET ###
733
734Conditional set: rd = cond ? 1 : 0.
735
736    void cset(const Register& rd, Condition cond)
737
738
739### CSETM ###
740
741Conditional set mask: rd = cond ? -1 : 0.
742
743    void csetm(const Register& rd, Condition cond)
744
745
746### CSINC ###
747
748Conditional select increment: rd = cond ? rn : rm + 1.
749
750    void csinc(const Register& rd,
751               const Register& rn,
752               const Register& rm,
753               Condition cond)
754
755
756### CSINV ###
757
758Conditional select inversion: rd = cond ? rn : ~rm.
759
760    void csinv(const Register& rd,
761               const Register& rn,
762               const Register& rm,
763               Condition cond)
764
765
766### CSNEG ###
767
768Conditional select negation: rd = cond ? rn : -rm.
769
770    void csneg(const Register& rd,
771               const Register& rn,
772               const Register& rm,
773               Condition cond)
774
775
776### DC ###
777
778System data cache operation.
779
780    void dc(DataCacheOp op, const Register& rt)
781
782
783### DMB ###
784
785Data memory barrier.
786
787    void dmb(BarrierDomain domain, BarrierType type)
788
789
790### DSB ###
791
792Data synchronization barrier.
793
794    void dsb(BarrierDomain domain, BarrierType type)
795
796
797### EON ###
798
799Bitwise enor/xnor (A ^ ~B).
800
801    void eon(const Register& rd, const Register& rn, const Operand& operand)
802
803
804### EOR ###
805
806Bitwise eor/xor (A ^ B).
807
808    void eor(const Register& rd, const Register& rn, const Operand& operand)
809
810
811### ESB ###
812
813Error synchronization barrier.
814
815    void esb()
816
817
818### EXTR ###
819
820Extract.
821
822    void extr(const Register& rd,
823              const Register& rn,
824              const Register& rm,
825              unsigned lsb)
826
827
828### HINT ###
829
830System hint (named type).
831
832    void hint(SystemHint code)
833
834
835### HINT ###
836
837System hint (numbered type).
838
839    void hint(int imm7)
840
841
842### HLT ###
843
844Halting debug-mode breakpoint.
845
846    void hlt(int code)
847
848
849### IC ###
850
851System instruction cache operation.
852
853    void ic(InstructionCacheOp op, const Register& rt)
854
855
856### ISB ###
857
858Instruction synchronization barrier.
859
860    void isb()
861
862
863### LDADD ###
864
865Atomic add on word or doubleword in memory _(Armv8.1)_
866
867    void ldadd(const Register& rs, const Register& rt, const MemOperand& src)
868
869
870### LDADDA ###
871
872Atomic add on word or doubleword in memory, with Load-acquire semantics _(Armv8.1)_
873
874    void ldadda(const Register& rs, const Register& rt, const MemOperand& src)
875
876
877### LDADDAB ###
878
879Atomic add on byte in memory, with Load-acquire semantics _(Armv8.1)_
880
881    void ldaddab(const Register& rs, const Register& rt, const MemOperand& src)
882
883
884### LDADDAH ###
885
886Atomic add on halfword in memory, with Load-acquire semantics _(Armv8.1)_
887
888    void ldaddah(const Register& rs, const Register& rt, const MemOperand& src)
889
890
891### LDADDAL ###
892
893Atomic add on word or doubleword in memory, with Load-acquire and Store-release semantics _(Armv8.1)_
894
895    void ldaddal(const Register& rs, const Register& rt, const MemOperand& src)
896
897
898### LDADDALB ###
899
900Atomic add on byte in memory, with Load-acquire and Store-release semantics _(Armv8.1)_
901
902    void ldaddalb(const Register& rs, const Register& rt, const MemOperand& src)
903
904
905### LDADDALH ###
906
907Atomic add on halfword in memory, with Load-acquire and Store-release semantics _(Armv8.1)_
908
909    void ldaddalh(const Register& rs, const Register& rt, const MemOperand& src)
910
911
912### LDADDB ###
913
914Atomic add on byte in memory _(Armv8.1)_
915
916    void ldaddb(const Register& rs, const Register& rt, const MemOperand& src)
917
918
919### LDADDH ###
920
921Atomic add on halfword in memory _(Armv8.1)_
922
923    void ldaddh(const Register& rs, const Register& rt, const MemOperand& src)
924
925
926### LDADDL ###
927
928Atomic add on word or doubleword in memory, with Store-release semantics _(Armv8.1)_
929
930    void ldaddl(const Register& rs, const Register& rt, const MemOperand& src)
931
932
933### LDADDLB ###
934
935Atomic add on byte in memory, with Store-release semantics _(Armv8.1)_
936
937    void ldaddlb(const Register& rs, const Register& rt, const MemOperand& src)
938
939
940### LDADDLH ###
941
942Atomic add on halfword in memory, with Store-release semantics _(Armv8.1)_
943
944    void ldaddlh(const Register& rs, const Register& rt, const MemOperand& src)
945
946
947### LDAPR ###
948
949Load-Acquire RCpc Register word or doubleword _(Armv8.3)_
950
951    void ldapr(const Register& rt, const MemOperand& src)
952
953
954### LDAPRB ###
955
956Load-Acquire RCpc Register byte _(Armv8.3)_
957
958    void ldaprb(const Register& rt, const MemOperand& src)
959
960
961### LDAPRH ###
962
963Load-Acquire RCpc Register halfword _(Armv8.3)_
964
965    void ldaprh(const Register& rt, const MemOperand& src)
966
967
968### LDAPUR ###
969
970Load-acquire RCpc Register word or double-word (with unscaled offset) _(Armv8.4)_.
971
972    void ldapur(const Register& rt, const MemOperand& src)
973
974
975### LDAPURB ###
976
977Load-acquire RCpc Register byte (with unscaled offset) _(Armv8.4)_.
978
979    void ldapurb(const Register& rt, const MemOperand& src)
980
981
982### LDAPURH ###
983
984Load-acquire RCpc Register half-word (with unscaled offset) _(Armv8.4)_.
985
986    void ldapurh(const Register& rt, const MemOperand& src)
987
988
989### LDAPURSB ###
990
991Load-acquire RCpc Register signed byte (with unscaled offset) _(Armv8.4)_.
992
993    void ldapursb(const Register& rt, const MemOperand& src)
994
995
996### LDAPURSH ###
997
998Load-acquire RCpc Register signed half-word (with unscaled offset) _(Armv8.4)_.
999
1000    void ldapursh(const Register& rt, const MemOperand& src)
1001
1002
1003### LDAPURSW ###
1004
1005Load-acquire RCpc Register signed word (with unscaled offset) _(Armv8.4)_.
1006
1007    void ldapursw(const Register& xt, const MemOperand& src)
1008
1009
1010### LDAR ###
1011
1012Load-acquire register.
1013
1014    void ldar(const Register& rt, const MemOperand& src)
1015
1016
1017### LDARB ###
1018
1019Load-acquire byte.
1020
1021    void ldarb(const Register& rt, const MemOperand& src)
1022
1023
1024### LDARH ###
1025
1026Load-acquire half-word.
1027
1028    void ldarh(const Register& rt, const MemOperand& src)
1029
1030
1031### LDAXP ###
1032
1033Load-acquire exclusive register pair.
1034
1035    void ldaxp(const Register& rt, const Register& rt2, const MemOperand& src)
1036
1037
1038### LDAXR ###
1039
1040Load-acquire exclusive register.
1041
1042    void ldaxr(const Register& rt, const MemOperand& src)
1043
1044
1045### LDAXRB ###
1046
1047Load-acquire exclusive byte.
1048
1049    void ldaxrb(const Register& rt, const MemOperand& src)
1050
1051
1052### LDAXRH ###
1053
1054Load-acquire exclusive half-word.
1055
1056    void ldaxrh(const Register& rt, const MemOperand& src)
1057
1058
1059### LDCLR ###
1060
1061Atomic bit clear on word or doubleword in memory _(Armv8.1)_
1062
1063    void ldclr(const Register& rs, const Register& rt, const MemOperand& src)
1064
1065
1066### LDCLRA ###
1067
1068Atomic bit clear on word or doubleword in memory, with Load-acquire semantics _(Armv8.1)_
1069
1070    void ldclra(const Register& rs, const Register& rt, const MemOperand& src)
1071
1072
1073### LDCLRAB ###
1074
1075Atomic bit clear on byte in memory, with Load-acquire semantics _(Armv8.1)_
1076
1077    void ldclrab(const Register& rs, const Register& rt, const MemOperand& src)
1078
1079
1080### LDCLRAH ###
1081
1082Atomic bit clear on halfword in memory, with Load-acquire semantics _(Armv8.1)_
1083
1084    void ldclrah(const Register& rs, const Register& rt, const MemOperand& src)
1085
1086
1087### LDCLRAL ###
1088
1089Atomic bit clear on word or doubleword in memory, with Load-acquire and Store-release semantics _(Armv8.1)_
1090
1091    void ldclral(const Register& rs, const Register& rt, const MemOperand& src)
1092
1093
1094### LDCLRALB ###
1095
1096Atomic bit clear on byte in memory, with Load-acquire and Store-release semantics _(Armv8.1)_
1097
1098    void ldclralb(const Register& rs, const Register& rt, const MemOperand& src)
1099
1100
1101### LDCLRALH ###
1102
1103Atomic bit clear on halfword in memory, with Load-acquire and Store-release semantics _(Armv8.1)_
1104
1105    void ldclralh(const Register& rs, const Register& rt, const MemOperand& src)
1106
1107
1108### LDCLRB ###
1109
1110Atomic bit clear on byte in memory _(Armv8.1)_
1111
1112    void ldclrb(const Register& rs, const Register& rt, const MemOperand& src)
1113
1114
1115### LDCLRH ###
1116
1117Atomic bit clear on halfword in memory _(Armv8.1)_
1118
1119    void ldclrh(const Register& rs, const Register& rt, const MemOperand& src)
1120
1121
1122### LDCLRL ###
1123
1124Atomic bit clear on word or doubleword in memory, with Store-release semantics _(Armv8.1)_
1125
1126    void ldclrl(const Register& rs, const Register& rt, const MemOperand& src)
1127
1128
1129### LDCLRLB ###
1130
1131Atomic bit clear on byte in memory, with Store-release semantics _(Armv8.1)_
1132
1133    void ldclrlb(const Register& rs, const Register& rt, const MemOperand& src)
1134
1135
1136### LDCLRLH ###
1137
1138Atomic bit clear on halfword in memory, with Store-release semantics _(Armv8.1)_
1139
1140    void ldclrlh(const Register& rs, const Register& rt, const MemOperand& src)
1141
1142
1143### LDEOR ###
1144
1145Atomic exclusive OR on word or doubleword in memory _(Armv8.1)_
1146
1147    void ldeor(const Register& rs, const Register& rt, const MemOperand& src)
1148
1149
1150### LDEORA ###
1151
1152Atomic exclusive OR on word or doubleword in memory, with Load-acquire semantics _(Armv8.1)_
1153
1154    void ldeora(const Register& rs, const Register& rt, const MemOperand& src)
1155
1156
1157### LDEORAB ###
1158
1159Atomic exclusive OR on byte in memory, with Load-acquire semantics _(Armv8.1)_
1160
1161    void ldeorab(const Register& rs, const Register& rt, const MemOperand& src)
1162
1163
1164### LDEORAH ###
1165
1166Atomic exclusive OR on halfword in memory, with Load-acquire semantics _(Armv8.1)_
1167
1168    void ldeorah(const Register& rs, const Register& rt, const MemOperand& src)
1169
1170
1171### LDEORAL ###
1172
1173Atomic exclusive OR on word or doubleword in memory, with Load-acquire and Store-release semantics _(Armv8.1)_
1174
1175    void ldeoral(const Register& rs, const Register& rt, const MemOperand& src)
1176
1177
1178### LDEORALB ###
1179
1180Atomic exclusive OR on byte in memory, with Load-acquire and Store-release semantics _(Armv8.1)_
1181
1182    void ldeoralb(const Register& rs, const Register& rt, const MemOperand& src)
1183
1184
1185### LDEORALH ###
1186
1187Atomic exclusive OR on halfword in memory, with Load-acquire and Store-release semantics _(Armv8.1)_
1188
1189    void ldeoralh(const Register& rs, const Register& rt, const MemOperand& src)
1190
1191
1192### LDEORB ###
1193
1194Atomic exclusive OR on byte in memory _(Armv8.1)_
1195
1196    void ldeorb(const Register& rs, const Register& rt, const MemOperand& src)
1197
1198
1199### LDEORH ###
1200
1201Atomic exclusive OR on halfword in memory _(Armv8.1)_
1202
1203    void ldeorh(const Register& rs, const Register& rt, const MemOperand& src)
1204
1205
1206### LDEORL ###
1207
1208Atomic exclusive OR on word or doubleword in memory, with Store-release semantics _(Armv8.1)_
1209
1210    void ldeorl(const Register& rs, const Register& rt, const MemOperand& src)
1211
1212
1213### LDEORLB ###
1214
1215Atomic exclusive OR on byte in memory, with Store-release semantics _(Armv8.1)_
1216
1217    void ldeorlb(const Register& rs, const Register& rt, const MemOperand& src)
1218
1219
1220### LDEORLH ###
1221
1222Atomic exclusive OR on halfword in memory, with Store-release semantics _(Armv8.1)_
1223
1224    void ldeorlh(const Register& rs, const Register& rt, const MemOperand& src)
1225
1226
1227### LDLAR ###
1228
1229Load LORelease register _(Armv8.1)_.
1230
1231    void ldlar(const Register& rt, const MemOperand& src)
1232
1233
1234### LDLARB ###
1235
1236Load LORelease byte _(Armv8.1)_.
1237
1238    void ldlarb(const Register& rt, const MemOperand& src)
1239
1240
1241### LDLARH ###
1242
1243Load LORelease half-word _(Armv8.1)_.
1244
1245    void ldlarh(const Register& rt, const MemOperand& src)
1246
1247
1248### LDNP ###
1249
1250Load integer or FP register pair, non-temporal.
1251
1252    void ldnp(const CPURegister& rt,
1253              const CPURegister& rt2,
1254              const MemOperand& src)
1255
1256
1257### LDP ###
1258
1259Load integer or FP register pair.
1260
1261    void ldp(const CPURegister& rt,
1262             const CPURegister& rt2,
1263             const MemOperand& src)
1264
1265
1266### LDPSW ###
1267
1268Load word pair with sign extension.
1269
1270    void ldpsw(const Register& xt, const Register& xt2, const MemOperand& src)
1271
1272
1273### LDR ###
1274
1275Load integer or FP register from literal pool.
1276
1277    void ldr(const CPURegister& rt, RawLiteral* literal)
1278
1279
1280### LDR ###
1281
1282Load integer or FP register from pc + imm19 << 2.
1283
1284    void ldr(const CPURegister& rt, int64_t imm19)
1285
1286
1287### LDR ###
1288
1289Load integer or FP register.
1290
1291    void ldr(const CPURegister& rt,
1292             const MemOperand& src,
1293             LoadStoreScalingOption option = PreferScaledOffset)
1294
1295
1296### LDRAA ###
1297
1298Load double-word with pointer authentication, using data key A and a modifier of zero _(Armv8.3)_.
1299
1300    void ldraa(const Register& xt, const MemOperand& src)
1301
1302
1303### LDRAB ###
1304
1305Load double-word with pointer authentication, using data key B and a modifier of zero _(Armv8.3)_.
1306
1307    void ldrab(const Register& xt, const MemOperand& src)
1308
1309
1310### LDRB ###
1311
1312Load byte.
1313
1314    void ldrb(const Register& rt,
1315              const MemOperand& src,
1316              LoadStoreScalingOption option = PreferScaledOffset)
1317
1318
1319### LDRH ###
1320
1321Load half-word.
1322
1323    void ldrh(const Register& rt,
1324              const MemOperand& src,
1325              LoadStoreScalingOption option = PreferScaledOffset)
1326
1327
1328### LDRSB ###
1329
1330Load byte with sign extension.
1331
1332    void ldrsb(const Register& rt,
1333               const MemOperand& src,
1334               LoadStoreScalingOption option = PreferScaledOffset)
1335
1336
1337### LDRSH ###
1338
1339Load half-word with sign extension.
1340
1341    void ldrsh(const Register& rt,
1342               const MemOperand& src,
1343               LoadStoreScalingOption option = PreferScaledOffset)
1344
1345
1346### LDRSW ###
1347
1348Load word with sign extension from literal pool.
1349
1350    void ldrsw(const Register& xt, RawLiteral* literal)
1351
1352
1353### LDRSW ###
1354
1355Load word with sign extension from pc + imm19 << 2.
1356
1357    void ldrsw(const Register& xt, int64_t imm19)
1358
1359
1360### LDRSW ###
1361
1362Load word with sign extension.
1363
1364    void ldrsw(const Register& xt,
1365               const MemOperand& src,
1366               LoadStoreScalingOption option = PreferScaledOffset)
1367
1368
1369### LDSET ###
1370
1371Atomic bit set on word or doubleword in memory _(Armv8.1)_
1372
1373    void ldset(const Register& rs, const Register& rt, const MemOperand& src)
1374
1375
1376### LDSETA ###
1377
1378Atomic bit set on word or doubleword in memory, with Load-acquire semantics _(Armv8.1)_
1379
1380    void ldseta(const Register& rs, const Register& rt, const MemOperand& src)
1381
1382
1383### LDSETAB ###
1384
1385Atomic bit set on byte in memory, with Load-acquire semantics _(Armv8.1)_
1386
1387    void ldsetab(const Register& rs, const Register& rt, const MemOperand& src)
1388
1389
1390### LDSETAH ###
1391
1392Atomic bit set on halfword in memory, with Load-acquire semantics _(Armv8.1)_
1393
1394    void ldsetah(const Register& rs, const Register& rt, const MemOperand& src)
1395
1396
1397### LDSETAL ###
1398
1399Atomic bit set on word or doubleword in memory, with Load-acquire and Store-release semantics _(Armv8.1)_
1400
1401    void ldsetal(const Register& rs, const Register& rt, const MemOperand& src)
1402
1403
1404### LDSETALB ###
1405
1406Atomic bit set on byte in memory, with Load-acquire and Store-release semantics _(Armv8.1)_
1407
1408    void ldsetalb(const Register& rs, const Register& rt, const MemOperand& src)
1409
1410
1411### LDSETALH ###
1412
1413Atomic bit set on halfword in memory, with Load-acquire and Store-release semantics _(Armv8.1)_
1414
1415    void ldsetalh(const Register& rs, const Register& rt, const MemOperand& src)
1416
1417
1418### LDSETB ###
1419
1420Atomic bit set on byte in memory _(Armv8.1)_
1421
1422    void ldsetb(const Register& rs, const Register& rt, const MemOperand& src)
1423
1424
1425### LDSETH ###
1426
1427Atomic bit set on halfword in memory _(Armv8.1)_
1428
1429    void ldseth(const Register& rs, const Register& rt, const MemOperand& src)
1430
1431
1432### LDSETL ###
1433
1434Atomic bit set on word or doubleword in memory, with Store-release semantics _(Armv8.1)_
1435
1436    void ldsetl(const Register& rs, const Register& rt, const MemOperand& src)
1437
1438
1439### LDSETLB ###
1440
1441Atomic bit set on byte in memory, with Store-release semantics _(Armv8.1)_
1442
1443    void ldsetlb(const Register& rs, const Register& rt, const MemOperand& src)
1444
1445
1446### LDSETLH ###
1447
1448Atomic bit set on halfword in memory, with Store-release semantics _(Armv8.1)_
1449
1450    void ldsetlh(const Register& rs, const Register& rt, const MemOperand& src)
1451
1452
1453### LDSMAX ###
1454
1455Atomic signed maximum on word or doubleword in memory _(Armv8.1)_
1456
1457    void ldsmax(const Register& rs, const Register& rt, const MemOperand& src)
1458
1459
1460### LDSMAXA ###
1461
1462Atomic signed maximum on word or doubleword in memory, with Load-acquire semantics _(Armv8.1)_
1463
1464    void ldsmaxa(const Register& rs, const Register& rt, const MemOperand& src)
1465
1466
1467### LDSMAXAB ###
1468
1469Atomic signed maximum on byte in memory, with Load-acquire semantics _(Armv8.1)_
1470
1471    void ldsmaxab(const Register& rs, const Register& rt, const MemOperand& src)
1472
1473
1474### LDSMAXAH ###
1475
1476Atomic signed maximum on halfword in memory, with Load-acquire semantics _(Armv8.1)_
1477
1478    void ldsmaxah(const Register& rs, const Register& rt, const MemOperand& src)
1479
1480
1481### LDSMAXAL ###
1482
1483Atomic signed maximum on word or doubleword in memory, with Load-acquire and Store-release semantics _(Armv8.1)_
1484
1485    void ldsmaxal(const Register& rs, const Register& rt, const MemOperand& src)
1486
1487
1488### LDSMAXALB ###
1489
1490Atomic signed maximum on byte in memory, with Load-acquire and Store-release semantics _(Armv8.1)_
1491
1492    void ldsmaxalb(const Register& rs, const Register& rt, const MemOperand& src)
1493
1494
1495### LDSMAXALH ###
1496
1497Atomic signed maximum on halfword in memory, with Load-acquire and Store-release semantics _(Armv8.1)_
1498
1499    void ldsmaxalh(const Register& rs, const Register& rt, const MemOperand& src)
1500
1501
1502### LDSMAXB ###
1503
1504Atomic signed maximum on byte in memory _(Armv8.1)_
1505
1506    void ldsmaxb(const Register& rs, const Register& rt, const MemOperand& src)
1507
1508
1509### LDSMAXH ###
1510
1511Atomic signed maximum on halfword in memory _(Armv8.1)_
1512
1513    void ldsmaxh(const Register& rs, const Register& rt, const MemOperand& src)
1514
1515
1516### LDSMAXL ###
1517
1518Atomic signed maximum on word or doubleword in memory, with Store-release semantics _(Armv8.1)_
1519
1520    void ldsmaxl(const Register& rs, const Register& rt, const MemOperand& src)
1521
1522
1523### LDSMAXLB ###
1524
1525Atomic signed maximum on byte in memory, with Store-release semantics _(Armv8.1)_
1526
1527    void ldsmaxlb(const Register& rs, const Register& rt, const MemOperand& src)
1528
1529
1530### LDSMAXLH ###
1531
1532Atomic signed maximum on halfword in memory, with Store-release semantics _(Armv8.1)_
1533
1534    void ldsmaxlh(const Register& rs, const Register& rt, const MemOperand& src)
1535
1536
1537### LDSMIN ###
1538
1539Atomic signed minimum on word or doubleword in memory _(Armv8.1)_
1540
1541    void ldsmin(const Register& rs, const Register& rt, const MemOperand& src)
1542
1543
1544### LDSMINA ###
1545
1546Atomic signed minimum on word or doubleword in memory, with Load-acquire semantics _(Armv8.1)_
1547
1548    void ldsmina(const Register& rs, const Register& rt, const MemOperand& src)
1549
1550
1551### LDSMINAB ###
1552
1553Atomic signed minimum on byte in memory, with Load-acquire semantics _(Armv8.1)_
1554
1555    void ldsminab(const Register& rs, const Register& rt, const MemOperand& src)
1556
1557
1558### LDSMINAH ###
1559
1560Atomic signed minimum on halfword in memory, with Load-acquire semantics _(Armv8.1)_
1561
1562    void ldsminah(const Register& rs, const Register& rt, const MemOperand& src)
1563
1564
1565### LDSMINAL ###
1566
1567Atomic signed minimum on word or doubleword in memory, with Load-acquire and Store-release semantics _(Armv8.1)_
1568
1569    void ldsminal(const Register& rs, const Register& rt, const MemOperand& src)
1570
1571
1572### LDSMINALB ###
1573
1574Atomic signed minimum on byte in memory, with Load-acquire and Store-release semantics _(Armv8.1)_
1575
1576    void ldsminalb(const Register& rs, const Register& rt, const MemOperand& src)
1577
1578
1579### LDSMINALH ###
1580
1581Atomic signed minimum on halfword in memory, with Load-acquire and Store-release semantics _(Armv8.1)_
1582
1583    void ldsminalh(const Register& rs, const Register& rt, const MemOperand& src)
1584
1585
1586### LDSMINB ###
1587
1588Atomic signed minimum on byte in memory _(Armv8.1)_
1589
1590    void ldsminb(const Register& rs, const Register& rt, const MemOperand& src)
1591
1592
1593### LDSMINH ###
1594
1595Atomic signed minimum on halfword in memory _(Armv8.1)_
1596
1597    void ldsminh(const Register& rs, const Register& rt, const MemOperand& src)
1598
1599
1600### LDSMINL ###
1601
1602Atomic signed minimum on word or doubleword in memory, with Store-release semantics _(Armv8.1)_
1603
1604    void ldsminl(const Register& rs, const Register& rt, const MemOperand& src)
1605
1606
1607### LDSMINLB ###
1608
1609Atomic signed minimum on byte in memory, with Store-release semantics _(Armv8.1)_
1610
1611    void ldsminlb(const Register& rs, const Register& rt, const MemOperand& src)
1612
1613
1614### LDSMINLH ###
1615
1616Atomic signed minimum on halfword in memory, with Store-release semantics _(Armv8.1)_
1617
1618    void ldsminlh(const Register& rs, const Register& rt, const MemOperand& src)
1619
1620
1621### LDUMAX ###
1622
1623Atomic unsigned maximum on word or doubleword in memory _(Armv8.1)_
1624
1625    void ldumax(const Register& rs, const Register& rt, const MemOperand& src)
1626
1627
1628### LDUMAXA ###
1629
1630Atomic unsigned maximum on word or doubleword in memory, with Load-acquire semantics _(Armv8.1)_
1631
1632    void ldumaxa(const Register& rs, const Register& rt, const MemOperand& src)
1633
1634
1635### LDUMAXAB ###
1636
1637Atomic unsigned maximum on byte in memory, with Load-acquire semantics _(Armv8.1)_
1638
1639    void ldumaxab(const Register& rs, const Register& rt, const MemOperand& src)
1640
1641
1642### LDUMAXAH ###
1643
1644Atomic unsigned maximum on halfword in memory, with Load-acquire semantics _(Armv8.1)_
1645
1646    void ldumaxah(const Register& rs, const Register& rt, const MemOperand& src)
1647
1648
1649### LDUMAXAL ###
1650
1651Atomic unsigned maximum on word or doubleword in memory, with Load-acquire and Store-release semantics _(Armv8.1)_
1652
1653    void ldumaxal(const Register& rs, const Register& rt, const MemOperand& src)
1654
1655
1656### LDUMAXALB ###
1657
1658Atomic unsigned maximum on byte in memory, with Load-acquire and Store-release semantics _(Armv8.1)_
1659
1660    void ldumaxalb(const Register& rs, const Register& rt, const MemOperand& src)
1661
1662
1663### LDUMAXALH ###
1664
1665Atomic unsigned maximum on halfword in memory, with Load-acquire and Store-release semantics _(Armv8.1)_
1666
1667    void ldumaxalh(const Register& rs, const Register& rt, const MemOperand& src)
1668
1669
1670### LDUMAXB ###
1671
1672Atomic unsigned maximum on byte in memory _(Armv8.1)_
1673
1674    void ldumaxb(const Register& rs, const Register& rt, const MemOperand& src)
1675
1676
1677### LDUMAXH ###
1678
1679Atomic unsigned maximum on halfword in memory _(Armv8.1)_
1680
1681    void ldumaxh(const Register& rs, const Register& rt, const MemOperand& src)
1682
1683
1684### LDUMAXL ###
1685
1686Atomic unsigned maximum on word or doubleword in memory, with Store-release semantics _(Armv8.1)_
1687
1688    void ldumaxl(const Register& rs, const Register& rt, const MemOperand& src)
1689
1690
1691### LDUMAXLB ###
1692
1693Atomic unsigned maximum on byte in memory, with Store-release semantics _(Armv8.1)_
1694
1695    void ldumaxlb(const Register& rs, const Register& rt, const MemOperand& src)
1696
1697
1698### LDUMAXLH ###
1699
1700Atomic unsigned maximum on halfword in memory, with Store-release semantics _(Armv8.1)_
1701
1702    void ldumaxlh(const Register& rs, const Register& rt, const MemOperand& src)
1703
1704
1705### LDUMIN ###
1706
1707Atomic unsigned minimum on word or doubleword in memory _(Armv8.1)_
1708
1709    void ldumin(const Register& rs, const Register& rt, const MemOperand& src)
1710
1711
1712### LDUMINA ###
1713
1714Atomic unsigned minimum on word or doubleword in memory, with Load-acquire semantics _(Armv8.1)_
1715
1716    void ldumina(const Register& rs, const Register& rt, const MemOperand& src)
1717
1718
1719### LDUMINAB ###
1720
1721Atomic unsigned minimum on byte in memory, with Load-acquire semantics _(Armv8.1)_
1722
1723    void lduminab(const Register& rs, const Register& rt, const MemOperand& src)
1724
1725
1726### LDUMINAH ###
1727
1728Atomic unsigned minimum on halfword in memory, with Load-acquire semantics _(Armv8.1)_
1729
1730    void lduminah(const Register& rs, const Register& rt, const MemOperand& src)
1731
1732
1733### LDUMINAL ###
1734
1735Atomic unsigned minimum on word or doubleword in memory, with Load-acquire and Store-release semantics _(Armv8.1)_
1736
1737    void lduminal(const Register& rs, const Register& rt, const MemOperand& src)
1738
1739
1740### LDUMINALB ###
1741
1742Atomic unsigned minimum on byte in memory, with Load-acquire and Store-release semantics _(Armv8.1)_
1743
1744    void lduminalb(const Register& rs, const Register& rt, const MemOperand& src)
1745
1746
1747### LDUMINALH ###
1748
1749Atomic unsigned minimum on halfword in memory, with Load-acquire and Store-release semantics _(Armv8.1)_
1750
1751    void lduminalh(const Register& rs, const Register& rt, const MemOperand& src)
1752
1753
1754### LDUMINB ###
1755
1756Atomic unsigned minimum on byte in memory _(Armv8.1)_
1757
1758    void lduminb(const Register& rs, const Register& rt, const MemOperand& src)
1759
1760
1761### LDUMINH ###
1762
1763Atomic unsigned minimum on halfword in memory _(Armv8.1)_
1764
1765    void lduminh(const Register& rs, const Register& rt, const MemOperand& src)
1766
1767
1768### LDUMINL ###
1769
1770Atomic unsigned minimum on word or doubleword in memory, with Store-release semantics _(Armv8.1)_
1771
1772    void lduminl(const Register& rs, const Register& rt, const MemOperand& src)
1773
1774
1775### LDUMINLB ###
1776
1777Atomic unsigned minimum on byte in memory, with Store-release semantics _(Armv8.1)_
1778
1779    void lduminlb(const Register& rs, const Register& rt, const MemOperand& src)
1780
1781
1782### LDUMINLH ###
1783
1784Atomic unsigned minimum on halfword in memory, with Store-release semantics _(Armv8.1)_
1785
1786    void lduminlh(const Register& rs, const Register& rt, const MemOperand& src)
1787
1788
1789### LDUR ###
1790
1791Load integer or FP register (with unscaled offset).
1792
1793    void ldur(const CPURegister& rt,
1794              const MemOperand& src,
1795              LoadStoreScalingOption option = PreferUnscaledOffset)
1796
1797
1798### LDURB ###
1799
1800Load byte (with unscaled offset).
1801
1802    void ldurb(const Register& rt,
1803               const MemOperand& src,
1804               LoadStoreScalingOption option = PreferUnscaledOffset)
1805
1806
1807### LDURH ###
1808
1809Load half-word (with unscaled offset).
1810
1811    void ldurh(const Register& rt,
1812               const MemOperand& src,
1813               LoadStoreScalingOption option = PreferUnscaledOffset)
1814
1815
1816### LDURSB ###
1817
1818Load byte with sign extension (and unscaled offset).
1819
1820    void ldursb(const Register& rt,
1821                const MemOperand& src,
1822                LoadStoreScalingOption option = PreferUnscaledOffset)
1823
1824
1825### LDURSH ###
1826
1827Load half-word with sign extension (and unscaled offset).
1828
1829    void ldursh(const Register& rt,
1830                const MemOperand& src,
1831                LoadStoreScalingOption option = PreferUnscaledOffset)
1832
1833
1834### LDURSW ###
1835
1836Load word with sign extension.
1837
1838    void ldursw(const Register& xt,
1839                const MemOperand& src,
1840                LoadStoreScalingOption option = PreferUnscaledOffset)
1841
1842
1843### LDXP ###
1844
1845Load exclusive register pair.
1846
1847    void ldxp(const Register& rt, const Register& rt2, const MemOperand& src)
1848
1849
1850### LDXR ###
1851
1852Load exclusive register.
1853
1854    void ldxr(const Register& rt, const MemOperand& src)
1855
1856
1857### LDXRB ###
1858
1859Load exclusive byte.
1860
1861    void ldxrb(const Register& rt, const MemOperand& src)
1862
1863
1864### LDXRH ###
1865
1866Load exclusive half-word.
1867
1868    void ldxrh(const Register& rt, const MemOperand& src)
1869
1870
1871### LSL ###
1872
1873Logical shift left.
1874
1875    void lsl(const Register& rd, const Register& rn, unsigned shift)
1876
1877
1878### LSLV ###
1879
1880Logical shift left by variable.
1881
1882    void lslv(const Register& rd, const Register& rn, const Register& rm)
1883
1884
1885### LSR ###
1886
1887Logical shift right.
1888
1889    void lsr(const Register& rd, const Register& rn, unsigned shift)
1890
1891
1892### LSRV ###
1893
1894Logical shift right by variable.
1895
1896    void lsrv(const Register& rd, const Register& rn, const Register& rm)
1897
1898
1899### MADD ###
1900
1901Multiply and accumulate.
1902
1903    void madd(const Register& rd,
1904              const Register& rn,
1905              const Register& rm,
1906              const Register& ra)
1907
1908
1909### MNEG ###
1910
1911Negated multiply.
1912
1913    void mneg(const Register& rd, const Register& rn, const Register& rm)
1914
1915
1916### MOV ###
1917
1918Move register to register.
1919
1920    void mov(const Register& rd, const Register& rn)
1921
1922
1923### MOVK ###
1924
1925Move immediate and keep.
1926
1927    void movk(const Register& rd, uint64_t imm, int shift = -1)
1928
1929
1930### MOVN ###
1931
1932Move inverted immediate.
1933
1934    void movn(const Register& rd, uint64_t imm, int shift = -1)
1935
1936
1937### MOVZ ###
1938
1939Move immediate.
1940
1941    void movz(const Register& rd, uint64_t imm, int shift = -1)
1942
1943
1944### MRS ###
1945
1946Move to register from system register.
1947
1948    void mrs(const Register& xt, SystemRegister sysreg)
1949
1950
1951### MSR ###
1952
1953Move from register to system register.
1954
1955    void msr(SystemRegister sysreg, const Register& xt)
1956
1957
1958### MSUB ###
1959
1960Multiply and subtract.
1961
1962    void msub(const Register& rd,
1963              const Register& rn,
1964              const Register& rm,
1965              const Register& ra)
1966
1967
1968### MUL ###
1969
1970Multiply.
1971
1972    void mul(const Register& rd, const Register& rn, const Register& rm)
1973
1974
1975### MVN ###
1976
1977Move inverted operand to register.
1978
1979    void mvn(const Register& rd, const Operand& operand)
1980
1981
1982### NEG ###
1983
1984Negate.
1985
1986    void neg(const Register& rd, const Operand& operand)
1987
1988
1989### NEGS ###
1990
1991Negate and update status flags.
1992
1993    void negs(const Register& rd, const Operand& operand)
1994
1995
1996### NGC ###
1997
1998Negate with carry bit.
1999
2000    void ngc(const Register& rd, const Operand& operand)
2001
2002
2003### NGCS ###
2004
2005Negate with carry bit and update status flags.
2006
2007    void ngcs(const Register& rd, const Operand& operand)
2008
2009
2010### NOP ###
2011
2012No-op.
2013
2014    void nop()
2015
2016
2017### ORN ###
2018
2019Bitwise nor (A | ~B).
2020
2021    void orn(const Register& rd, const Register& rn, const Operand& operand)
2022
2023
2024### ORR ###
2025
2026Bitwise or (A | B).
2027
2028    void orr(const Register& rd, const Register& rn, const Operand& operand)
2029
2030
2031### PACDA ###
2032
2033Pointer Authentication Code for Data address, using key A _(Armv8.3)_.
2034
2035    void pacda(const Register& xd, const Register& xn)
2036
2037
2038### PACDA1716 ###
2039
2040Pointer Authentication Code for Data address, using key A, with address in x17 and modifier in x16 _(Armv8.3)_.
2041
2042    void pacda1716()
2043
2044
2045### PACDASP ###
2046
2047Pointer Authentication Code for Data address, using key A, with address in LR and modifier in SP _(Armv8.3)_.
2048
2049    void pacdasp()
2050
2051
2052### PACDAZ ###
2053
2054Pointer Authentication Code for Data address, using key A, with address in LR and a modifier of zero _(Armv8.3)_.
2055
2056    void pacdaz()
2057
2058
2059### PACDB ###
2060
2061Pointer Authentication Code for Data address, using key B _(Armv8.3)_.
2062
2063    void pacdb(const Register& xd, const Register& xn)
2064
2065
2066### PACDB1716 ###
2067
2068Pointer Authentication Code for Data address, using key B, with address in x17 and modifier in x16 _(Armv8.3)_.
2069
2070    void pacdb1716()
2071
2072
2073### PACDBSP ###
2074
2075Pointer Authentication Code for Data address, using key B, with address in LR and modifier in SP _(Armv8.3)_.
2076
2077    void pacdbsp()
2078
2079
2080### PACDBZ ###
2081
2082Pointer Authentication Code for Data address, using key B, with address in LR and a modifier of zero _(Armv8.3)_.
2083
2084    void pacdbz()
2085
2086
2087### PACDZA ###
2088
2089Pointer Authentication Code for Data address, using key A and a modifier of zero _(Armv8.3)_.
2090
2091    void pacdza(const Register& xd)
2092
2093
2094### PACDZB ###
2095
2096Pointer Authentication Code for Data address, using key B and a modifier of zero _(Armv8.3)_.
2097
2098    void pacdzb(const Register& xd)
2099
2100
2101### PACGA ###
2102
2103Pointer Authentication Code, using Generic key _(Armv8.3)_.
2104
2105    void pacga(const Register& xd, const Register& xn, const Register& xm)
2106
2107
2108### PACIA ###
2109
2110Pointer Authentication Code for Instruction address, using key A _(Armv8.3)_.
2111
2112    void pacia(const Register& xd, const Register& rn)
2113
2114
2115### PACIA1716 ###
2116
2117Pointer Authentication Code for Instruction address, using key A, with address in x17 and modifier in x16 _(Armv8.3)_.
2118
2119    void pacia1716()
2120
2121
2122### PACIASP ###
2123
2124Pointer Authentication Code for Instruction address, using key A, with address in LR and modifier in SP _(Armv8.3)_.
2125
2126    void paciasp()
2127
2128
2129### PACIAZ ###
2130
2131Pointer Authentication Code for Instruction address, using key A, with address in LR and a modifier of zero _(Armv8.3)_.
2132
2133    void paciaz()
2134
2135
2136### PACIB ###
2137
2138Pointer Authentication Code for Instruction address, using key B _(Armv8.3)_.
2139
2140    void pacib(const Register& xd, const Register& xn)
2141
2142
2143### PACIB1716 ###
2144
2145Pointer Authentication Code for Instruction address, using key B, with address in x17 and modifier in x16 _(Armv8.3)_.
2146
2147    void pacib1716()
2148
2149
2150### PACIBSP ###
2151
2152Pointer Authentication Code for Instruction address, using key B, with address in LR and modifier in SP _(Armv8.3)_.
2153
2154    void pacibsp()
2155
2156
2157### PACIBZ ###
2158
2159Pointer Authentication Code for Instruction address, using key B, with address in LR and a modifier of zero _(Armv8.3)_.
2160
2161    void pacibz()
2162
2163
2164### PACIZA ###
2165
2166Pointer Authentication Code for Instruction address, using key A and a modifier of zero _(Armv8.3)_.
2167
2168    void paciza(const Register& xd)
2169
2170
2171### PACIZB ###
2172
2173Pointer Authentication Code for Instruction address, using key B and a modifier of zero _(Armv8.3)_.
2174
2175    void pacizb(const Register& xd)
2176
2177
2178### PRFM ###
2179
2180Prefetch from pc + imm19 << 2.
2181
2182    void prfm(PrefetchOperation op, int64_t imm19)
2183
2184
2185### PRFM ###
2186
2187Prefetch memory in the literal pool.
2188
2189    void prfm(PrefetchOperation op, RawLiteral* literal)
2190
2191
2192### PRFM ###
2193
2194Prefetch memory.
2195
2196    void prfm(PrefetchOperation op,
2197              const MemOperand& addr,
2198              LoadStoreScalingOption option = PreferScaledOffset)
2199
2200
2201### PRFUM ###
2202
2203Prefetch memory (with unscaled offset).
2204
2205    void prfum(PrefetchOperation op,
2206               const MemOperand& addr,
2207               LoadStoreScalingOption option = PreferUnscaledOffset)
2208
2209
2210### RBIT ###
2211
2212Bit reverse.
2213
2214    void rbit(const Register& rd, const Register& rn)
2215
2216
2217### RET ###
2218
2219Branch to register with return hint.
2220
2221    void ret(const Register& xn = lr)
2222
2223
2224### RETAA ###
2225
2226Return from subroutine, with pointer authentication. Using key A _(Armv8.3)_.
2227
2228    void retaa()
2229
2230
2231### RETAB ###
2232
2233Return from subroutine, with pointer authentication. Using key B _(Armv8.3)_.
2234
2235    void retab()
2236
2237
2238### REV ###
2239
2240Reverse bytes.
2241
2242    void rev(const Register& rd, const Register& rn)
2243
2244
2245### REV16 ###
2246
2247Reverse bytes in 16-bit half words.
2248
2249    void rev16(const Register& rd, const Register& rn)
2250
2251
2252### REV32 ###
2253
2254Reverse bytes in 32-bit words.
2255
2256    void rev32(const Register& xd, const Register& xn)
2257
2258
2259### REV64 ###
2260
2261Reverse bytes in 64-bit general purpose register, an alias for rev _(Armv8.2)_.
2262
2263    void rev64(const Register& xd, const Register& xn)
2264
2265
2266### RMIF ###
2267
2268Rotate register right and insert into NZCV flags under the control of a mask _(Armv8.4)_.
2269
2270    void rmif(const Register& xn, unsigned rotation, StatusFlags flags)
2271
2272
2273### ROR ###
2274
2275Rotate right.
2276
2277    void ror(const Register& rd, const Register& rs, unsigned shift)
2278
2279
2280### RORV ###
2281
2282Rotate right by variable.
2283
2284    void rorv(const Register& rd, const Register& rn, const Register& rm)
2285
2286
2287### SBC ###
2288
2289Subtract with carry bit.
2290
2291    void sbc(const Register& rd, const Register& rn, const Operand& operand)
2292
2293
2294### SBCS ###
2295
2296Subtract with carry bit and update status flags.
2297
2298    void sbcs(const Register& rd, const Register& rn, const Operand& operand)
2299
2300
2301### SBFIZ ###
2302
2303Signed bitfield insert with zero at right.
2304
2305    void sbfiz(const Register& rd,
2306               const Register& rn,
2307               unsigned lsb,
2308               unsigned width)
2309
2310
2311### SBFM ###
2312
2313Signed bitfield move.
2314
2315    void sbfm(const Register& rd,
2316              const Register& rn,
2317              unsigned immr,
2318              unsigned imms)
2319
2320
2321### SBFX ###
2322
2323Signed bitfield extract.
2324
2325    void sbfx(const Register& rd,
2326              const Register& rn,
2327              unsigned lsb,
2328              unsigned width)
2329
2330
2331### SDIV ###
2332
2333Signed integer divide.
2334
2335    void sdiv(const Register& rd, const Register& rn, const Register& rm)
2336
2337
2338### SETF16 ###
2339
2340Set NZCV flags from register, treated as an 16-bit value _(Armv8.4)_.
2341
2342    void setf16(const Register& rn)
2343
2344
2345### SETF8 ###
2346
2347Set NZCV flags from register, treated as an 8-bit value _(Armv8.4)_.
2348
2349    void setf8(const Register& rn)
2350
2351
2352### SMADDL ###
2353
2354Signed long multiply and accumulate: 32 x 32 + 64 -> 64-bit.
2355
2356    void smaddl(const Register& xd,
2357                const Register& wn,
2358                const Register& wm,
2359                const Register& xa)
2360
2361
2362### SMSUBL ###
2363
2364Signed long multiply and subtract: 64 - (32 x 32) -> 64-bit.
2365
2366    void smsubl(const Register& xd,
2367                const Register& wn,
2368                const Register& wm,
2369                const Register& xa)
2370
2371
2372### SMULH ###
2373
2374Signed multiply high: 64 x 64 -> 64-bit <127:64>.
2375
2376    void smulh(const Register& xd, const Register& xn, const Register& xm)
2377
2378
2379### SMULL ###
2380
2381Signed long multiply: 32 x 32 -> 64-bit.
2382
2383    void smull(const Register& xd, const Register& wn, const Register& wm)
2384
2385
2386### STADD ###
2387
2388Atomic add on word or doubleword in memory, without return. _(Armv8.1)_
2389
2390    void stadd(const Register& rs, const MemOperand& src)
2391
2392
2393### STADDB ###
2394
2395Atomic add on byte in memory, without return. _(Armv8.1)_
2396
2397    void staddb(const Register& rs, const MemOperand& src)
2398
2399
2400### STADDH ###
2401
2402Atomic add on halfword in memory, without return. _(Armv8.1)_
2403
2404    void staddh(const Register& rs, const MemOperand& src)
2405
2406
2407### STADDL ###
2408
2409Atomic add on word or doubleword in memory, with Store-release semantics and without return. _(Armv8.1)_
2410
2411    void staddl(const Register& rs, const MemOperand& src)
2412
2413
2414### STADDLB ###
2415
2416Atomic add on byte in memory, with Store-release semantics and without return. _(Armv8.1)_
2417
2418    void staddlb(const Register& rs, const MemOperand& src)
2419
2420
2421### STADDLH ###
2422
2423Atomic add on halfword in memory, with Store-release semantics and without return. _(Armv8.1)_
2424
2425    void staddlh(const Register& rs, const MemOperand& src)
2426
2427
2428### STCLR ###
2429
2430Atomic bit clear on word or doubleword in memory, without return. _(Armv8.1)_
2431
2432    void stclr(const Register& rs, const MemOperand& src)
2433
2434
2435### STCLRB ###
2436
2437Atomic bit clear on byte in memory, without return. _(Armv8.1)_
2438
2439    void stclrb(const Register& rs, const MemOperand& src)
2440
2441
2442### STCLRH ###
2443
2444Atomic bit clear on halfword in memory, without return. _(Armv8.1)_
2445
2446    void stclrh(const Register& rs, const MemOperand& src)
2447
2448
2449### STCLRL ###
2450
2451Atomic bit clear on word or doubleword in memory, with Store-release semantics and without return. _(Armv8.1)_
2452
2453    void stclrl(const Register& rs, const MemOperand& src)
2454
2455
2456### STCLRLB ###
2457
2458Atomic bit clear on byte in memory, with Store-release semantics and without return. _(Armv8.1)_
2459
2460    void stclrlb(const Register& rs, const MemOperand& src)
2461
2462
2463### STCLRLH ###
2464
2465Atomic bit clear on halfword in memory, with Store-release semantics and without return. _(Armv8.1)_
2466
2467    void stclrlh(const Register& rs, const MemOperand& src)
2468
2469
2470### STEOR ###
2471
2472Atomic exclusive OR on word or doubleword in memory, without return. _(Armv8.1)_
2473
2474    void steor(const Register& rs, const MemOperand& src)
2475
2476
2477### STEORB ###
2478
2479Atomic exclusive OR on byte in memory, without return. _(Armv8.1)_
2480
2481    void steorb(const Register& rs, const MemOperand& src)
2482
2483
2484### STEORH ###
2485
2486Atomic exclusive OR on halfword in memory, without return. _(Armv8.1)_
2487
2488    void steorh(const Register& rs, const MemOperand& src)
2489
2490
2491### STEORL ###
2492
2493Atomic exclusive OR on word or doubleword in memory, with Store-release semantics and without return. _(Armv8.1)_
2494
2495    void steorl(const Register& rs, const MemOperand& src)
2496
2497
2498### STEORLB ###
2499
2500Atomic exclusive OR on byte in memory, with Store-release semantics and without return. _(Armv8.1)_
2501
2502    void steorlb(const Register& rs, const MemOperand& src)
2503
2504
2505### STEORLH ###
2506
2507Atomic exclusive OR on halfword in memory, with Store-release semantics and without return. _(Armv8.1)_
2508
2509    void steorlh(const Register& rs, const MemOperand& src)
2510
2511
2512### STLLR ###
2513
2514Store LORelease register _(Armv8.1)_.
2515
2516    void stllr(const Register& rt, const MemOperand& dst)
2517
2518
2519### STLLRB ###
2520
2521Store LORelease byte _(Armv8.1)_.
2522
2523    void stllrb(const Register& rt, const MemOperand& dst)
2524
2525
2526### STLLRH ###
2527
2528Store LORelease half-word _(Armv8.1)_.
2529
2530    void stllrh(const Register& rt, const MemOperand& dst)
2531
2532
2533### STLR ###
2534
2535Store-release register.
2536
2537    void stlr(const Register& rt, const MemOperand& dst)
2538
2539
2540### STLRB ###
2541
2542Store-release byte.
2543
2544    void stlrb(const Register& rt, const MemOperand& dst)
2545
2546
2547### STLRH ###
2548
2549Store-release half-word.
2550
2551    void stlrh(const Register& rt, const MemOperand& dst)
2552
2553
2554### STLUR ###
2555
2556Store-release word or double-word (with unscaled offset) _(Armv8.4)_.
2557
2558    void stlur(const Register& rt, const MemOperand& dst)
2559
2560
2561### STLURB ###
2562
2563Store-release byte (with unscaled offset) _(Armv8.4)_.
2564
2565    void stlurb(const Register& rt, const MemOperand& dst)
2566
2567
2568### STLURH ###
2569
2570Store-release half-word (with unscaled offset) _(Armv8.4)_.
2571
2572    void stlurh(const Register& rt, const MemOperand& dst)
2573
2574
2575### STLXP ###
2576
2577Store-release exclusive register pair.
2578
2579    void stlxp(const Register& rs,
2580               const Register& rt,
2581               const Register& rt2,
2582               const MemOperand& dst)
2583
2584
2585### STLXR ###
2586
2587Store-release exclusive register.
2588
2589    void stlxr(const Register& rs, const Register& rt, const MemOperand& dst)
2590
2591
2592### STLXRB ###
2593
2594Store-release exclusive byte.
2595
2596    void stlxrb(const Register& rs, const Register& rt, const MemOperand& dst)
2597
2598
2599### STLXRH ###
2600
2601Store-release exclusive half-word.
2602
2603    void stlxrh(const Register& rs, const Register& rt, const MemOperand& dst)
2604
2605
2606### STNP ###
2607
2608Store integer or FP register pair, non-temporal.
2609
2610    void stnp(const CPURegister& rt,
2611              const CPURegister& rt2,
2612              const MemOperand& dst)
2613
2614
2615### STP ###
2616
2617Store integer or FP register pair.
2618
2619    void stp(const CPURegister& rt,
2620             const CPURegister& rt2,
2621             const MemOperand& dst)
2622
2623
2624### STR ###
2625
2626Store integer or FP register.
2627
2628    void str(const CPURegister& rt,
2629             const MemOperand& dst,
2630             LoadStoreScalingOption option = PreferScaledOffset)
2631
2632
2633### STRB ###
2634
2635Store byte.
2636
2637    void strb(const Register& rt,
2638              const MemOperand& dst,
2639              LoadStoreScalingOption option = PreferScaledOffset)
2640
2641
2642### STRH ###
2643
2644Store half-word.
2645
2646    void strh(const Register& rt,
2647              const MemOperand& dst,
2648              LoadStoreScalingOption option = PreferScaledOffset)
2649
2650
2651### STSET ###
2652
2653Atomic bit set on word or doubleword in memory, without return. _(Armv8.1)_
2654
2655    void stset(const Register& rs, const MemOperand& src)
2656
2657
2658### STSETB ###
2659
2660Atomic bit set on byte in memory, without return. _(Armv8.1)_
2661
2662    void stsetb(const Register& rs, const MemOperand& src)
2663
2664
2665### STSETH ###
2666
2667Atomic bit set on halfword in memory, without return. _(Armv8.1)_
2668
2669    void stseth(const Register& rs, const MemOperand& src)
2670
2671
2672### STSETL ###
2673
2674Atomic bit set on word or doubleword in memory, with Store-release semantics and without return. _(Armv8.1)_
2675
2676    void stsetl(const Register& rs, const MemOperand& src)
2677
2678
2679### STSETLB ###
2680
2681Atomic bit set on byte in memory, with Store-release semantics and without return. _(Armv8.1)_
2682
2683    void stsetlb(const Register& rs, const MemOperand& src)
2684
2685
2686### STSETLH ###
2687
2688Atomic bit set on halfword in memory, with Store-release semantics and without return. _(Armv8.1)_
2689
2690    void stsetlh(const Register& rs, const MemOperand& src)
2691
2692
2693### STSMAX ###
2694
2695Atomic signed maximum on word or doubleword in memory, without return. _(Armv8.1)_
2696
2697    void stsmax(const Register& rs, const MemOperand& src)
2698
2699
2700### STSMAXB ###
2701
2702Atomic signed maximum on byte in memory, without return. _(Armv8.1)_
2703
2704    void stsmaxb(const Register& rs, const MemOperand& src)
2705
2706
2707### STSMAXH ###
2708
2709Atomic signed maximum on halfword in memory, without return. _(Armv8.1)_
2710
2711    void stsmaxh(const Register& rs, const MemOperand& src)
2712
2713
2714### STSMAXL ###
2715
2716Atomic signed maximum on word or doubleword in memory, with Store-release semantics and without return. _(Armv8.1)_
2717
2718    void stsmaxl(const Register& rs, const MemOperand& src)
2719
2720
2721### STSMAXLB ###
2722
2723Atomic signed maximum on byte in memory, with Store-release semantics and without return. _(Armv8.1)_
2724
2725    void stsmaxlb(const Register& rs, const MemOperand& src)
2726
2727
2728### STSMAXLH ###
2729
2730Atomic signed maximum on halfword in memory, with Store-release semantics and without return. _(Armv8.1)_
2731
2732    void stsmaxlh(const Register& rs, const MemOperand& src)
2733
2734
2735### STSMIN ###
2736
2737Atomic signed minimum on word or doubleword in memory, without return. _(Armv8.1)_
2738
2739    void stsmin(const Register& rs, const MemOperand& src)
2740
2741
2742### STSMINB ###
2743
2744Atomic signed minimum on byte in memory, without return. _(Armv8.1)_
2745
2746    void stsminb(const Register& rs, const MemOperand& src)
2747
2748
2749### STSMINH ###
2750
2751Atomic signed minimum on halfword in memory, without return. _(Armv8.1)_
2752
2753    void stsminh(const Register& rs, const MemOperand& src)
2754
2755
2756### STSMINL ###
2757
2758Atomic signed minimum on word or doubleword in memory, with Store-release semantics and without return. semantics _(Armv8.1)_
2759
2760    void stsminl(const Register& rs, const MemOperand& src)
2761
2762
2763### STSMINLB ###
2764
2765Atomic signed minimum on byte in memory, with Store-release semantics and without return. _(Armv8.1)_
2766
2767    void stsminlb(const Register& rs, const MemOperand& src)
2768
2769
2770### STSMINLH ###
2771
2772Atomic signed minimum on halfword in memory, with Store-release semantics and without return. _(Armv8.1)_
2773
2774    void stsminlh(const Register& rs, const MemOperand& src)
2775
2776
2777### STUMAX ###
2778
2779Atomic unsigned maximum on word or doubleword in memory, without return. _(Armv8.1)_
2780
2781    void stumax(const Register& rs, const MemOperand& src)
2782
2783
2784### STUMAXB ###
2785
2786Atomic unsigned maximum on byte in memory, without return. _(Armv8.1)_
2787
2788    void stumaxb(const Register& rs, const MemOperand& src)
2789
2790
2791### STUMAXH ###
2792
2793Atomic unsigned maximum on halfword in memory, without return. _(Armv8.1)_
2794
2795    void stumaxh(const Register& rs, const MemOperand& src)
2796
2797
2798### STUMAXL ###
2799
2800Atomic unsigned maximum on word or doubleword in memory, with Store-release semantics and without return. _(Armv8.1)_
2801
2802    void stumaxl(const Register& rs, const MemOperand& src)
2803
2804
2805### STUMAXLB ###
2806
2807Atomic unsigned maximum on byte in memory, with Store-release semantics and without return. _(Armv8.1)_
2808
2809    void stumaxlb(const Register& rs, const MemOperand& src)
2810
2811
2812### STUMAXLH ###
2813
2814Atomic unsigned maximum on halfword in memory, with Store-release semantics and without return. _(Armv8.1)_
2815
2816    void stumaxlh(const Register& rs, const MemOperand& src)
2817
2818
2819### STUMIN ###
2820
2821Atomic unsigned minimum on word or doubleword in memory, without return. _(Armv8.1)_
2822
2823    void stumin(const Register& rs, const MemOperand& src)
2824
2825
2826### STUMINB ###
2827
2828Atomic unsigned minimum on byte in memory, without return. _(Armv8.1)_
2829
2830    void stuminb(const Register& rs, const MemOperand& src)
2831
2832
2833### STUMINH ###
2834
2835Atomic unsigned minimum on halfword in memory, without return. _(Armv8.1)_
2836
2837    void stuminh(const Register& rs, const MemOperand& src)
2838
2839
2840### STUMINL ###
2841
2842Atomic unsigned minimum on word or doubleword in memory, with Store-release semantics and without return. _(Armv8.1)_
2843
2844    void stuminl(const Register& rs, const MemOperand& src)
2845
2846
2847### STUMINLB ###
2848
2849Atomic unsigned minimum on byte in memory, with Store-release semantics and without return. _(Armv8.1)_
2850
2851    void stuminlb(const Register& rs, const MemOperand& src)
2852
2853
2854### STUMINLH ###
2855
2856Atomic unsigned minimum on halfword in memory, with Store-release semantics and without return. _(Armv8.1)_
2857
2858    void stuminlh(const Register& rs, const MemOperand& src)
2859
2860
2861### STUR ###
2862
2863Store integer or FP register (with unscaled offset).
2864
2865    void stur(const CPURegister& rt,
2866              const MemOperand& src,
2867              LoadStoreScalingOption option = PreferUnscaledOffset)
2868
2869
2870### STURB ###
2871
2872Store byte (with unscaled offset).
2873
2874    void sturb(const Register& rt,
2875               const MemOperand& dst,
2876               LoadStoreScalingOption option = PreferUnscaledOffset)
2877
2878
2879### STURH ###
2880
2881Store half-word (with unscaled offset).
2882
2883    void sturh(const Register& rt,
2884               const MemOperand& dst,
2885               LoadStoreScalingOption option = PreferUnscaledOffset)
2886
2887
2888### STXP ###
2889
2890Store exclusive register pair.
2891
2892    void stxp(const Register& rs,
2893              const Register& rt,
2894              const Register& rt2,
2895              const MemOperand& dst)
2896
2897
2898### STXR ###
2899
2900Store exclusive register.
2901
2902    void stxr(const Register& rs, const Register& rt, const MemOperand& dst)
2903
2904
2905### STXRB ###
2906
2907Store exclusive byte.
2908
2909    void stxrb(const Register& rs, const Register& rt, const MemOperand& dst)
2910
2911
2912### STXRH ###
2913
2914Store exclusive half-word.
2915
2916    void stxrh(const Register& rs, const Register& rt, const MemOperand& dst)
2917
2918
2919### SUB ###
2920
2921Subtract.
2922
2923    void sub(const Register& rd, const Register& rn, const Operand& operand)
2924
2925
2926### SUBS ###
2927
2928Subtract and update status flags.
2929
2930    void subs(const Register& rd, const Register& rn, const Operand& operand)
2931
2932
2933### SVC ###
2934
2935Generate exception targeting EL1.
2936
2937    void svc(int code)
2938
2939
2940### SWP ###
2941
2942Swap word or doubleword in memory _(Armv8.1)_
2943
2944    void swp(const Register& rs, const Register& rt, const MemOperand& src)
2945
2946
2947### SWPA ###
2948
2949Swap word or doubleword in memory, with Load-acquire semantics _(Armv8.1)_
2950
2951    void swpa(const Register& rs, const Register& rt, const MemOperand& src)
2952
2953
2954### SWPAB ###
2955
2956Swap byte in memory, with Load-acquire semantics _(Armv8.1)_
2957
2958    void swpab(const Register& rs, const Register& rt, const MemOperand& src)
2959
2960
2961### SWPAH ###
2962
2963Swap halfword in memory, with Load-acquire semantics _(Armv8.1)_
2964
2965    void swpah(const Register& rs, const Register& rt, const MemOperand& src)
2966
2967
2968### SWPAL ###
2969
2970Swap word or doubleword in memory, with Load-acquire and Store-release semantics _(Armv8.1)_
2971
2972    void swpal(const Register& rs, const Register& rt, const MemOperand& src)
2973
2974
2975### SWPALB ###
2976
2977Swap byte in memory, with Load-acquire and Store-release semantics _(Armv8.1)_
2978
2979    void swpalb(const Register& rs, const Register& rt, const MemOperand& src)
2980
2981
2982### SWPALH ###
2983
2984Swap halfword in memory, with Load-acquire and Store-release semantics _(Armv8.1)_
2985
2986    void swpalh(const Register& rs, const Register& rt, const MemOperand& src)
2987
2988
2989### SWPB ###
2990
2991Swap byte in memory _(Armv8.1)_
2992
2993    void swpb(const Register& rs, const Register& rt, const MemOperand& src)
2994
2995
2996### SWPH ###
2997
2998Swap halfword in memory _(Armv8.1)_
2999
3000    void swph(const Register& rs, const Register& rt, const MemOperand& src)
3001
3002
3003### SWPL ###
3004
3005Swap word or doubleword in memory, with Store-release semantics _(Armv8.1)_
3006
3007    void swpl(const Register& rs, const Register& rt, const MemOperand& src)
3008
3009
3010### SWPLB ###
3011
3012Swap byte in memory, with Store-release semantics _(Armv8.1)_
3013
3014    void swplb(const Register& rs, const Register& rt, const MemOperand& src)
3015
3016
3017### SWPLH ###
3018
3019Swap halfword in memory, with Store-release semantics _(Armv8.1)_
3020
3021    void swplh(const Register& rs, const Register& rt, const MemOperand& src)
3022
3023
3024### SXTB ###
3025
3026Signed extend byte.
3027
3028    void sxtb(const Register& rd, const Register& rn)
3029
3030
3031### SXTH ###
3032
3033Signed extend halfword.
3034
3035    void sxth(const Register& rd, const Register& rn)
3036
3037
3038### SXTW ###
3039
3040Signed extend word.
3041
3042    void sxtw(const Register& rd, const Register& rn)
3043
3044
3045### SYS ###
3046
3047System instruction with pre-encoded op (op1:crn:crm:op2).
3048
3049    void sys(int op, const Register& xt = xzr)
3050
3051
3052### SYS ###
3053
3054System instruction.
3055
3056    void sys(int op1, int crn, int crm, int op2, const Register& xt = xzr)
3057
3058
3059### TBNZ ###
3060
3061Test bit and branch to PC offset if not zero.
3062
3063    void tbnz(const Register& rt, unsigned bit_pos, int64_t imm14)
3064
3065
3066### TBNZ ###
3067
3068Test bit and branch to label if not zero.
3069
3070    void tbnz(const Register& rt, unsigned bit_pos, Label* label)
3071
3072
3073### TBZ ###
3074
3075Test bit and branch to PC offset if zero.
3076
3077    void tbz(const Register& rt, unsigned bit_pos, int64_t imm14)
3078
3079
3080### TBZ ###
3081
3082Test bit and branch to label if zero.
3083
3084    void tbz(const Register& rt, unsigned bit_pos, Label* label)
3085
3086
3087### TST ###
3088
3089Bit test and set flags.
3090
3091    void tst(const Register& rn, const Operand& operand)
3092
3093
3094### UBFIZ ###
3095
3096Unsigned bitfield insert with zero at right.
3097
3098    void ubfiz(const Register& rd,
3099               const Register& rn,
3100               unsigned lsb,
3101               unsigned width)
3102
3103
3104### UBFM ###
3105
3106Unsigned bitfield move.
3107
3108    void ubfm(const Register& rd,
3109              const Register& rn,
3110              unsigned immr,
3111              unsigned imms)
3112
3113
3114### UBFX ###
3115
3116Unsigned bitfield extract.
3117
3118    void ubfx(const Register& rd,
3119              const Register& rn,
3120              unsigned lsb,
3121              unsigned width)
3122
3123
3124### UDIV ###
3125
3126Unsigned integer divide.
3127
3128    void udiv(const Register& rd, const Register& rn, const Register& rm)
3129
3130
3131### UMADDL ###
3132
3133Unsigned long multiply and accumulate: 32 x 32 + 64 -> 64-bit.
3134
3135    void umaddl(const Register& xd,
3136                const Register& wn,
3137                const Register& wm,
3138                const Register& xa)
3139
3140
3141### UMSUBL ###
3142
3143Unsigned long multiply and subtract: 64 - (32 x 32) -> 64-bit.
3144
3145    void umsubl(const Register& xd,
3146                const Register& wn,
3147                const Register& wm,
3148                const Register& xa)
3149
3150
3151### UMULH ###
3152
3153Unsigned multiply high: 64 x 64 -> 64-bit <127:64>.
3154
3155    void umulh(const Register& xd, const Register& xn, const Register& xm)
3156
3157
3158### UMULL ###
3159
3160Unsigned long multiply: 32 x 32 -> 64-bit.
3161
3162    void umull(const Register& xd, const Register& wn, const Register& wm)
3163
3164
3165### UXTB ###
3166
3167Unsigned extend byte.
3168
3169    void uxtb(const Register& rd, const Register& rn)
3170
3171
3172### UXTH ###
3173
3174Unsigned extend halfword.
3175
3176    void uxth(const Register& rd, const Register& rn)
3177
3178
3179### UXTW ###
3180
3181Unsigned extend word.
3182
3183    void uxtw(const Register& rd, const Register& rn)
3184
3185
3186### XAFLAG ###
3187
3188Convert floating-point condition flags from alternative format to Arm format _(Armv8.5)_.
3189
3190    void xaflag()
3191
3192
3193### XPACD ###
3194
3195Strip Pointer Authentication Code of Data address _(Armv8.3)_.
3196
3197    void xpacd(const Register& xd)
3198
3199
3200### XPACI ###
3201
3202Strip Pointer Authentication Code of Instruction address _(Armv8.3)_.
3203
3204    void xpaci(const Register& xd)
3205
3206
3207### XPACLRI ###
3208
3209Strip Pointer Authentication Code of Instruction address in LR _(Armv8.3)_.
3210
3211    void xpaclri()
3212
3213
3214
3215AArch64 floating point and NEON instructions
3216--------------------------------------------
3217
3218### ABS ###
3219
3220Absolute value.
3221
3222    void abs(const VRegister& vd, const VRegister& vn)
3223
3224
3225### ADD ###
3226
3227Add.
3228
3229    void add(const VRegister& vd, const VRegister& vn, const VRegister& vm)
3230
3231
3232### ADDHN ###
3233
3234Add narrow returning high half.
3235
3236    void addhn(const VRegister& vd, const VRegister& vn, const VRegister& vm)
3237
3238
3239### ADDHN2 ###
3240
3241Add narrow returning high half (second part).
3242
3243    void addhn2(const VRegister& vd, const VRegister& vn, const VRegister& vm)
3244
3245
3246### ADDP ###
3247
3248Add pair of elements scalar.
3249
3250    void addp(const VRegister& vd, const VRegister& vn)
3251
3252
3253### ADDP ###
3254
3255Add pairwise.
3256
3257    void addp(const VRegister& vd, const VRegister& vn, const VRegister& vm)
3258
3259
3260### ADDV ###
3261
3262Add across vector.
3263
3264    void addv(const VRegister& vd, const VRegister& vn)
3265
3266
3267### AND ###
3268
3269Bitwise and.
3270
3271    void and_(const VRegister& vd, const VRegister& vn, const VRegister& vm)
3272
3273
3274### BIC ###
3275
3276Bit clear immediate.
3277
3278    void bic(const VRegister& vd, const int imm8, const int left_shift = 0)
3279
3280
3281### BIC ###
3282
3283Bit clear.
3284
3285    void bic(const VRegister& vd, const VRegister& vn, const VRegister& vm)
3286
3287
3288### BIF ###
3289
3290Bitwise insert if false.
3291
3292    void bif(const VRegister& vd, const VRegister& vn, const VRegister& vm)
3293
3294
3295### BIT ###
3296
3297Bitwise insert if true.
3298
3299    void bit(const VRegister& vd, const VRegister& vn, const VRegister& vm)
3300
3301
3302### BSL ###
3303
3304Bitwise select.
3305
3306    void bsl(const VRegister& vd, const VRegister& vn, const VRegister& vm)
3307
3308
3309### CLS ###
3310
3311Count leading sign bits.
3312
3313    void cls(const VRegister& vd, const VRegister& vn)
3314
3315
3316### CLZ ###
3317
3318Count leading zero bits (vector).
3319
3320    void clz(const VRegister& vd, const VRegister& vn)
3321
3322
3323### CMEQ ###
3324
3325Compare bitwise to zero.
3326
3327    void cmeq(const VRegister& vd, const VRegister& vn, int value)
3328
3329
3330### CMEQ ###
3331
3332Compare equal.
3333
3334    void cmeq(const VRegister& vd, const VRegister& vn, const VRegister& vm)
3335
3336
3337### CMGE ###
3338
3339Compare signed greater than or equal to zero.
3340
3341    void cmge(const VRegister& vd, const VRegister& vn, int value)
3342
3343
3344### CMGE ###
3345
3346Compare signed greater than or equal.
3347
3348    void cmge(const VRegister& vd, const VRegister& vn, const VRegister& vm)
3349
3350
3351### CMGT ###
3352
3353Compare signed greater than zero.
3354
3355    void cmgt(const VRegister& vd, const VRegister& vn, int value)
3356
3357
3358### CMGT ###
3359
3360Compare signed greater than.
3361
3362    void cmgt(const VRegister& vd, const VRegister& vn, const VRegister& vm)
3363
3364
3365### CMHI ###
3366
3367Compare unsigned higher.
3368
3369    void cmhi(const VRegister& vd, const VRegister& vn, const VRegister& vm)
3370
3371
3372### CMHS ###
3373
3374Compare unsigned higher or same.
3375
3376    void cmhs(const VRegister& vd, const VRegister& vn, const VRegister& vm)
3377
3378
3379### CMLE ###
3380
3381Compare signed less than or equal to zero.
3382
3383    void cmle(const VRegister& vd, const VRegister& vn, int value)
3384
3385
3386### CMLT ###
3387
3388Compare signed less than zero.
3389
3390    void cmlt(const VRegister& vd, const VRegister& vn, int value)
3391
3392
3393### CMTST ###
3394
3395Compare bitwise test bits nonzero.
3396
3397    void cmtst(const VRegister& vd, const VRegister& vn, const VRegister& vm)
3398
3399
3400### CNT ###
3401
3402Population count per byte.
3403
3404    void cnt(const VRegister& vd, const VRegister& vn)
3405
3406
3407### DUP ###
3408
3409Duplicate general-purpose register to vector.
3410
3411    void dup(const VRegister& vd, const Register& rn)
3412
3413
3414### DUP ###
3415
3416Duplicate vector element to vector or scalar.
3417
3418    void dup(const VRegister& vd, const VRegister& vn, int vn_index)
3419
3420
3421### EOR ###
3422
3423Bitwise eor.
3424
3425    void eor(const VRegister& vd, const VRegister& vn, const VRegister& vm)
3426
3427
3428### EXT ###
3429
3430Extract vector from pair of vectors.
3431
3432    void ext(const VRegister& vd,
3433             const VRegister& vn,
3434             const VRegister& vm,
3435             int index)
3436
3437
3438### FABD ###
3439
3440FP absolute difference.
3441
3442    void fabd(const VRegister& vd, const VRegister& vn, const VRegister& vm)
3443
3444
3445### FABS ###
3446
3447FP absolute.
3448
3449    void fabs(const VRegister& vd, const VRegister& vn)
3450
3451
3452### FACGE ###
3453
3454FP absolute greater than or equal.
3455
3456    void facge(const VRegister& vd, const VRegister& vn, const VRegister& vm)
3457
3458
3459### FACGT ###
3460
3461FP absolute greater than.
3462
3463    void facgt(const VRegister& vd, const VRegister& vn, const VRegister& vm)
3464
3465
3466### FADD ###
3467
3468FP add.
3469
3470    void fadd(const VRegister& vd, const VRegister& vn, const VRegister& vm)
3471
3472
3473### FADDP ###
3474
3475FP pairwise add scalar.
3476
3477    void faddp(const VRegister& vd, const VRegister& vn)
3478
3479
3480### FADDP ###
3481
3482FP pairwise add vector.
3483
3484    void faddp(const VRegister& vd, const VRegister& vn, const VRegister& vm)
3485
3486
3487### FCADD ###
3488
3489FP complex add _(Armv8.3)_.
3490
3491    void fcadd(const VRegister& vd,
3492               const VRegister& vn,
3493               const VRegister& vm,
3494               int rot)
3495
3496
3497### FCCMP ###
3498
3499FP conditional compare.
3500
3501    void fccmp(const VRegister& vn,
3502               const VRegister& vm,
3503               StatusFlags nzcv,
3504               Condition cond)
3505
3506
3507### FCCMPE ###
3508
3509FP conditional signaling compare.
3510
3511    void fccmpe(const VRegister& vn,
3512                const VRegister& vm,
3513                StatusFlags nzcv,
3514                Condition cond)
3515
3516
3517### FCMEQ ###
3518
3519FP compare equal to zero.
3520
3521    void fcmeq(const VRegister& vd, const VRegister& vn, double imm)
3522
3523
3524### FCMEQ ###
3525
3526FP compare equal.
3527
3528    void fcmeq(const VRegister& vd, const VRegister& vn, const VRegister& vm)
3529
3530
3531### FCMGE ###
3532
3533FP greater than or equal to zero.
3534
3535    void fcmge(const VRegister& vd, const VRegister& vn, double imm)
3536
3537
3538### FCMGE ###
3539
3540FP greater than or equal.
3541
3542    void fcmge(const VRegister& vd, const VRegister& vn, const VRegister& vm)
3543
3544
3545### FCMGT ###
3546
3547FP greater than zero.
3548
3549    void fcmgt(const VRegister& vd, const VRegister& vn, double imm)
3550
3551
3552### FCMGT ###
3553
3554FP greater than.
3555
3556    void fcmgt(const VRegister& vd, const VRegister& vn, const VRegister& vm)
3557
3558
3559### FCMLA ###
3560
3561FP complex multiply accumulate (by element) _(Armv8.3)_.
3562
3563    void fcmla(const VRegister& vd,
3564               const VRegister& vn,
3565               const VRegister& vm,
3566               int vm_index,
3567               int rot)
3568
3569
3570### FCMLA ###
3571
3572FP complex multiply accumulate _(Armv8.3)_.
3573
3574    void fcmla(const VRegister& vd,
3575               const VRegister& vn,
3576               const VRegister& vm,
3577               int rot)
3578
3579
3580### FCMLE ###
3581
3582FP less than or equal to zero.
3583
3584    void fcmle(const VRegister& vd, const VRegister& vn, double imm)
3585
3586
3587### FCMLT ###
3588
3589FP less than to zero.
3590
3591    void fcmlt(const VRegister& vd, const VRegister& vn, double imm)
3592
3593
3594### FCMP ###
3595
3596FP compare immediate.
3597
3598    void fcmp(const VRegister& vn, double value)
3599
3600
3601### FCMP ###
3602
3603FP compare registers.
3604
3605    void fcmp(const VRegister& vn, const VRegister& vm)
3606
3607
3608### FCMPE ###
3609
3610FP signaling compare immediate.
3611
3612    void fcmpe(const VRegister& vn, double value)
3613
3614
3615### FCMPE ###
3616
3617FP signaling compare registers.
3618
3619    void fcmpe(const VRegister& vn, const VRegister& vm)
3620
3621
3622### FCSEL ###
3623
3624FP conditional select.
3625
3626    void fcsel(const VRegister& vd,
3627               const VRegister& vn,
3628               const VRegister& vm,
3629               Condition cond)
3630
3631
3632### FCVT ###
3633
3634FP convert between precisions.
3635
3636    void fcvt(const VRegister& vd, const VRegister& vn)
3637
3638
3639### FCVTAS ###
3640
3641FP convert to signed integer, nearest with ties to away.
3642
3643    void fcvtas(const Register& rd, const VRegister& vn)
3644
3645
3646### FCVTAS ###
3647
3648FP convert to signed integer, nearest with ties to away.
3649
3650    void fcvtas(const VRegister& vd, const VRegister& vn)
3651
3652
3653### FCVTAU ###
3654
3655FP convert to unsigned integer, nearest with ties to away.
3656
3657    void fcvtau(const Register& rd, const VRegister& vn)
3658
3659
3660### FCVTAU ###
3661
3662FP convert to unsigned integer, nearest with ties to away.
3663
3664    void fcvtau(const VRegister& vd, const VRegister& vn)
3665
3666
3667### FCVTL ###
3668
3669FP convert to higher precision.
3670
3671    void fcvtl(const VRegister& vd, const VRegister& vn)
3672
3673
3674### FCVTL2 ###
3675
3676FP convert to higher precision (second part).
3677
3678    void fcvtl2(const VRegister& vd, const VRegister& vn)
3679
3680
3681### FCVTMS ###
3682
3683FP convert to signed integer, round towards -infinity.
3684
3685    void fcvtms(const Register& rd, const VRegister& vn)
3686
3687
3688### FCVTMS ###
3689
3690FP convert to signed integer, round towards -infinity.
3691
3692    void fcvtms(const VRegister& vd, const VRegister& vn)
3693
3694
3695### FCVTMU ###
3696
3697FP convert to unsigned integer, round towards -infinity.
3698
3699    void fcvtmu(const Register& rd, const VRegister& vn)
3700
3701
3702### FCVTMU ###
3703
3704FP convert to unsigned integer, round towards -infinity.
3705
3706    void fcvtmu(const VRegister& vd, const VRegister& vn)
3707
3708
3709### FCVTN ###
3710
3711FP convert to lower precision.
3712
3713    void fcvtn(const VRegister& vd, const VRegister& vn)
3714
3715
3716### FCVTN2 ###
3717
3718FP convert to lower prevision (second part).
3719
3720    void fcvtn2(const VRegister& vd, const VRegister& vn)
3721
3722
3723### FCVTNS ###
3724
3725FP convert to signed integer, nearest with ties to even.
3726
3727    void fcvtns(const Register& rd, const VRegister& vn)
3728
3729
3730### FCVTNS ###
3731
3732FP convert to signed integer, nearest with ties to even.
3733
3734    void fcvtns(const VRegister& rd, const VRegister& vn)
3735
3736
3737### FCVTNU ###
3738
3739FP convert to unsigned integer, nearest with ties to even.
3740
3741    void fcvtnu(const Register& rd, const VRegister& vn)
3742
3743
3744### FCVTNU ###
3745
3746FP convert to unsigned integer, nearest with ties to even.
3747
3748    void fcvtnu(const VRegister& rd, const VRegister& vn)
3749
3750
3751### FCVTPS ###
3752
3753FP convert to signed integer, round towards +infinity.
3754
3755    void fcvtps(const Register& rd, const VRegister& vn)
3756
3757
3758### FCVTPS ###
3759
3760FP convert to signed integer, round towards +infinity.
3761
3762    void fcvtps(const VRegister& vd, const VRegister& vn)
3763
3764
3765### FCVTPU ###
3766
3767FP convert to unsigned integer, round towards +infinity.
3768
3769    void fcvtpu(const Register& rd, const VRegister& vn)
3770
3771
3772### FCVTPU ###
3773
3774FP convert to unsigned integer, round towards +infinity.
3775
3776    void fcvtpu(const VRegister& vd, const VRegister& vn)
3777
3778
3779### FCVTXN ###
3780
3781FP convert to lower precision, rounding to odd.
3782
3783    void fcvtxn(const VRegister& vd, const VRegister& vn)
3784
3785
3786### FCVTXN2 ###
3787
3788FP convert to lower precision, rounding to odd (second part).
3789
3790    void fcvtxn2(const VRegister& vd, const VRegister& vn)
3791
3792
3793### FCVTZS ###
3794
3795FP convert to signed integer or fixed-point, round towards zero.
3796
3797    void fcvtzs(const Register& rd, const VRegister& vn, int fbits = 0)
3798
3799
3800### FCVTZS ###
3801
3802FP convert to signed integer or fixed-point, round towards zero.
3803
3804    void fcvtzs(const VRegister& vd, const VRegister& vn, int fbits = 0)
3805
3806
3807### FCVTZU ###
3808
3809FP convert to unsigned integer or fixed-point, round towards zero.
3810
3811    void fcvtzu(const Register& rd, const VRegister& vn, int fbits = 0)
3812
3813
3814### FCVTZU ###
3815
3816FP convert to unsigned integer or fixed-point, round towards zero.
3817
3818    void fcvtzu(const VRegister& vd, const VRegister& vn, int fbits = 0)
3819
3820
3821### FDIV ###
3822
3823FP divide.
3824
3825    void fdiv(const VRegister& vd, const VRegister& fn, const VRegister& vm)
3826
3827
3828### FJCVTZS ###
3829
3830FP JavaScript convert to signed integer, rounding toward zero _(Armv8.3)_.
3831
3832    void fjcvtzs(const Register& rd, const VRegister& vn)
3833
3834
3835### FMADD ###
3836
3837FP fused multiply-add.
3838
3839    void fmadd(const VRegister& vd,
3840               const VRegister& vn,
3841               const VRegister& vm,
3842               const VRegister& va)
3843
3844
3845### FMAX ###
3846
3847FP maximum.
3848
3849    void fmax(const VRegister& vd, const VRegister& fn, const VRegister& vm)
3850
3851
3852### FMAXNM ###
3853
3854FP maximum number.
3855
3856    void fmaxnm(const VRegister& vd, const VRegister& fn, const VRegister& vm)
3857
3858
3859### FMAXNMP ###
3860
3861FP pairwise maximum number scalar.
3862
3863    void fmaxnmp(const VRegister& vd, const VRegister& vn)
3864
3865
3866### FMAXNMP ###
3867
3868FP pairwise maximum number vector.
3869
3870    void fmaxnmp(const VRegister& vd, const VRegister& vn, const VRegister& vm)
3871
3872
3873### FMAXNMV ###
3874
3875FP maximum number across vector.
3876
3877    void fmaxnmv(const VRegister& vd, const VRegister& vn)
3878
3879
3880### FMAXP ###
3881
3882FP pairwise maximum scalar.
3883
3884    void fmaxp(const VRegister& vd, const VRegister& vn)
3885
3886
3887### FMAXP ###
3888
3889FP pairwise maximum vector.
3890
3891    void fmaxp(const VRegister& vd, const VRegister& vn, const VRegister& vm)
3892
3893
3894### FMAXV ###
3895
3896FP maximum across vector.
3897
3898    void fmaxv(const VRegister& vd, const VRegister& vn)
3899
3900
3901### FMIN ###
3902
3903FP minimum.
3904
3905    void fmin(const VRegister& vd, const VRegister& fn, const VRegister& vm)
3906
3907
3908### FMINNM ###
3909
3910FP minimum number.
3911
3912    void fminnm(const VRegister& vd, const VRegister& fn, const VRegister& vm)
3913
3914
3915### FMINNMP ###
3916
3917FP pairwise minimum number scalar.
3918
3919    void fminnmp(const VRegister& vd, const VRegister& vn)
3920
3921
3922### FMINNMP ###
3923
3924FP pairwise minimum number vector.
3925
3926    void fminnmp(const VRegister& vd, const VRegister& vn, const VRegister& vm)
3927
3928
3929### FMINNMV ###
3930
3931FP minimum number across vector.
3932
3933    void fminnmv(const VRegister& vd, const VRegister& vn)
3934
3935
3936### FMINP ###
3937
3938FP pairwise minimum scalar.
3939
3940    void fminp(const VRegister& vd, const VRegister& vn)
3941
3942
3943### FMINP ###
3944
3945FP pairwise minimum vector.
3946
3947    void fminp(const VRegister& vd, const VRegister& vn, const VRegister& vm)
3948
3949
3950### FMINV ###
3951
3952FP minimum across vector.
3953
3954    void fminv(const VRegister& vd, const VRegister& vn)
3955
3956
3957### FMLA ###
3958
3959FP fused multiply-add to accumulator by element.
3960
3961    void fmla(const VRegister& vd,
3962              const VRegister& vn,
3963              const VRegister& vm,
3964              int vm_index)
3965
3966
3967### FMLA ###
3968
3969FP vector multiply accumulate.
3970
3971    void fmla(const VRegister& vd, const VRegister& vn, const VRegister& vm)
3972
3973
3974### FMLAL ###
3975
3976FP fused multiply-add long to accumulator by element.
3977
3978    void fmlal(const VRegister& vd,
3979               const VRegister& vn,
3980               const VRegister& vm,
3981               int vm_index)
3982
3983
3984### FMLAL ###
3985
3986FP fused multiply-add long to accumulator.
3987
3988    void fmlal(const VRegister& vd, const VRegister& vn, const VRegister& vm)
3989
3990
3991### FMLAL2 ###
3992
3993FP fused multiply-add long to accumulator (second part).
3994
3995    void fmlal2(const VRegister& vd, const VRegister& vn, const VRegister& vm)
3996
3997
3998### FMLAL2 ###
3999
4000FP fused multiply-add long to accumulator by element (second part).
4001
4002    void fmlal2(const VRegister& vd,
4003                const VRegister& vn,
4004                const VRegister& vm,
4005                int vm_index)
4006
4007
4008### FMLS ###
4009
4010FP fused multiply-sub from accumulator by element.
4011
4012    void fmls(const VRegister& vd,
4013              const VRegister& vn,
4014              const VRegister& vm,
4015              int vm_index)
4016
4017
4018### FMLS ###
4019
4020FP vector multiply subtract.
4021
4022    void fmls(const VRegister& vd, const VRegister& vn, const VRegister& vm)
4023
4024
4025### FMLSL ###
4026
4027FP fused multiply-subtract long to accumulator by element.
4028
4029    void fmlsl(const VRegister& vd,
4030               const VRegister& vn,
4031               const VRegister& vm,
4032               int vm_index)
4033
4034
4035### FMLSL ###
4036
4037FP fused multiply-subtract long to accumulator.
4038
4039    void fmlsl(const VRegister& vd, const VRegister& vn, const VRegister& vm)
4040
4041
4042### FMLSL2 ###
4043
4044FP fused multiply-subtract long to accumulator (second part).
4045
4046    void fmlsl2(const VRegister& vd, const VRegister& vn, const VRegister& vm)
4047
4048
4049### FMLSL2 ###
4050
4051FP fused multiply-subtract long to accumulator by element (second part).
4052
4053    void fmlsl2(const VRegister& vd,
4054                const VRegister& vn,
4055                const VRegister& vm,
4056                int vm_index)
4057
4058
4059### FMOV ###
4060
4061Move 64-bit register to top half of 128-bit FP register.
4062
4063    void fmov(const VRegister& vd, int index, const Register& rn)
4064
4065
4066### FMOV ###
4067
4068Move FP register to FP register.
4069
4070    void fmov(const VRegister& vd, const VRegister& fn)
4071
4072
4073### FMOV ###
4074
4075Move FP register to register.
4076
4077    void fmov(const Register& rd, const VRegister& fn)
4078
4079
4080### FMOV ###
4081
4082Move double precision immediate to FP register.
4083
4084    void fmov(const VRegister& vd, double imm)
4085
4086
4087### FMOV ###
4088
4089Move half precision immediate to FP register _(Armv8.2)_.
4090
4091    void fmov(const VRegister& vd, Float16 imm)
4092
4093
4094### FMOV ###
4095
4096Move register to FP register.
4097
4098    void fmov(const VRegister& vd, const Register& rn)
4099
4100
4101### FMOV ###
4102
4103Move single precision immediate to FP register.
4104
4105    void fmov(const VRegister& vd, float imm)
4106
4107
4108### FMOV ###
4109
4110Move top half of 128-bit FP register to 64-bit register.
4111
4112    void fmov(const Register& rd, const VRegister& vn, int index)
4113
4114
4115### FMSUB ###
4116
4117FP fused multiply-subtract.
4118
4119    void fmsub(const VRegister& vd,
4120               const VRegister& vn,
4121               const VRegister& vm,
4122               const VRegister& va)
4123
4124
4125### FMUL ###
4126
4127FP multiply by element.
4128
4129    void fmul(const VRegister& vd,
4130              const VRegister& vn,
4131              const VRegister& vm,
4132              int vm_index)
4133
4134
4135### FMUL ###
4136
4137FP multiply.
4138
4139    void fmul(const VRegister& vd, const VRegister& vn, const VRegister& vm)
4140
4141
4142### FMULX ###
4143
4144FP multiply extended by element.
4145
4146    void fmulx(const VRegister& vd,
4147               const VRegister& vn,
4148               const VRegister& vm,
4149               int vm_index)
4150
4151
4152### FMULX ###
4153
4154FP vector multiply extended.
4155
4156    void fmulx(const VRegister& vd, const VRegister& vn, const VRegister& vm)
4157
4158
4159### FNEG ###
4160
4161FP negate.
4162
4163    void fneg(const VRegister& vd, const VRegister& vn)
4164
4165
4166### FNMADD ###
4167
4168FP fused multiply-add and negate.
4169
4170    void fnmadd(const VRegister& vd,
4171                const VRegister& vn,
4172                const VRegister& vm,
4173                const VRegister& va)
4174
4175
4176### FNMSUB ###
4177
4178FP fused multiply-subtract and negate.
4179
4180    void fnmsub(const VRegister& vd,
4181                const VRegister& vn,
4182                const VRegister& vm,
4183                const VRegister& va)
4184
4185
4186### FNMUL ###
4187
4188FP multiply-negate scalar.
4189
4190    void fnmul(const VRegister& vd, const VRegister& vn, const VRegister& vm)
4191
4192
4193### FRECPE ###
4194
4195FP reciprocal estimate.
4196
4197    void frecpe(const VRegister& vd, const VRegister& vn)
4198
4199
4200### FRECPS ###
4201
4202FP reciprocal step.
4203
4204    void frecps(const VRegister& vd, const VRegister& vn, const VRegister& vm)
4205
4206
4207### FRECPX ###
4208
4209FP reciprocal exponent scalar.
4210
4211    void frecpx(const VRegister& vd, const VRegister& vn)
4212
4213
4214### FRINTA ###
4215
4216FP round to integer, nearest with ties to away.
4217
4218    void frinta(const VRegister& vd, const VRegister& vn)
4219
4220
4221### FRINTI ###
4222
4223FP round to integer, implicit rounding.
4224
4225    void frinti(const VRegister& vd, const VRegister& vn)
4226
4227
4228### FRINTM ###
4229
4230FP round to integer, toward minus infinity.
4231
4232    void frintm(const VRegister& vd, const VRegister& vn)
4233
4234
4235### FRINTN ###
4236
4237FP round to integer, nearest with ties to even.
4238
4239    void frintn(const VRegister& vd, const VRegister& vn)
4240
4241
4242### FRINTP ###
4243
4244FP round to integer, toward plus infinity.
4245
4246    void frintp(const VRegister& vd, const VRegister& vn)
4247
4248
4249### FRINTX ###
4250
4251FP round to integer, exact, implicit rounding.
4252
4253    void frintx(const VRegister& vd, const VRegister& vn)
4254
4255
4256### FRINTZ ###
4257
4258FP round to integer, towards zero.
4259
4260    void frintz(const VRegister& vd, const VRegister& vn)
4261
4262
4263### FRSQRTE ###
4264
4265FP reciprocal square root estimate.
4266
4267    void frsqrte(const VRegister& vd, const VRegister& vn)
4268
4269
4270### FRSQRTS ###
4271
4272FP reciprocal square root step.
4273
4274    void frsqrts(const VRegister& vd, const VRegister& vn, const VRegister& vm)
4275
4276
4277### FSQRT ###
4278
4279FP square root.
4280
4281    void fsqrt(const VRegister& vd, const VRegister& vn)
4282
4283
4284### FSUB ###
4285
4286FP subtract.
4287
4288    void fsub(const VRegister& vd, const VRegister& vn, const VRegister& vm)
4289
4290
4291### INS ###
4292
4293Insert vector element from another vector element.
4294
4295    void ins(const VRegister& vd,
4296             int vd_index,
4297             const VRegister& vn,
4298             int vn_index)
4299
4300
4301### INS ###
4302
4303Insert vector element from general-purpose register.
4304
4305    void ins(const VRegister& vd, int vd_index, const Register& rn)
4306
4307
4308### LD1 ###
4309
4310One-element single structure load to one lane.
4311
4312    void ld1(const VRegister& vt, int lane, const MemOperand& src)
4313
4314
4315### LD1 ###
4316
4317One-element structure load to four registers.
4318
4319    void ld1(const VRegister& vt,
4320             const VRegister& vt2,
4321             const VRegister& vt3,
4322             const VRegister& vt4,
4323             const MemOperand& src)
4324
4325
4326### LD1 ###
4327
4328One-element structure load to one register.
4329
4330    void ld1(const VRegister& vt, const MemOperand& src)
4331
4332
4333### LD1 ###
4334
4335One-element structure load to three registers.
4336
4337    void ld1(const VRegister& vt,
4338             const VRegister& vt2,
4339             const VRegister& vt3,
4340             const MemOperand& src)
4341
4342
4343### LD1 ###
4344
4345One-element structure load to two registers.
4346
4347    void ld1(const VRegister& vt, const VRegister& vt2, const MemOperand& src)
4348
4349
4350### LD1R ###
4351
4352One-element single structure load to all lanes.
4353
4354    void ld1r(const VRegister& vt, const MemOperand& src)
4355
4356
4357### LD2 ###
4358
4359Two-element single structure load to one lane.
4360
4361    void ld2(const VRegister& vt,
4362             const VRegister& vt2,
4363             int lane,
4364             const MemOperand& src)
4365
4366
4367### LD2 ###
4368
4369Two-element structure load.
4370
4371    void ld2(const VRegister& vt, const VRegister& vt2, const MemOperand& src)
4372
4373
4374### LD2R ###
4375
4376Two-element single structure load to all lanes.
4377
4378    void ld2r(const VRegister& vt, const VRegister& vt2, const MemOperand& src)
4379
4380
4381### LD3 ###
4382
4383Three-element single structure load to one lane.
4384
4385    void ld3(const VRegister& vt,
4386             const VRegister& vt2,
4387             const VRegister& vt3,
4388             int lane,
4389             const MemOperand& src)
4390
4391
4392### LD3 ###
4393
4394Three-element structure load.
4395
4396    void ld3(const VRegister& vt,
4397             const VRegister& vt2,
4398             const VRegister& vt3,
4399             const MemOperand& src)
4400
4401
4402### LD3R ###
4403
4404Three-element single structure load to all lanes.
4405
4406    void ld3r(const VRegister& vt,
4407              const VRegister& vt2,
4408              const VRegister& vt3,
4409              const MemOperand& src)
4410
4411
4412### LD4 ###
4413
4414Four-element single structure load to one lane.
4415
4416    void ld4(const VRegister& vt,
4417             const VRegister& vt2,
4418             const VRegister& vt3,
4419             const VRegister& vt4,
4420             int lane,
4421             const MemOperand& src)
4422
4423
4424### LD4 ###
4425
4426Four-element structure load.
4427
4428    void ld4(const VRegister& vt,
4429             const VRegister& vt2,
4430             const VRegister& vt3,
4431             const VRegister& vt4,
4432             const MemOperand& src)
4433
4434
4435### LD4R ###
4436
4437Four-element single structure load to all lanes.
4438
4439    void ld4r(const VRegister& vt,
4440              const VRegister& vt2,
4441              const VRegister& vt3,
4442              const VRegister& vt4,
4443              const MemOperand& src)
4444
4445
4446### MLA ###
4447
4448Multiply-add by scalar element.
4449
4450    void mla(const VRegister& vd,
4451             const VRegister& vn,
4452             const VRegister& vm,
4453             int vm_index)
4454
4455
4456### MLA ###
4457
4458Multiply-add to accumulator.
4459
4460    void mla(const VRegister& vd, const VRegister& vn, const VRegister& vm)
4461
4462
4463### MLS ###
4464
4465Multiply-subtract by scalar element.
4466
4467    void mls(const VRegister& vd,
4468             const VRegister& vn,
4469             const VRegister& vm,
4470             int vm_index)
4471
4472
4473### MLS ###
4474
4475Multiply-subtract to accumulator.
4476
4477    void mls(const VRegister& vd, const VRegister& vn, const VRegister& vm)
4478
4479
4480### MOV ###
4481
4482Move general-purpose register to a vector element.
4483
4484    void mov(const VRegister& vd, int vd_index, const Register& rn)
4485
4486
4487### MOV ###
4488
4489Move register to register.
4490
4491    void mov(const VRegister& vd, const VRegister& vn)
4492
4493
4494### MOV ###
4495
4496Move vector element to another vector element.
4497
4498    void mov(const VRegister& vd,
4499             int vd_index,
4500             const VRegister& vn,
4501             int vn_index)
4502
4503
4504### MOV ###
4505
4506Move vector element to general-purpose register.
4507
4508    void mov(const Register& rd, const VRegister& vn, int vn_index)
4509
4510
4511### MOV ###
4512
4513Move vector element to scalar.
4514
4515    void mov(const VRegister& vd, const VRegister& vn, int vn_index)
4516
4517
4518### MOVI ###
4519
4520Vector move immediate.
4521
4522    void movi(const VRegister& vd,
4523              const uint64_t imm,
4524              Shift shift = LSL,
4525              const int shift_amount = 0)
4526
4527
4528### MUL ###
4529
4530Multiply by scalar element.
4531
4532    void mul(const VRegister& vd,
4533             const VRegister& vn,
4534             const VRegister& vm,
4535             int vm_index)
4536
4537
4538### MUL ###
4539
4540Multiply.
4541
4542    void mul(const VRegister& vd, const VRegister& vn, const VRegister& vm)
4543
4544
4545### MVN ###
4546
4547Bitwise not.
4548
4549    void mvn(const VRegister& vd, const VRegister& vn)
4550
4551
4552### MVNI ###
4553
4554Vector move inverted immediate.
4555
4556    void mvni(const VRegister& vd,
4557              const int imm8,
4558              Shift shift = LSL,
4559              const int shift_amount = 0)
4560
4561
4562### NEG ###
4563
4564Negate.
4565
4566    void neg(const VRegister& vd, const VRegister& vn)
4567
4568
4569### NOT ###
4570
4571Bitwise not.
4572
4573    void not_(const VRegister& vd, const VRegister& vn)
4574
4575
4576### ORN ###
4577
4578Bitwise orn.
4579
4580    void orn(const VRegister& vd, const VRegister& vn, const VRegister& vm)
4581
4582
4583### ORR ###
4584
4585Bitwise or immediate.
4586
4587    void orr(const VRegister& vd, const int imm8, const int left_shift = 0)
4588
4589
4590### ORR ###
4591
4592Bitwise or.
4593
4594    void orr(const VRegister& vd, const VRegister& vn, const VRegister& vm)
4595
4596
4597### PMUL ###
4598
4599Polynomial multiply.
4600
4601    void pmul(const VRegister& vd, const VRegister& vn, const VRegister& vm)
4602
4603
4604### PMULL ###
4605
4606Polynomial multiply long.
4607
4608    void pmull(const VRegister& vd, const VRegister& vn, const VRegister& vm)
4609
4610
4611### PMULL2 ###
4612
4613Polynomial multiply long (second part).
4614
4615    void pmull2(const VRegister& vd, const VRegister& vn, const VRegister& vm)
4616
4617
4618### RADDHN ###
4619
4620Rounding add narrow returning high half.
4621
4622    void raddhn(const VRegister& vd, const VRegister& vn, const VRegister& vm)
4623
4624
4625### RADDHN2 ###
4626
4627Rounding add narrow returning high half (second part).
4628
4629    void raddhn2(const VRegister& vd, const VRegister& vn, const VRegister& vm)
4630
4631
4632### RBIT ###
4633
4634Reverse bit order.
4635
4636    void rbit(const VRegister& vd, const VRegister& vn)
4637
4638
4639### REV16 ###
4640
4641Reverse elements in 16-bit halfwords.
4642
4643    void rev16(const VRegister& vd, const VRegister& vn)
4644
4645
4646### REV32 ###
4647
4648Reverse elements in 32-bit words.
4649
4650    void rev32(const VRegister& vd, const VRegister& vn)
4651
4652
4653### REV64 ###
4654
4655Reverse elements in 64-bit doublewords.
4656
4657    void rev64(const VRegister& vd, const VRegister& vn)
4658
4659
4660### RSHRN ###
4661
4662Rounding shift right narrow by immediate.
4663
4664    void rshrn(const VRegister& vd, const VRegister& vn, int shift)
4665
4666
4667### RSHRN2 ###
4668
4669Rounding shift right narrow by immediate (second part).
4670
4671    void rshrn2(const VRegister& vd, const VRegister& vn, int shift)
4672
4673
4674### RSUBHN ###
4675
4676Rounding subtract narrow returning high half.
4677
4678    void rsubhn(const VRegister& vd, const VRegister& vn, const VRegister& vm)
4679
4680
4681### RSUBHN2 ###
4682
4683Rounding subtract narrow returning high half (second part).
4684
4685    void rsubhn2(const VRegister& vd, const VRegister& vn, const VRegister& vm)
4686
4687
4688### SABA ###
4689
4690Signed absolute difference and accumulate.
4691
4692    void saba(const VRegister& vd, const VRegister& vn, const VRegister& vm)
4693
4694
4695### SABAL ###
4696
4697Signed absolute difference and accumulate long.
4698
4699    void sabal(const VRegister& vd, const VRegister& vn, const VRegister& vm)
4700
4701
4702### SABAL2 ###
4703
4704Signed absolute difference and accumulate long (second part).
4705
4706    void sabal2(const VRegister& vd, const VRegister& vn, const VRegister& vm)
4707
4708
4709### SABD ###
4710
4711Signed absolute difference.
4712
4713    void sabd(const VRegister& vd, const VRegister& vn, const VRegister& vm)
4714
4715
4716### SABDL ###
4717
4718Signed absolute difference long.
4719
4720    void sabdl(const VRegister& vd, const VRegister& vn, const VRegister& vm)
4721
4722
4723### SABDL2 ###
4724
4725Signed absolute difference long (second part).
4726
4727    void sabdl2(const VRegister& vd, const VRegister& vn, const VRegister& vm)
4728
4729
4730### SADALP ###
4731
4732Signed pairwise long add and accumulate.
4733
4734    void sadalp(const VRegister& vd, const VRegister& vn)
4735
4736
4737### SADDL ###
4738
4739Signed add long.
4740
4741    void saddl(const VRegister& vd, const VRegister& vn, const VRegister& vm)
4742
4743
4744### SADDL2 ###
4745
4746Signed add long (second part).
4747
4748    void saddl2(const VRegister& vd, const VRegister& vn, const VRegister& vm)
4749
4750
4751### SADDLP ###
4752
4753Signed pairwise long add.
4754
4755    void saddlp(const VRegister& vd, const VRegister& vn)
4756
4757
4758### SADDLV ###
4759
4760Signed add long across vector.
4761
4762    void saddlv(const VRegister& vd, const VRegister& vn)
4763
4764
4765### SADDW ###
4766
4767Signed add wide.
4768
4769    void saddw(const VRegister& vd, const VRegister& vn, const VRegister& vm)
4770
4771
4772### SADDW2 ###
4773
4774Signed add wide (second part).
4775
4776    void saddw2(const VRegister& vd, const VRegister& vn, const VRegister& vm)
4777
4778
4779### SCVTF ###
4780
4781Convert signed integer or fixed point to FP.
4782
4783    void scvtf(const VRegister& fd, const Register& rn, int fbits = 0)
4784
4785
4786### SCVTF ###
4787
4788Convert signed integer or fixed-point to FP.
4789
4790    void scvtf(const VRegister& fd, const VRegister& vn, int fbits = 0)
4791
4792
4793### SDOT ###
4794
4795Signed dot product _(Armv8.2)_.
4796
4797    void sdot(const VRegister& vd, const VRegister& vn, const VRegister& vm)
4798
4799
4800### SDOT ###
4801
4802Signed dot product by element _(Armv8.2)_.
4803
4804    void sdot(const VRegister& vd,
4805              const VRegister& vn,
4806              const VRegister& vm,
4807              int vm_index)
4808
4809
4810### SHADD ###
4811
4812Signed halving add.
4813
4814    void shadd(const VRegister& vd, const VRegister& vn, const VRegister& vm)
4815
4816
4817### SHL ###
4818
4819Shift left by immediate.
4820
4821    void shl(const VRegister& vd, const VRegister& vn, int shift)
4822
4823
4824### SHLL ###
4825
4826Shift left long by element size.
4827
4828    void shll(const VRegister& vd, const VRegister& vn, int shift)
4829
4830
4831### SHLL2 ###
4832
4833Shift left long by element size (second part).
4834
4835    void shll2(const VRegister& vd, const VRegister& vn, int shift)
4836
4837
4838### SHRN ###
4839
4840Shift right narrow by immediate.
4841
4842    void shrn(const VRegister& vd, const VRegister& vn, int shift)
4843
4844
4845### SHRN2 ###
4846
4847Shift right narrow by immediate (second part).
4848
4849    void shrn2(const VRegister& vd, const VRegister& vn, int shift)
4850
4851
4852### SHSUB ###
4853
4854Signed halving sub.
4855
4856    void shsub(const VRegister& vd, const VRegister& vn, const VRegister& vm)
4857
4858
4859### SLI ###
4860
4861Shift left by immediate and insert.
4862
4863    void sli(const VRegister& vd, const VRegister& vn, int shift)
4864
4865
4866### SMAX ###
4867
4868Signed maximum.
4869
4870    void smax(const VRegister& vd, const VRegister& vn, const VRegister& vm)
4871
4872
4873### SMAXP ###
4874
4875Signed pairwise maximum.
4876
4877    void smaxp(const VRegister& vd, const VRegister& vn, const VRegister& vm)
4878
4879
4880### SMAXV ###
4881
4882Signed maximum across vector.
4883
4884    void smaxv(const VRegister& vd, const VRegister& vn)
4885
4886
4887### SMIN ###
4888
4889Signed minimum.
4890
4891    void smin(const VRegister& vd, const VRegister& vn, const VRegister& vm)
4892
4893
4894### SMINP ###
4895
4896Signed minimum pairwise.
4897
4898    void sminp(const VRegister& vd, const VRegister& vn, const VRegister& vm)
4899
4900
4901### SMINV ###
4902
4903Signed minimum across vector.
4904
4905    void sminv(const VRegister& vd, const VRegister& vn)
4906
4907
4908### SMLAL ###
4909
4910Signed long multiply-add by scalar element.
4911
4912    void smlal(const VRegister& vd,
4913               const VRegister& vn,
4914               const VRegister& vm,
4915               int vm_index)
4916
4917
4918### SMLAL ###
4919
4920Signed long multiply-add.
4921
4922    void smlal(const VRegister& vd, const VRegister& vn, const VRegister& vm)
4923
4924
4925### SMLAL2 ###
4926
4927Signed long multiply-add (second part).
4928
4929    void smlal2(const VRegister& vd, const VRegister& vn, const VRegister& vm)
4930
4931
4932### SMLAL2 ###
4933
4934Signed long multiply-add by scalar element (second part).
4935
4936    void smlal2(const VRegister& vd,
4937                const VRegister& vn,
4938                const VRegister& vm,
4939                int vm_index)
4940
4941
4942### SMLSL ###
4943
4944Signed long multiply-sub by scalar element.
4945
4946    void smlsl(const VRegister& vd,
4947               const VRegister& vn,
4948               const VRegister& vm,
4949               int vm_index)
4950
4951
4952### SMLSL ###
4953
4954Signed long multiply-sub.
4955
4956    void smlsl(const VRegister& vd, const VRegister& vn, const VRegister& vm)
4957
4958
4959### SMLSL2 ###
4960
4961Signed long multiply-sub (second part).
4962
4963    void smlsl2(const VRegister& vd, const VRegister& vn, const VRegister& vm)
4964
4965
4966### SMLSL2 ###
4967
4968Signed long multiply-sub by scalar element (second part).
4969
4970    void smlsl2(const VRegister& vd,
4971                const VRegister& vn,
4972                const VRegister& vm,
4973                int vm_index)
4974
4975
4976### SMOV ###
4977
4978Signed move vector element to general-purpose register.
4979
4980    void smov(const Register& rd, const VRegister& vn, int vn_index)
4981
4982
4983### SMULL ###
4984
4985Signed long multiply by scalar element.
4986
4987    void smull(const VRegister& vd,
4988               const VRegister& vn,
4989               const VRegister& vm,
4990               int vm_index)
4991
4992
4993### SMULL ###
4994
4995Signed long multiply.
4996
4997    void smull(const VRegister& vd, const VRegister& vn, const VRegister& vm)
4998
4999
5000### SMULL2 ###
5001
5002Signed long multiply (second part).
5003
5004    void smull2(const VRegister& vd, const VRegister& vn, const VRegister& vm)
5005
5006
5007### SMULL2 ###
5008
5009Signed long multiply by scalar element (second part).
5010
5011    void smull2(const VRegister& vd,
5012                const VRegister& vn,
5013                const VRegister& vm,
5014                int vm_index)
5015
5016
5017### SQABS ###
5018
5019Signed saturating absolute value.
5020
5021    void sqabs(const VRegister& vd, const VRegister& vn)
5022
5023
5024### SQADD ###
5025
5026Signed saturating add.
5027
5028    void sqadd(const VRegister& vd, const VRegister& vn, const VRegister& vm)
5029
5030
5031### SQDMLAL ###
5032
5033Signed saturating doubling long multiply-add by element.
5034
5035    void sqdmlal(const VRegister& vd,
5036                 const VRegister& vn,
5037                 const VRegister& vm,
5038                 int vm_index)
5039
5040
5041### SQDMLAL ###
5042
5043Signed saturating doubling long multiply-add.
5044
5045    void sqdmlal(const VRegister& vd, const VRegister& vn, const VRegister& vm)
5046
5047
5048### SQDMLAL2 ###
5049
5050Signed saturating doubling long multiply-add (second part).
5051
5052    void sqdmlal2(const VRegister& vd, const VRegister& vn, const VRegister& vm)
5053
5054
5055### SQDMLAL2 ###
5056
5057Signed saturating doubling long multiply-add by element (second part).
5058
5059    void sqdmlal2(const VRegister& vd,
5060                  const VRegister& vn,
5061                  const VRegister& vm,
5062                  int vm_index)
5063
5064
5065### SQDMLSL ###
5066
5067Signed saturating doubling long multiply-sub by element.
5068
5069    void sqdmlsl(const VRegister& vd,
5070                 const VRegister& vn,
5071                 const VRegister& vm,
5072                 int vm_index)
5073
5074
5075### SQDMLSL ###
5076
5077Signed saturating doubling long multiply-subtract.
5078
5079    void sqdmlsl(const VRegister& vd, const VRegister& vn, const VRegister& vm)
5080
5081
5082### SQDMLSL2 ###
5083
5084Signed saturating doubling long multiply-sub by element (second part).
5085
5086    void sqdmlsl2(const VRegister& vd,
5087                  const VRegister& vn,
5088                  const VRegister& vm,
5089                  int vm_index)
5090
5091
5092### SQDMLSL2 ###
5093
5094Signed saturating doubling long multiply-subtract (second part).
5095
5096    void sqdmlsl2(const VRegister& vd, const VRegister& vn, const VRegister& vm)
5097
5098
5099### SQDMULH ###
5100
5101Signed saturating doubling multiply element returning high half.
5102
5103    void sqdmulh(const VRegister& vd,
5104                 const VRegister& vn,
5105                 const VRegister& vm,
5106                 int vm_index)
5107
5108
5109### SQDMULH ###
5110
5111Signed saturating doubling multiply returning high half.
5112
5113    void sqdmulh(const VRegister& vd, const VRegister& vn, const VRegister& vm)
5114
5115
5116### SQDMULL ###
5117
5118Signed saturating double long multiply by element.
5119
5120    void sqdmull(const VRegister& vd,
5121                 const VRegister& vn,
5122                 const VRegister& vm,
5123                 int vm_index)
5124
5125
5126### SQDMULL ###
5127
5128Signed saturating doubling long multiply.
5129
5130    void sqdmull(const VRegister& vd, const VRegister& vn, const VRegister& vm)
5131
5132
5133### SQDMULL2 ###
5134
5135Signed saturating double long multiply by element (second part).
5136
5137    void sqdmull2(const VRegister& vd,
5138                  const VRegister& vn,
5139                  const VRegister& vm,
5140                  int vm_index)
5141
5142
5143### SQDMULL2 ###
5144
5145Signed saturating doubling long multiply (second part).
5146
5147    void sqdmull2(const VRegister& vd, const VRegister& vn, const VRegister& vm)
5148
5149
5150### SQNEG ###
5151
5152Signed saturating negate.
5153
5154    void sqneg(const VRegister& vd, const VRegister& vn)
5155
5156
5157### SQRDMLAH ###
5158
5159Signed saturating rounding doubling multiply accumulate element returning high half _(Armv8.1)_.
5160
5161    void sqrdmlah(const VRegister& vd,
5162                  const VRegister& vn,
5163                  const VRegister& vm,
5164                  int vm_index)
5165
5166
5167### SQRDMLAH ###
5168
5169Signed saturating rounding doubling multiply accumulate returning high half _(Armv8.1)_.
5170
5171    void sqrdmlah(const VRegister& vd, const VRegister& vn, const VRegister& vm)
5172
5173
5174### SQRDMLSH ###
5175
5176Signed saturating rounding doubling multiply subtract element returning high half _(Armv8.1)_.
5177
5178    void sqrdmlsh(const VRegister& vd,
5179                  const VRegister& vn,
5180                  const VRegister& vm,
5181                  int vm_index)
5182
5183
5184### SQRDMLSH ###
5185
5186Signed saturating rounding doubling multiply subtract returning high half _(Armv8.1)_.
5187
5188    void sqrdmlsh(const VRegister& vd, const VRegister& vn, const VRegister& vm)
5189
5190
5191### SQRDMULH ###
5192
5193Signed saturating rounding doubling multiply element returning high half.
5194
5195    void sqrdmulh(const VRegister& vd,
5196                  const VRegister& vn,
5197                  const VRegister& vm,
5198                  int vm_index)
5199
5200
5201### SQRDMULH ###
5202
5203Signed saturating rounding doubling multiply returning high half.
5204
5205    void sqrdmulh(const VRegister& vd, const VRegister& vn, const VRegister& vm)
5206
5207
5208### SQRSHL ###
5209
5210Signed saturating rounding shift left by register.
5211
5212    void sqrshl(const VRegister& vd, const VRegister& vn, const VRegister& vm)
5213
5214
5215### SQRSHRN ###
5216
5217Signed saturating rounded shift right narrow by immediate.
5218
5219    void sqrshrn(const VRegister& vd, const VRegister& vn, int shift)
5220
5221
5222### SQRSHRN2 ###
5223
5224Signed saturating rounded shift right narrow by immediate (second part).
5225
5226    void sqrshrn2(const VRegister& vd, const VRegister& vn, int shift)
5227
5228
5229### SQRSHRUN ###
5230
5231Signed sat rounded shift right unsigned narrow by immediate.
5232
5233    void sqrshrun(const VRegister& vd, const VRegister& vn, int shift)
5234
5235
5236### SQRSHRUN2 ###
5237
5238Signed sat rounded shift right unsigned narrow by immediate (second part).
5239
5240    void sqrshrun2(const VRegister& vd, const VRegister& vn, int shift)
5241
5242
5243### SQSHL ###
5244
5245Signed saturating shift left by immediate.
5246
5247    void sqshl(const VRegister& vd, const VRegister& vn, int shift)
5248
5249
5250### SQSHL ###
5251
5252Signed saturating shift left by register.
5253
5254    void sqshl(const VRegister& vd, const VRegister& vn, const VRegister& vm)
5255
5256
5257### SQSHLU ###
5258
5259Signed saturating shift left unsigned by immediate.
5260
5261    void sqshlu(const VRegister& vd, const VRegister& vn, int shift)
5262
5263
5264### SQSHRN ###
5265
5266Signed saturating shift right narrow by immediate.
5267
5268    void sqshrn(const VRegister& vd, const VRegister& vn, int shift)
5269
5270
5271### SQSHRN2 ###
5272
5273Signed saturating shift right narrow by immediate (second part).
5274
5275    void sqshrn2(const VRegister& vd, const VRegister& vn, int shift)
5276
5277
5278### SQSHRUN ###
5279
5280Signed saturating shift right unsigned narrow by immediate.
5281
5282    void sqshrun(const VRegister& vd, const VRegister& vn, int shift)
5283
5284
5285### SQSHRUN2 ###
5286
5287Signed saturating shift right unsigned narrow by immediate (second part).
5288
5289    void sqshrun2(const VRegister& vd, const VRegister& vn, int shift)
5290
5291
5292### SQSUB ###
5293
5294Signed saturating subtract.
5295
5296    void sqsub(const VRegister& vd, const VRegister& vn, const VRegister& vm)
5297
5298
5299### SQXTN ###
5300
5301Signed saturating extract narrow.
5302
5303    void sqxtn(const VRegister& vd, const VRegister& vn)
5304
5305
5306### SQXTN2 ###
5307
5308Signed saturating extract narrow (second part).
5309
5310    void sqxtn2(const VRegister& vd, const VRegister& vn)
5311
5312
5313### SQXTUN ###
5314
5315Signed saturating extract unsigned narrow.
5316
5317    void sqxtun(const VRegister& vd, const VRegister& vn)
5318
5319
5320### SQXTUN2 ###
5321
5322Signed saturating extract unsigned narrow (second part).
5323
5324    void sqxtun2(const VRegister& vd, const VRegister& vn)
5325
5326
5327### SRHADD ###
5328
5329Signed rounding halving add.
5330
5331    void srhadd(const VRegister& vd, const VRegister& vn, const VRegister& vm)
5332
5333
5334### SRI ###
5335
5336Shift right by immediate and insert.
5337
5338    void sri(const VRegister& vd, const VRegister& vn, int shift)
5339
5340
5341### SRSHL ###
5342
5343Signed rounding shift left by register.
5344
5345    void srshl(const VRegister& vd, const VRegister& vn, const VRegister& vm)
5346
5347
5348### SRSHR ###
5349
5350Signed rounding shift right by immediate.
5351
5352    void srshr(const VRegister& vd, const VRegister& vn, int shift)
5353
5354
5355### SRSRA ###
5356
5357Signed rounding shift right by immediate and accumulate.
5358
5359    void srsra(const VRegister& vd, const VRegister& vn, int shift)
5360
5361
5362### SSHL ###
5363
5364Signed shift left by register.
5365
5366    void sshl(const VRegister& vd, const VRegister& vn, const VRegister& vm)
5367
5368
5369### SSHLL ###
5370
5371Signed shift left long by immediate.
5372
5373    void sshll(const VRegister& vd, const VRegister& vn, int shift)
5374
5375
5376### SSHLL2 ###
5377
5378Signed shift left long by immediate (second part).
5379
5380    void sshll2(const VRegister& vd, const VRegister& vn, int shift)
5381
5382
5383### SSHR ###
5384
5385Signed shift right by immediate.
5386
5387    void sshr(const VRegister& vd, const VRegister& vn, int shift)
5388
5389
5390### SSRA ###
5391
5392Signed shift right by immediate and accumulate.
5393
5394    void ssra(const VRegister& vd, const VRegister& vn, int shift)
5395
5396
5397### SSUBL ###
5398
5399Signed subtract long.
5400
5401    void ssubl(const VRegister& vd, const VRegister& vn, const VRegister& vm)
5402
5403
5404### SSUBL2 ###
5405
5406Signed subtract long (second part).
5407
5408    void ssubl2(const VRegister& vd, const VRegister& vn, const VRegister& vm)
5409
5410
5411### SSUBW ###
5412
5413Signed integer subtract wide.
5414
5415    void ssubw(const VRegister& vd, const VRegister& vn, const VRegister& vm)
5416
5417
5418### SSUBW2 ###
5419
5420Signed integer subtract wide (second part).
5421
5422    void ssubw2(const VRegister& vd, const VRegister& vn, const VRegister& vm)
5423
5424
5425### ST1 ###
5426
5427One-element single structure store from one lane.
5428
5429    void st1(const VRegister& vt, int lane, const MemOperand& src)
5430
5431
5432### ST1 ###
5433
5434One-element structure store from four registers.
5435
5436    void st1(const VRegister& vt,
5437             const VRegister& vt2,
5438             const VRegister& vt3,
5439             const VRegister& vt4,
5440             const MemOperand& src)
5441
5442
5443### ST1 ###
5444
5445One-element structure store from one register.
5446
5447    void st1(const VRegister& vt, const MemOperand& src)
5448
5449
5450### ST1 ###
5451
5452One-element structure store from three registers.
5453
5454    void st1(const VRegister& vt,
5455             const VRegister& vt2,
5456             const VRegister& vt3,
5457             const MemOperand& src)
5458
5459
5460### ST1 ###
5461
5462One-element structure store from two registers.
5463
5464    void st1(const VRegister& vt, const VRegister& vt2, const MemOperand& src)
5465
5466
5467### ST2 ###
5468
5469Two-element single structure store from two lanes.
5470
5471    void st2(const VRegister& vt,
5472             const VRegister& vt2,
5473             int lane,
5474             const MemOperand& src)
5475
5476
5477### ST2 ###
5478
5479Two-element structure store from two registers.
5480
5481    void st2(const VRegister& vt, const VRegister& vt2, const MemOperand& src)
5482
5483
5484### ST3 ###
5485
5486Three-element single structure store from three lanes.
5487
5488    void st3(const VRegister& vt,
5489             const VRegister& vt2,
5490             const VRegister& vt3,
5491             int lane,
5492             const MemOperand& src)
5493
5494
5495### ST3 ###
5496
5497Three-element structure store from three registers.
5498
5499    void st3(const VRegister& vt,
5500             const VRegister& vt2,
5501             const VRegister& vt3,
5502             const MemOperand& src)
5503
5504
5505### ST4 ###
5506
5507Four-element single structure store from four lanes.
5508
5509    void st4(const VRegister& vt,
5510             const VRegister& vt2,
5511             const VRegister& vt3,
5512             const VRegister& vt4,
5513             int lane,
5514             const MemOperand& src)
5515
5516
5517### ST4 ###
5518
5519Four-element structure store from four registers.
5520
5521    void st4(const VRegister& vt,
5522             const VRegister& vt2,
5523             const VRegister& vt3,
5524             const VRegister& vt4,
5525             const MemOperand& src)
5526
5527
5528### SUB ###
5529
5530Subtract.
5531
5532    void sub(const VRegister& vd, const VRegister& vn, const VRegister& vm)
5533
5534
5535### SUBHN ###
5536
5537Subtract narrow returning high half.
5538
5539    void subhn(const VRegister& vd, const VRegister& vn, const VRegister& vm)
5540
5541
5542### SUBHN2 ###
5543
5544Subtract narrow returning high half (second part).
5545
5546    void subhn2(const VRegister& vd, const VRegister& vn, const VRegister& vm)
5547
5548
5549### SUQADD ###
5550
5551Signed saturating accumulate of unsigned value.
5552
5553    void suqadd(const VRegister& vd, const VRegister& vn)
5554
5555
5556### SXTL ###
5557
5558Signed extend long.
5559
5560    void sxtl(const VRegister& vd, const VRegister& vn)
5561
5562
5563### SXTL2 ###
5564
5565Signed extend long (second part).
5566
5567    void sxtl2(const VRegister& vd, const VRegister& vn)
5568
5569
5570### TBL ###
5571
5572Table lookup from four registers.
5573
5574    void tbl(const VRegister& vd,
5575             const VRegister& vn,
5576             const VRegister& vn2,
5577             const VRegister& vn3,
5578             const VRegister& vn4,
5579             const VRegister& vm)
5580
5581
5582### TBL ###
5583
5584Table lookup from one register.
5585
5586    void tbl(const VRegister& vd, const VRegister& vn, const VRegister& vm)
5587
5588
5589### TBL ###
5590
5591Table lookup from three registers.
5592
5593    void tbl(const VRegister& vd,
5594             const VRegister& vn,
5595             const VRegister& vn2,
5596             const VRegister& vn3,
5597             const VRegister& vm)
5598
5599
5600### TBL ###
5601
5602Table lookup from two registers.
5603
5604    void tbl(const VRegister& vd,
5605             const VRegister& vn,
5606             const VRegister& vn2,
5607             const VRegister& vm)
5608
5609
5610### TBX ###
5611
5612Table lookup extension from four registers.
5613
5614    void tbx(const VRegister& vd,
5615             const VRegister& vn,
5616             const VRegister& vn2,
5617             const VRegister& vn3,
5618             const VRegister& vn4,
5619             const VRegister& vm)
5620
5621
5622### TBX ###
5623
5624Table lookup extension from one register.
5625
5626    void tbx(const VRegister& vd, const VRegister& vn, const VRegister& vm)
5627
5628
5629### TBX ###
5630
5631Table lookup extension from three registers.
5632
5633    void tbx(const VRegister& vd,
5634             const VRegister& vn,
5635             const VRegister& vn2,
5636             const VRegister& vn3,
5637             const VRegister& vm)
5638
5639
5640### TBX ###
5641
5642Table lookup extension from two registers.
5643
5644    void tbx(const VRegister& vd,
5645             const VRegister& vn,
5646             const VRegister& vn2,
5647             const VRegister& vm)
5648
5649
5650### TRN1 ###
5651
5652Transpose vectors (primary).
5653
5654    void trn1(const VRegister& vd, const VRegister& vn, const VRegister& vm)
5655
5656
5657### TRN2 ###
5658
5659Transpose vectors (secondary).
5660
5661    void trn2(const VRegister& vd, const VRegister& vn, const VRegister& vm)
5662
5663
5664### UABA ###
5665
5666Unsigned absolute difference and accumulate.
5667
5668    void uaba(const VRegister& vd, const VRegister& vn, const VRegister& vm)
5669
5670
5671### UABAL ###
5672
5673Unsigned absolute difference and accumulate long.
5674
5675    void uabal(const VRegister& vd, const VRegister& vn, const VRegister& vm)
5676
5677
5678### UABAL2 ###
5679
5680Unsigned absolute difference and accumulate long (second part).
5681
5682    void uabal2(const VRegister& vd, const VRegister& vn, const VRegister& vm)
5683
5684
5685### UABD ###
5686
5687Unsigned absolute difference.
5688
5689    void uabd(const VRegister& vd, const VRegister& vn, const VRegister& vm)
5690
5691
5692### UABDL ###
5693
5694Unsigned absolute difference long.
5695
5696    void uabdl(const VRegister& vd, const VRegister& vn, const VRegister& vm)
5697
5698
5699### UABDL2 ###
5700
5701Unsigned absolute difference long (second part).
5702
5703    void uabdl2(const VRegister& vd, const VRegister& vn, const VRegister& vm)
5704
5705
5706### UADALP ###
5707
5708Unsigned pairwise long add and accumulate.
5709
5710    void uadalp(const VRegister& vd, const VRegister& vn)
5711
5712
5713### UADDL ###
5714
5715Unsigned add long.
5716
5717    void uaddl(const VRegister& vd, const VRegister& vn, const VRegister& vm)
5718
5719
5720### UADDL2 ###
5721
5722Unsigned add long (second part).
5723
5724    void uaddl2(const VRegister& vd, const VRegister& vn, const VRegister& vm)
5725
5726
5727### UADDLP ###
5728
5729Unsigned pairwise long add.
5730
5731    void uaddlp(const VRegister& vd, const VRegister& vn)
5732
5733
5734### UADDLV ###
5735
5736Unsigned add long across vector.
5737
5738    void uaddlv(const VRegister& vd, const VRegister& vn)
5739
5740
5741### UADDW ###
5742
5743Unsigned add wide.
5744
5745    void uaddw(const VRegister& vd, const VRegister& vn, const VRegister& vm)
5746
5747
5748### UADDW2 ###
5749
5750Unsigned add wide (second part).
5751
5752    void uaddw2(const VRegister& vd, const VRegister& vn, const VRegister& vm)
5753
5754
5755### UCVTF ###
5756
5757Convert unsigned integer or fixed point to FP.
5758
5759    void ucvtf(const VRegister& fd, const Register& rn, int fbits = 0)
5760
5761
5762### UCVTF ###
5763
5764Convert unsigned integer or fixed-point to FP.
5765
5766    void ucvtf(const VRegister& fd, const VRegister& vn, int fbits = 0)
5767
5768
5769### UDOT ###
5770
5771Unsigned dot product _(Armv8.2)_.
5772
5773    void udot(const VRegister& vd, const VRegister& vn, const VRegister& vm)
5774
5775
5776### UDOT ###
5777
5778Unsigned dot product by element _(Armv8.2)_.
5779
5780    void udot(const VRegister& vd,
5781              const VRegister& vn,
5782              const VRegister& vm,
5783              int vm_index)
5784
5785
5786### UHADD ###
5787
5788Unsigned halving add.
5789
5790    void uhadd(const VRegister& vd, const VRegister& vn, const VRegister& vm)
5791
5792
5793### UHSUB ###
5794
5795Unsigned halving sub.
5796
5797    void uhsub(const VRegister& vd, const VRegister& vn, const VRegister& vm)
5798
5799
5800### UMAX ###
5801
5802Unsigned maximum.
5803
5804    void umax(const VRegister& vd, const VRegister& vn, const VRegister& vm)
5805
5806
5807### UMAXP ###
5808
5809Unsigned pairwise maximum.
5810
5811    void umaxp(const VRegister& vd, const VRegister& vn, const VRegister& vm)
5812
5813
5814### UMAXV ###
5815
5816Unsigned maximum across vector.
5817
5818    void umaxv(const VRegister& vd, const VRegister& vn)
5819
5820
5821### UMIN ###
5822
5823Unsigned minimum.
5824
5825    void umin(const VRegister& vd, const VRegister& vn, const VRegister& vm)
5826
5827
5828### UMINP ###
5829
5830Unsigned pairwise minimum.
5831
5832    void uminp(const VRegister& vd, const VRegister& vn, const VRegister& vm)
5833
5834
5835### UMINV ###
5836
5837Unsigned minimum across vector.
5838
5839    void uminv(const VRegister& vd, const VRegister& vn)
5840
5841
5842### UMLAL ###
5843
5844Unsigned long multiply-add by scalar element.
5845
5846    void umlal(const VRegister& vd,
5847               const VRegister& vn,
5848               const VRegister& vm,
5849               int vm_index)
5850
5851
5852### UMLAL ###
5853
5854Unsigned long multiply-add.
5855
5856    void umlal(const VRegister& vd, const VRegister& vn, const VRegister& vm)
5857
5858
5859### UMLAL2 ###
5860
5861Unsigned long multiply-add (second part).
5862
5863    void umlal2(const VRegister& vd, const VRegister& vn, const VRegister& vm)
5864
5865
5866### UMLAL2 ###
5867
5868Unsigned long multiply-add by scalar element (second part).
5869
5870    void umlal2(const VRegister& vd,
5871                const VRegister& vn,
5872                const VRegister& vm,
5873                int vm_index)
5874
5875
5876### UMLSL ###
5877
5878Unsigned long multiply-sub by scalar element.
5879
5880    void umlsl(const VRegister& vd,
5881               const VRegister& vn,
5882               const VRegister& vm,
5883               int vm_index)
5884
5885
5886### UMLSL ###
5887
5888Unsigned long multiply-sub.
5889
5890    void umlsl(const VRegister& vd, const VRegister& vn, const VRegister& vm)
5891
5892
5893### UMLSL2 ###
5894
5895Unsigned long multiply-sub (second part).
5896
5897    void umlsl2(const VRegister& vd, const VRegister& vn, const VRegister& vm)
5898
5899
5900### UMLSL2 ###
5901
5902Unsigned long multiply-sub by scalar element (second part).
5903
5904    void umlsl2(const VRegister& vd,
5905                const VRegister& vn,
5906                const VRegister& vm,
5907                int vm_index)
5908
5909
5910### UMOV ###
5911
5912Unsigned move vector element to general-purpose register.
5913
5914    void umov(const Register& rd, const VRegister& vn, int vn_index)
5915
5916
5917### UMULL ###
5918
5919Unsigned long multiply by scalar element.
5920
5921    void umull(const VRegister& vd,
5922               const VRegister& vn,
5923               const VRegister& vm,
5924               int vm_index)
5925
5926
5927### UMULL ###
5928
5929Unsigned long multiply long.
5930
5931    void umull(const VRegister& vd, const VRegister& vn, const VRegister& vm)
5932
5933
5934### UMULL2 ###
5935
5936Unsigned long multiply (second part).
5937
5938    void umull2(const VRegister& vd, const VRegister& vn, const VRegister& vm)
5939
5940
5941### UMULL2 ###
5942
5943Unsigned long multiply by scalar element (second part).
5944
5945    void umull2(const VRegister& vd,
5946                const VRegister& vn,
5947                const VRegister& vm,
5948                int vm_index)
5949
5950
5951### UQADD ###
5952
5953Unsigned saturating add.
5954
5955    void uqadd(const VRegister& vd, const VRegister& vn, const VRegister& vm)
5956
5957
5958### UQRSHL ###
5959
5960Unsigned saturating rounding shift left by register.
5961
5962    void uqrshl(const VRegister& vd, const VRegister& vn, const VRegister& vm)
5963
5964
5965### UQRSHRN ###
5966
5967Unsigned saturating rounding shift right narrow by immediate.
5968
5969    void uqrshrn(const VRegister& vd, const VRegister& vn, int shift)
5970
5971
5972### UQRSHRN2 ###
5973
5974Unsigned saturating rounding shift right narrow by immediate (second part).
5975
5976    void uqrshrn2(const VRegister& vd, const VRegister& vn, int shift)
5977
5978
5979### UQSHL ###
5980
5981Unsigned saturating shift left by immediate.
5982
5983    void uqshl(const VRegister& vd, const VRegister& vn, int shift)
5984
5985
5986### UQSHL ###
5987
5988Unsigned saturating shift left by register.
5989
5990    void uqshl(const VRegister& vd, const VRegister& vn, const VRegister& vm)
5991
5992
5993### UQSHRN ###
5994
5995Unsigned saturating shift right narrow by immediate.
5996
5997    void uqshrn(const VRegister& vd, const VRegister& vn, int shift)
5998
5999
6000### UQSHRN2 ###
6001
6002Unsigned saturating shift right narrow by immediate (second part).
6003
6004    void uqshrn2(const VRegister& vd, const VRegister& vn, int shift)
6005
6006
6007### UQSUB ###
6008
6009Unsigned saturating subtract.
6010
6011    void uqsub(const VRegister& vd, const VRegister& vn, const VRegister& vm)
6012
6013
6014### UQXTN ###
6015
6016Unsigned saturating extract narrow.
6017
6018    void uqxtn(const VRegister& vd, const VRegister& vn)
6019
6020
6021### UQXTN2 ###
6022
6023Unsigned saturating extract narrow (second part).
6024
6025    void uqxtn2(const VRegister& vd, const VRegister& vn)
6026
6027
6028### URECPE ###
6029
6030Unsigned reciprocal estimate.
6031
6032    void urecpe(const VRegister& vd, const VRegister& vn)
6033
6034
6035### URHADD ###
6036
6037Unsigned rounding halving add.
6038
6039    void urhadd(const VRegister& vd, const VRegister& vn, const VRegister& vm)
6040
6041
6042### URSHL ###
6043
6044Unsigned rounding shift left by register.
6045
6046    void urshl(const VRegister& vd, const VRegister& vn, const VRegister& vm)
6047
6048
6049### URSHR ###
6050
6051Unsigned rounding shift right by immediate.
6052
6053    void urshr(const VRegister& vd, const VRegister& vn, int shift)
6054
6055
6056### URSQRTE ###
6057
6058Unsigned reciprocal square root estimate.
6059
6060    void ursqrte(const VRegister& vd, const VRegister& vn)
6061
6062
6063### URSRA ###
6064
6065Unsigned rounding shift right by immediate and accumulate.
6066
6067    void ursra(const VRegister& vd, const VRegister& vn, int shift)
6068
6069
6070### USHL ###
6071
6072Unsigned shift left by register.
6073
6074    void ushl(const VRegister& vd, const VRegister& vn, const VRegister& vm)
6075
6076
6077### USHLL ###
6078
6079Unsigned shift left long by immediate.
6080
6081    void ushll(const VRegister& vd, const VRegister& vn, int shift)
6082
6083
6084### USHLL2 ###
6085
6086Unsigned shift left long by immediate (second part).
6087
6088    void ushll2(const VRegister& vd, const VRegister& vn, int shift)
6089
6090
6091### USHR ###
6092
6093Unsigned shift right by immediate.
6094
6095    void ushr(const VRegister& vd, const VRegister& vn, int shift)
6096
6097
6098### USQADD ###
6099
6100Unsigned saturating accumulate of signed value.
6101
6102    void usqadd(const VRegister& vd, const VRegister& vn)
6103
6104
6105### USRA ###
6106
6107Unsigned shift right by immediate and accumulate.
6108
6109    void usra(const VRegister& vd, const VRegister& vn, int shift)
6110
6111
6112### USUBL ###
6113
6114Unsigned subtract long.
6115
6116    void usubl(const VRegister& vd, const VRegister& vn, const VRegister& vm)
6117
6118
6119### USUBL2 ###
6120
6121Unsigned subtract long (second part).
6122
6123    void usubl2(const VRegister& vd, const VRegister& vn, const VRegister& vm)
6124
6125
6126### USUBW ###
6127
6128Unsigned subtract wide.
6129
6130    void usubw(const VRegister& vd, const VRegister& vn, const VRegister& vm)
6131
6132
6133### USUBW2 ###
6134
6135Unsigned subtract wide (second part).
6136
6137    void usubw2(const VRegister& vd, const VRegister& vn, const VRegister& vm)
6138
6139
6140### UXTL ###
6141
6142Unsigned extend long.
6143
6144    void uxtl(const VRegister& vd, const VRegister& vn)
6145
6146
6147### UXTL2 ###
6148
6149Unsigned extend long (second part).
6150
6151    void uxtl2(const VRegister& vd, const VRegister& vn)
6152
6153
6154### UZP1 ###
6155
6156Unzip vectors (primary).
6157
6158    void uzp1(const VRegister& vd, const VRegister& vn, const VRegister& vm)
6159
6160
6161### UZP2 ###
6162
6163Unzip vectors (secondary).
6164
6165    void uzp2(const VRegister& vd, const VRegister& vn, const VRegister& vm)
6166
6167
6168### XTN ###
6169
6170Extract narrow.
6171
6172    void xtn(const VRegister& vd, const VRegister& vn)
6173
6174
6175### XTN2 ###
6176
6177Extract narrow (second part).
6178
6179    void xtn2(const VRegister& vd, const VRegister& vn)
6180
6181
6182### ZIP1 ###
6183
6184Zip vectors (primary).
6185
6186    void zip1(const VRegister& vd, const VRegister& vn, const VRegister& vm)
6187
6188
6189### ZIP2 ###
6190
6191Zip vectors (secondary).
6192
6193    void zip2(const VRegister& vd, const VRegister& vn, const VRegister& vm)
6194
6195
6196
6197Additional or pseudo instructions
6198---------------------------------
6199
6200### BIND ###
6201
6202Bind a label to the current PC.
6203
6204    void bind(Label* label)
6205
6206
6207### DC ###
6208
6209Emit data in the instruction stream.
6210
6211    void dc(T data)
6212
6213
6214### DC32 ###
6215
6216Emit 32 bits of data into the instruction stream.
6217
6218    void dc32(uint32_t data)
6219
6220
6221### DC64 ###
6222
6223Emit 64 bits of data into the instruction stream.
6224
6225    void dc64(uint64_t data)
6226
6227
6228### DCI ###
6229
6230Emit raw instructions into the instruction stream.
6231
6232    void dci(Instr raw_inst)
6233
6234
6235### PLACE ###
6236
6237Place a literal at the current PC.
6238
6239    void place(RawLiteral* literal)
6240
6241
6242
6243