1 /* 2 * Copyright (c) 2014-2019, ARM Limited and Contributors. All rights reserved. 3 * Copyright (c) 2020, NVIDIA Corporation. All rights reserved. 4 * 5 * SPDX-License-Identifier: BSD-3-Clause 6 */ 7 8 #ifndef CORTEX_A57_H 9 #define CORTEX_A57_H 10 11 #include <lib/utils_def.h> 12 13 /* Cortex-A57 midr for revision 0 */ 14 #define CORTEX_A57_MIDR U(0x410FD070) 15 16 /* Retention timer tick definitions */ 17 #define RETENTION_ENTRY_TICKS_2 U(0x1) 18 #define RETENTION_ENTRY_TICKS_8 U(0x2) 19 #define RETENTION_ENTRY_TICKS_32 U(0x3) 20 #define RETENTION_ENTRY_TICKS_64 U(0x4) 21 #define RETENTION_ENTRY_TICKS_128 U(0x5) 22 #define RETENTION_ENTRY_TICKS_256 U(0x6) 23 #define RETENTION_ENTRY_TICKS_512 U(0x7) 24 25 /******************************************************************************* 26 * CPU Extended Control register specific definitions. 27 ******************************************************************************/ 28 #define CORTEX_A57_ECTLR_EL1 S3_1_C15_C2_1 29 30 #define CORTEX_A57_ECTLR_SMP_BIT (ULL(1) << 6) 31 #define CORTEX_A57_ECTLR_DIS_TWD_ACC_PFTCH_BIT (ULL(1) << 38) 32 #define CORTEX_A57_ECTLR_L2_IPFTCH_DIST_MASK (ULL(0x3) << 35) 33 #define CORTEX_A57_ECTLR_L2_DPFTCH_DIST_MASK (ULL(0x3) << 32) 34 35 #define CORTEX_A57_ECTLR_CPU_RET_CTRL_SHIFT U(0) 36 #define CORTEX_A57_ECTLR_CPU_RET_CTRL_MASK (ULL(0x7) << CORTEX_A57_ECTLR_CPU_RET_CTRL_SHIFT) 37 38 /******************************************************************************* 39 * CPU Memory Error Syndrome register specific definitions. 40 ******************************************************************************/ 41 #define CORTEX_A57_MERRSR_EL1 S3_1_C15_C2_2 42 43 /******************************************************************************* 44 * CPU Auxiliary Control register specific definitions. 45 ******************************************************************************/ 46 #define CORTEX_A57_CPUACTLR_EL1 S3_1_C15_C2_0 47 48 #define CORTEX_A57_CPUACTLR_EL1_DIS_LOAD_PASS_DMB (ULL(1) << 59) 49 #define CORTEX_A57_CPUACTLR_EL1_DIS_DMB_NULLIFICATION (ULL(1) << 58) 50 #define CORTEX_A57_CPUACTLR_EL1_DIS_LOAD_PASS_STORE (ULL(1) << 55) 51 #define CORTEX_A57_CPUACTLR_EL1_GRE_NGRE_AS_NGNRE (ULL(1) << 54) 52 #define CORTEX_A57_CPUACTLR_EL1_DIS_OVERREAD (ULL(1) << 52) 53 #define CORTEX_A57_CPUACTLR_EL1_NO_ALLOC_WBWA (ULL(1) << 49) 54 #define CORTEX_A57_CPUACTLR_EL1_DCC_AS_DCCI (ULL(1) << 44) 55 #define CORTEX_A57_CPUACTLR_EL1_FORCE_FPSCR_FLUSH (ULL(1) << 38) 56 #define CORTEX_A57_CPUACTLR_EL1_DIS_INSTR_PREFETCH (ULL(1) << 32) 57 #define CORTEX_A57_CPUACTLR_EL1_DIS_STREAMING (ULL(3) << 27) 58 #define CORTEX_A57_CPUACTLR_EL1_EN_NC_LOAD_FWD (ULL(1) << 24) 59 #define CORTEX_A57_CPUACTLR_EL1_DIS_L1_STREAMING (ULL(3) << 25) 60 #define CORTEX_A57_CPUACTLR_EL1_DIS_INDIRECT_PREDICTOR (ULL(1) << 4) 61 62 /******************************************************************************* 63 * L2 Control register specific definitions. 64 ******************************************************************************/ 65 #define CORTEX_A57_L2CTLR_EL1 S3_1_C11_C0_2 66 67 #define CORTEX_A57_L2CTLR_DATA_RAM_LATENCY_SHIFT U(0) 68 #define CORTEX_A57_L2CTLR_TAG_RAM_LATENCY_SHIFT U(6) 69 70 #define CORTEX_A57_L2_DATA_RAM_LATENCY_3_CYCLES U(0x2) 71 #define CORTEX_A57_L2_TAG_RAM_LATENCY_3_CYCLES U(0x2) 72 73 #define CORTEX_A57_L2_ECC_PARITY_PROTECTION_BIT (U(1) << 21) 74 75 /******************************************************************************* 76 * L2 Extended Control register specific definitions. 77 ******************************************************************************/ 78 #define CORTEX_A57_L2ECTLR_EL1 S3_1_C11_C0_3 79 80 #define CORTEX_A57_L2ECTLR_RET_CTRL_SHIFT U(0) 81 #define CORTEX_A57_L2ECTLR_RET_CTRL_MASK (U(0x7) << CORTEX_A57_L2ECTLR_RET_CTRL_SHIFT) 82 83 /******************************************************************************* 84 * L2 Memory Error Syndrome register specific definitions. 85 ******************************************************************************/ 86 #define CORTEX_A57_L2MERRSR_EL1 S3_1_C15_C2_3 87 88 #endif /* CORTEX_A57_H */ 89