1 /* 2 * Copyright (c) 2015-2019, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef CORTEX_A72_H 8 #define CORTEX_A72_H 9 10 #include <lib/utils_def.h> 11 12 /* Cortex-A72 midr for revision 0 */ 13 #define CORTEX_A72_MIDR U(0x410FD080) 14 15 /******************************************************************************* 16 * CPU Extended Control register specific definitions. 17 ******************************************************************************/ 18 #define CORTEX_A72_ECTLR_EL1 S3_1_C15_C2_1 19 20 #define CORTEX_A72_ECTLR_SMP_BIT (ULL(1) << 6) 21 #define CORTEX_A72_ECTLR_DIS_TWD_ACC_PFTCH_BIT (ULL(1) << 38) 22 #define CORTEX_A72_ECTLR_L2_IPFTCH_DIST_MASK (ULL(0x3) << 35) 23 #define CORTEX_A72_ECTLR_L2_DPFTCH_DIST_MASK (ULL(0x3) << 32) 24 25 /******************************************************************************* 26 * CPU Memory Error Syndrome register specific definitions. 27 ******************************************************************************/ 28 #define CORTEX_A72_MERRSR_EL1 S3_1_C15_C2_2 29 30 /******************************************************************************* 31 * CPU Auxiliary Control register specific definitions. 32 ******************************************************************************/ 33 #define CORTEX_A72_CPUACTLR_EL1 S3_1_C15_C2_0 34 35 #define CORTEX_A72_CPUACTLR_EL1_DISABLE_L1_DCACHE_HW_PFTCH (ULL(1) << 56) 36 #define CORTEX_A72_CPUACTLR_EL1_DIS_LOAD_PASS_STORE (ULL(1) << 55) 37 #define CORTEX_A72_CPUACTLR_EL1_NO_ALLOC_WBWA (ULL(1) << 49) 38 #define CORTEX_A72_CPUACTLR_EL1_DCC_AS_DCCI (ULL(1) << 44) 39 #define CORTEX_A72_CPUACTLR_EL1_DIS_INSTR_PREFETCH (ULL(1) << 32) 40 41 /******************************************************************************* 42 * L2 Auxiliary Control register specific definitions. 43 ******************************************************************************/ 44 #define CORTEX_A72_L2ACTLR_EL1 S3_1_C15_C0_0 45 46 #define CORTEX_A72_L2ACTLR_FORCE_TAG_BANK_CLK_ACTIVE (ULL(1) << 28) 47 #define CORTEX_A72_L2ACTLR_FORCE_L2_LOGIC_CLK_ACTIVE (ULL(1) << 27) 48 #define CORTEX_A72_L2ACTLR_FORCE_L2_GIC_TIMER_RCG_CLK_ACTIVE (ULL(1) << 26) 49 #define CORTEX_A72_L2ACTLR_ENABLE_UNIQUE_CLEAN (ULL(1) << 14) 50 #define CORTEX_A72_L2ACTLR_DISABLE_DSB_WITH_NO_DVM_SYNC (ULL(1) << 11) 51 #define CORTEX_A72_L2ACTLR_DISABLE_DVM_CMO_BROADCAST (ULL(1) << 8) 52 #define CORTEX_A72_L2ACTLR_ENABLE_HAZARD_DETECT_TIMEOUT (ULL(1) << 7) 53 #define CORTEX_A72_L2ACTLR_DISABLE_ACE_SH_OR_CHI (ULL(1) << 6) 54 55 /******************************************************************************* 56 * L2 Control register specific definitions. 57 ******************************************************************************/ 58 #define CORTEX_A72_L2CTLR_EL1 S3_1_C11_C0_2 59 60 #define CORTEX_A72_L2CTLR_DATA_RAM_LATENCY_SHIFT U(0) 61 #define CORTEX_A72_L2CTLR_DATA_RAM_SETUP_SHIFT U(5) 62 #define CORTEX_A72_L2CTLR_TAG_RAM_LATENCY_SHIFT U(6) 63 #define CORTEX_A72_L2CTLR_TAG_RAM_SETUP_SHIFT U(9) 64 65 #define CORTEX_A72_L2_DATA_RAM_LATENCY_MASK U(0x7) 66 #define CORTEX_A72_L2_TAG_RAM_LATENCY_MASK U(0x7) 67 #define CORTEX_A72_L2_DATA_RAM_LATENCY_3_CYCLES U(0x2) 68 #define CORTEX_A72_L2_TAG_RAM_LATENCY_2_CYCLES U(0x1) 69 #define CORTEX_A72_L2_TAG_RAM_LATENCY_3_CYCLES U(0x2) 70 71 /******************************************************************************* 72 * L2 Memory Error Syndrome register specific definitions. 73 ******************************************************************************/ 74 #define CORTEX_A72_L2MERRSR_EL1 S3_1_C15_C2_3 75 76 #endif /* CORTEX_A72_H */ 77