1 /* 2 * Copyright (c) 2017-2019, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef CORTEX_A75_H 8 #define CORTEX_A75_H 9 10 #include <lib/utils_def.h> 11 12 /* Cortex-A75 MIDR */ 13 #define CORTEX_A75_MIDR U(0x410fd0a0) 14 15 /******************************************************************************* 16 * CPU Extended Control register specific definitions. 17 ******************************************************************************/ 18 #define CORTEX_A75_CPUPWRCTLR_EL1 S3_0_C15_C2_7 19 #define CORTEX_A75_CPUECTLR_EL1 S3_0_C15_C1_4 20 21 /******************************************************************************* 22 * CPU Auxiliary Control register specific definitions. 23 ******************************************************************************/ 24 #define CORTEX_A75_CPUACTLR_EL1 S3_0_C15_C1_0 25 26 #define CORTEX_A75_CPUACTLR_EL1_DISABLE_LOAD_PASS_STORE (ULL(1) << 35) 27 28 /* Definitions of register field mask in CORTEX_A75_CPUPWRCTLR_EL1 */ 29 #define CORTEX_A75_CORE_PWRDN_EN_MASK U(0x1) 30 31 #define CORTEX_A75_ACTLR_AMEN_BIT (ULL(1) << 4) 32 33 /* 34 * The Cortex-A75 core implements five counters, 0-4. Events 0, 1, 2, are 35 * fixed and are enabled (Group 0). Events 3 and 4 (Group 1) are 36 * programmable by programming the appropriate Event count bits in 37 * CPUAMEVTYPER<n> register and are disabled by default. Platforms may 38 * enable this with suitable programming. 39 */ 40 #define CORTEX_A75_AMU_NR_COUNTERS U(5) 41 #define CORTEX_A75_AMU_GROUP0_MASK U(0x7) 42 #define CORTEX_A75_AMU_GROUP1_MASK (U(0) << 3) 43 44 #ifndef __ASSEMBLER__ 45 #include <stdint.h> 46 47 uint64_t cortex_a75_amu_cnt_read(int idx); 48 void cortex_a75_amu_cnt_write(int idx, uint64_t val); 49 unsigned int cortex_a75_amu_read_cpuamcntenset_el0(void); 50 unsigned int cortex_a75_amu_read_cpuamcntenclr_el0(void); 51 void cortex_a75_amu_write_cpuamcntenset_el0(unsigned int mask); 52 void cortex_a75_amu_write_cpuamcntenclr_el0(unsigned int mask); 53 #endif /* __ASSEMBLER__ */ 54 55 #endif /* CORTEX_A75_H */ 56