1 /* 2 * Copyright (C) 2016-2021 Marvell International Ltd. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 * https://spdx.org/licenses 6 */ 7 8 #ifndef PLATFORM_DEF_H 9 #define PLATFORM_DEF_H 10 11 #ifndef __ASSEMBLER__ 12 #include <stdio.h> 13 #endif /* __ASSEMBLER__ */ 14 15 #include <board_marvell_def.h> 16 #include <mvebu_def.h> 17 18 /* 19 * Most platform porting definitions provided by included headers 20 */ 21 22 /* 23 * DRAM Memory layout: 24 * +-----------------------+ 25 * : : 26 * : Linux : 27 * 0x04X00000-->+-----------------------+ 28 * | BL3-3(u-boot) |>>}>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>> 29 * |-----------------------| } | 30 * | BL3-[0,1, 2] | }---------------------------------> | 31 * |-----------------------| } || | 32 * | BL2 | }->FIP (loaded by || | 33 * |-----------------------| } BootROM to DRAM) || | 34 * | FIP_TOC | } || | 35 * 0x04120000-->|-----------------------| || | 36 * | BL1 (RO) | || | 37 * 0x04100000-->+-----------------------+ || | 38 * : : || | 39 * : Trusted SRAM section : \/ | 40 * 0x04040000-->+-----------------------+ Replaced by BL2 +----------------+ | 41 * | BL1 (RW) | <<<<<<<<<<<<<<<< | BL3-1 NOBITS | | 42 * 0x04037000-->|-----------------------| <<<<<<<<<<<<<<<< |----------------| | 43 * | | <<<<<<<<<<<<<<<< | BL3-1 PROGBITS | | 44 * 0x04023000-->|-----------------------| +----------------+ | 45 * | BL2 | | 46 * |-----------------------| | 47 * | | | 48 * 0x04001000-->|-----------------------| | 49 * | Shared | | 50 * 0x04000000-->+-----------------------+ | 51 * : : | 52 * : Linux : | 53 * : : | 54 * |-----------------------| | 55 * | | U-Boot(BL3-3) Loaded by BL2 | 56 * | U-Boot | <<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<< 57 * 0x00000000-->+-----------------------+ 58 * 59 * Trusted SRAM section 0x4000000..0x4200000: 60 * ---------------------------------------- 61 * SRAM_BASE = 0x4001000 62 * BL2_BASE = 0x4006000 63 * BL2_LIMIT = BL31_BASE 64 * BL31_BASE = 0x4023000 = (64MB + 256KB - 0x1D000) 65 * BL31_PROGBITS_LIMIT = BL1_RW_BASE 66 * BL1_RW_BASE = 0x4037000 = (64MB + 256KB - 0x9000) 67 * BL1_RW_LIMIT = BL31_LIMIT = 0x4040000 68 * 69 * 70 * PLAT_MARVELL_FIP_BASE = 0x4120000 71 */ 72 73 /* 74 * Since BL33 is loaded by BL2 (and validated by BL31) to DRAM offset 0, 75 * it is allowed to load/copy images to 'NULL' pointers 76 */ 77 #if defined(IMAGE_BL2) || defined(IMAGE_BL31) 78 #define PLAT_ALLOW_ZERO_ADDR_COPY 79 #endif 80 81 #define PLAT_MARVELL_ATF_BASE 0x4000000 82 #define PLAT_MARVELL_ATF_LOAD_ADDR \ 83 (PLAT_MARVELL_ATF_BASE + 0x100000) 84 85 #define PLAT_MARVELL_FIP_BASE \ 86 (PLAT_MARVELL_ATF_LOAD_ADDR + 0x20000) 87 #define PLAT_MARVELL_FIP_MAX_SIZE 0x4000000 88 89 #define PLAT_MARVELL_CLUSTER_CORE_COUNT U(2) 90 /* DRAM[2MB..66MB] is used as Trusted ROM */ 91 #define PLAT_MARVELL_TRUSTED_ROM_BASE PLAT_MARVELL_ATF_LOAD_ADDR 92 /* 4 MB for FIP image */ 93 #define PLAT_MARVELL_TRUSTED_ROM_SIZE 0x00400000 94 /* Reserve 12M for SCP (Secure PayLoad) Trusted RAM 95 * OP-TEE SHMEM follows this region 96 */ 97 #define PLAT_MARVELL_TRUSTED_RAM_BASE 0x04400000 98 #define PLAT_MARVELL_TRUSTED_RAM_SIZE 0x00C00000 /* 12 MB DRAM */ 99 100 /* 101 * PLAT_ARM_MAX_BL1_RW_SIZE is calculated using the current BL1 RW debug size 102 * plus a little space for growth. 103 */ 104 #define PLAT_MARVELL_MAX_BL1_RW_SIZE 0xA000 105 106 /* 107 * PLAT_ARM_MAX_BL2_SIZE is calculated using the current BL2 debug size plus a 108 * little space for growth. 109 */ 110 #define PLAT_MARVELL_MAX_BL2_SIZE 0xF000 111 112 /* 113 * PLAT_ARM_MAX_BL31_SIZE is calculated using the current BL31 debug size plus a 114 * little space for growth. 115 */ 116 #define PLAT_MARVEL_MAX_BL31_SIZE 0x5D000 117 118 #define PLAT_MARVELL_CPU_ENTRY_ADDR BL1_RO_BASE 119 120 /* GIC related definitions */ 121 #define PLAT_MARVELL_GICD_BASE (MVEBU_REGS_BASE + MVEBU_GICD_BASE) 122 #define PLAT_MARVELL_GICR_BASE (MVEBU_REGS_BASE + MVEBU_GICR_BASE) 123 #define PLAT_MARVELL_GICC_BASE (MVEBU_REGS_BASE + MVEBU_GICC_BASE) 124 125 #define PLAT_MARVELL_G0_IRQ_PROPS(grp) \ 126 INTR_PROP_DESC(MARVELL_IRQ_SEC_SGI_0, GIC_HIGHEST_SEC_PRIORITY, grp, \ 127 GIC_INTR_CFG_LEVEL), \ 128 INTR_PROP_DESC(MARVELL_IRQ_SEC_SGI_6, GIC_HIGHEST_SEC_PRIORITY, grp, \ 129 GIC_INTR_CFG_LEVEL) 130 131 #define PLAT_MARVELL_G1S_IRQ_PROPS(grp) \ 132 INTR_PROP_DESC(MARVELL_IRQ_SEC_PHY_TIMER, \ 133 GIC_HIGHEST_SEC_PRIORITY, grp, GIC_INTR_CFG_LEVEL), \ 134 INTR_PROP_DESC(MARVELL_IRQ_SEC_SGI_1, GIC_HIGHEST_SEC_PRIORITY, grp, \ 135 GIC_INTR_CFG_LEVEL), \ 136 INTR_PROP_DESC(MARVELL_IRQ_SEC_SGI_2, GIC_HIGHEST_SEC_PRIORITY, grp, \ 137 GIC_INTR_CFG_LEVEL), \ 138 INTR_PROP_DESC(MARVELL_IRQ_SEC_SGI_3, GIC_HIGHEST_SEC_PRIORITY, grp, \ 139 GIC_INTR_CFG_LEVEL), \ 140 INTR_PROP_DESC(MARVELL_IRQ_SEC_SGI_4, GIC_HIGHEST_SEC_PRIORITY, grp, \ 141 GIC_INTR_CFG_LEVEL), \ 142 INTR_PROP_DESC(MARVELL_IRQ_SEC_SGI_5, GIC_HIGHEST_SEC_PRIORITY, grp, \ 143 GIC_INTR_CFG_LEVEL), \ 144 INTR_PROP_DESC(MARVELL_IRQ_SEC_SGI_7, GIC_HIGHEST_SEC_PRIORITY, grp, \ 145 GIC_INTR_CFG_LEVEL) 146 147 148 #define PLAT_MARVELL_SHARED_RAM_CACHED 1 149 150 /* CCI related constants */ 151 #define PLAT_MARVELL_CCI_BASE MVEBU_CCI_BASE 152 #define PLAT_MARVELL_CCI_CLUSTER0_SL_IFACE_IX 3 153 #define PLAT_MARVELL_CCI_CLUSTER1_SL_IFACE_IX 4 154 155 /* 156 * Load address of BL3-3 for this platform port 157 */ 158 #define PLAT_MARVELL_NS_IMAGE_OFFSET 0x0 159 160 /* System Reference Clock*/ 161 #define PLAT_REF_CLK_IN_HZ COUNTER_FREQUENCY 162 163 /* 164 * PL011 related constants 165 */ 166 #define PLAT_MARVELL_BOOT_UART_BASE (MVEBU_REGS_BASE + 0x12000) 167 #define PLAT_MARVELL_BOOT_UART_CLK_IN_HZ 25804800 168 169 #define PLAT_MARVELL_CRASH_UART_BASE PLAT_MARVELL_BOOT_UART_BASE 170 #define PLAT_MARVELL_CRASH_UART_CLK_IN_HZ PLAT_MARVELL_BOOT_UART_CLK_IN_HZ 171 172 #define PLAT_MARVELL_BL31_RUN_UART_BASE PLAT_MARVELL_BOOT_UART_BASE 173 #define PLAT_MARVELL_BL31_RUN_UART_CLK_IN_HZ PLAT_MARVELL_BOOT_UART_CLK_IN_HZ 174 175 /* Required platform porting definitions */ 176 #define PLAT_MAX_PWR_LVL MPIDR_AFFLVL1 177 178 /* System timer related constants */ 179 #define PLAT_MARVELL_NSTIMER_FRAME_ID 1 180 181 /* Mailbox base address */ 182 #define PLAT_MARVELL_MAILBOX_BASE (MARVELL_SHARED_RAM_BASE + 0x400) 183 #define PLAT_MARVELL_MAILBOX_SIZE 0x100 184 #define PLAT_MARVELL_MAILBOX_MAGIC_NUM 0x6D72766C /* mrvl */ 185 186 /* DRAM CS memory map registers related constants */ 187 #define MVEBU_CS_MMAP_LOW(cs_num) \ 188 (MVEBU_CS_MMAP_REG_BASE + (cs_num) * 0x8) 189 #define MVEBU_CS_MMAP_ENABLE 0x1 190 #define MVEBU_CS_MMAP_AREA_LEN_OFFS 16 191 #define MVEBU_CS_MMAP_AREA_LEN_MASK \ 192 (0x1f << MVEBU_CS_MMAP_AREA_LEN_OFFS) 193 #define MVEBU_CS_MMAP_START_ADDR_LOW_OFFS 23 194 #define MVEBU_CS_MMAP_START_ADDR_LOW_MASK \ 195 (0x1ff << MVEBU_CS_MMAP_START_ADDR_LOW_OFFS) 196 197 #define MVEBU_CS_MMAP_HIGH(cs_num) \ 198 (MVEBU_CS_MMAP_REG_BASE + 0x4 + (cs_num) * 0x8) 199 200 /* DRAM max CS number */ 201 #define MVEBU_MAX_CS_MMAP_NUM (2) 202 203 /* CPU decoder window related constants */ 204 #define CPU_DEC_WIN_CTRL_REG(win_num) \ 205 (MVEBU_CPU_DEC_WIN_REG_BASE + (win_num) * 0x10) 206 #define CPU_DEC_CR_WIN_ENABLE 0x1 207 #define CPU_DEC_CR_WIN_TARGET_OFFS 4 208 #define CPU_DEC_CR_WIN_TARGET_MASK \ 209 (0xf << CPU_DEC_CR_WIN_TARGET_OFFS) 210 211 #define CPU_DEC_WIN_SIZE_REG(win_num) \ 212 (MVEBU_CPU_DEC_WIN_REG_BASE + 0x4 + (win_num) * 0x10) 213 #define CPU_DEC_CR_WIN_SIZE_OFFS 0 214 #define CPU_DEC_CR_WIN_SIZE_MASK \ 215 (0xffff << CPU_DEC_CR_WIN_SIZE_OFFS) 216 #define CPU_DEC_CR_WIN_SIZE_ALIGNMENT 0x10000 217 218 #define CPU_DEC_WIN_BASE_REG(win_num) \ 219 (MVEBU_CPU_DEC_WIN_REG_BASE + 0x8 + (win_num) * 0x10) 220 #define CPU_DEC_BR_BASE_OFFS 0 221 #define CPU_DEC_BR_BASE_MASK \ 222 (0xffff << CPU_DEC_BR_BASE_OFFS) 223 224 #define CPU_DEC_REMAP_LOW_REG(win_num) \ 225 (MVEBU_CPU_DEC_WIN_REG_BASE + 0xC + (win_num) * 0x10) 226 #define CPU_DEC_RLR_REMAP_LOW_OFFS 0 227 #define CPU_DEC_RLR_REMAP_LOW_MASK \ 228 (0xffff << CPU_DEC_BR_BASE_OFFS) 229 230 #define CPU_DEC_CCI_BASE_REG (MVEBU_CPU_DEC_WIN_REG_BASE + 0xe0) 231 232 /* Securities */ 233 #define IRQ_SEC_OS_TICK_INT MARVELL_IRQ_SEC_PHY_TIMER 234 235 #endif /* PLATFORM_DEF_H */ 236