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Searched defs:Covered (Results 1 – 14 of 14) sorted by relevance

/external/llvm-project/llvm/tools/llvm-cov/
DCoverageSummaryInfo.h25 size_t Covered; variable
33 RegionCoverageInfo(size_t Covered, size_t NumRegions) in RegionCoverageInfo()
66 size_t Covered; variable
74 LineCoverageInfo(size_t Covered, size_t NumLines) in LineCoverageInfo()
124 void addFunction(bool Covered) { in addFunction()
/external/llvm/tools/llvm-cov/
DCoverageSummaryInfo.h26 size_t Covered; member
59 size_t Covered; member
/external/swiftshader/tests/regres/cov/
Dimport.go33 Covered SpanList // Spans with coverage member
/external/oss-fuzz/infra/base-images/base-runner/gocoverage/gocovsum/
Dgocovsum.go18 Covered int `json:"covered"` member
/external/llvm/lib/CodeGen/
DMachineInstrBundle.cpp319 bool Covered = TRI->isSuperRegisterEq(Reg, MOReg); in analyzePhysReg() local
/external/llvm-project/llvm/lib/CodeGen/
DMachineInstrBundle.cpp335 bool Covered = TRI->isSuperRegisterEq(Reg, MOReg); in AnalyzePhysRegInBundle() local
DRDFLiveness.cpp564 RegisterAggr Covered(PRI); in computePhiInfo() local
/external/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/
DMachineInstrBundle.cpp336 bool Covered = TRI->isSuperRegisterEq(Reg, MOReg); in AnalyzePhysRegInBundle() local
/external/llvm/lib/CodeGen/GlobalISel/
DRegisterBankInfo.cpp83 BitVector &Covered = RB.ContainedRegClasses; in addRegBankCoverage() local
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Hexagon/
DRDFLiveness.cpp524 RegisterAggr Covered(PRI); in computePhiInfo() local
/external/llvm/utils/TableGen/
DRegisterInfoEmitter.cpp1470 BitVector Covered = RegBank.computeCoveredRegisters(*Regs); in runTargetDesc() local
/external/swiftshader/third_party/llvm-10.0/llvm/lib/DebugInfo/DWARF/
DDWARFVerifier.cpp70 bool Covered = I1->LowPC <= R.LowPC; in contains() local
/external/llvm-project/llvm/lib/DebugInfo/DWARF/
DDWARFVerifier.cpp72 bool Covered = I1->LowPC <= R.LowPC; in contains() local
/external/llvm-project/llvm/utils/TableGen/
DRegisterInfoEmitter.cpp1562 BitVector Covered = RegBank.computeCoveredRegisters(*Regs); in runTargetDesc() local