| /external/llvm-project/llvm/unittests/Analysis/ |
| D | LazyCallGraphTest.cpp | 623 LazyCallGraph::RefSCC &DRC = *CG.lookupRefSCC(D); in TEST() local
773 LazyCallGraph::RefSCC &DRC = *CG.lookupRefSCC(D1); in TEST() local
865 LazyCallGraph::RefSCC &DRC = *CG.lookupRefSCC(D1); in TEST() local
968 LazyCallGraph::RefSCC &DRC = *CG.lookupRefSCC(D); in TEST() local
1041 LazyCallGraph::RefSCC &DRC = *CG.lookupRefSCC(D); in TEST() local
1111 LazyCallGraph::RefSCC &DRC = *CG.lookupRefSCC(D1); in TEST() local
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| /external/llvm/unittests/Analysis/ |
| D | LazyCallGraphTest.cpp | 494 LazyCallGraph::RefSCC &DRC = *CG.lookupRefSCC(D); in TEST() local
619 LazyCallGraph::RefSCC &DRC = *CG.lookupRefSCC(D1); in TEST() local
683 LazyCallGraph::RefSCC &DRC = *I; in TEST() local
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| /external/llvm/lib/CodeGen/ |
| D | MachineSink.cpp | 171 const TargetRegisterClass *DRC = MRI->getRegClass(DstReg); in INITIALIZE_PASS_DEPENDENCY() local
|
| D | MachineVerifier.cpp | 978 if (const TargetRegisterClass *DRC = in visitMachineOperand() local
1028 if (const TargetRegisterClass *DRC = in visitMachineOperand() local
|
| /external/llvm-project/llvm/lib/CodeGen/ |
| D | MachineVerifier.cpp | 1770 if (const TargetRegisterClass *DRC = in visitMachineOperand() local
1879 if (const TargetRegisterClass *DRC = in visitMachineOperand() local
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| D | MachineSink.cpp | 249 const TargetRegisterClass *DRC = MRI->getRegClass(DstReg); in INITIALIZE_PASS_DEPENDENCY() local
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/ |
| D | MachineVerifier.cpp | 1687 if (const TargetRegisterClass *DRC = in visitMachineOperand() local
1787 if (const TargetRegisterClass *DRC = in visitMachineOperand() local
|
| D | MachineSink.cpp | 232 const TargetRegisterClass *DRC = MRI->getRegClass(DstReg); in INITIALIZE_PASS_DEPENDENCY() local
|
| /external/llvm-project/llvm/lib/Target/Hexagon/ |
| D | HexagonEarlyIfConv.cpp | 778 MachineBasicBlock::iterator At, const TargetRegisterClass *DRC, in buildMux()
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| D | HexagonBitSimplify.cpp | 933 auto *DRC = getFinalVRegClass(RD, MRI); in isTransparentCopy() local
1484 const BitTracker::RegisterCell &DRC = BT.lookup(DR); in processBlock() local
|
| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Hexagon/ |
| D | HexagonEarlyIfConv.cpp | 778 MachineBasicBlock::iterator At, const TargetRegisterClass *DRC, in buildMux()
|
| D | HexagonBitSimplify.cpp | 932 auto *DRC = getFinalVRegClass(RD, MRI); in isTransparentCopy() local
1474 const BitTracker::RegisterCell &DRC = BT.lookup(DR); in processBlock() local
|
| /external/llvm/lib/Target/Hexagon/ |
| D | HexagonBitSimplify.cpp | 886 auto *DRC = getFinalVRegClass(RD, MRI); in isTransparentCopy() local
|
| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/ |
| D | SIInstrInfo.cpp | 3933 const TargetRegisterClass *DRC = RI.getRegClass(OpInfo.RegClass); in isLegalRegOperand() local
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| /external/llvm-project/llvm/lib/Target/AMDGPU/ |
| D | SIInstrInfo.cpp | 4418 const TargetRegisterClass *DRC = RI.getRegClass(OpInfo.RegClass); in isLegalRegOperand() local
|