| /external/llvm-project/llvm/lib/CodeGen/ |
| D | ExpandPostRAPseudos.cpp | 89 Register DstSubReg = TRI->getSubReg(DstReg, SubIdx); in LowerSubregToReg() local
|
| D | RegisterCoalescer.cpp | 3727 unsigned SrcSubReg, DstSubReg; in applyTerminalRule() local
|
| /external/llvm/lib/CodeGen/ |
| D | ExpandPostRAPseudos.cpp | 93 unsigned DstSubReg = TRI->getSubReg(DstReg, SubIdx); in LowerSubregToReg() local
|
| D | RegisterCoalescer.cpp | 2836 unsigned DstReg, DstSubReg, SrcReg, SrcSubReg; in applyTerminalRule() local
|
| /external/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/ |
| D | ExpandPostRAPseudos.cpp | 89 Register DstSubReg = TRI->getSubReg(DstReg, SubIdx); in LowerSubregToReg() local
|
| D | RegisterCoalescer.cpp | 3704 unsigned DstReg, DstSubReg, SrcReg, SrcSubReg; in applyTerminalRule() local
|
| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AVR/ |
| D | AVRRegisterInfo.cpp | 280 unsigned DstSubReg, in shouldCoalesce()
|
| /external/llvm-project/llvm/lib/Target/AVR/ |
| D | AVRRegisterInfo.cpp | 283 unsigned DstSubReg, in shouldCoalesce()
|
| /external/llvm-project/llvm/lib/Target/Hexagon/ |
| D | HexagonRegisterInfo.cpp | 249 const TargetRegisterClass *DstRC, unsigned DstSubReg, in shouldCoalesce()
|
| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Hexagon/ |
| D | HexagonRegisterInfo.cpp | 242 const TargetRegisterClass *DstRC, unsigned DstSubReg, in shouldCoalesce()
|
| /external/llvm-project/llvm/lib/Target/SystemZ/ |
| D | SystemZRegisterInfo.cpp | 343 unsigned DstSubReg, in shouldCoalesce()
|
| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/SystemZ/ |
| D | SystemZRegisterInfo.cpp | 344 unsigned DstSubReg, in shouldCoalesce()
|
| /external/llvm-project/llvm/lib/Target/AArch64/ |
| D | AArch64RegisterInfo.cpp | 742 const TargetRegisterClass *DstRC, unsigned DstSubReg, in shouldCoalesce()
|
| /external/llvm/lib/Target/ARM/ |
| D | ARMBaseRegisterInfo.cpp | 787 unsigned DstSubReg, in shouldCoalesce()
|
| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/ |
| D | ARMBaseRegisterInfo.cpp | 840 unsigned DstSubReg, in shouldCoalesce()
|
| /external/llvm-project/llvm/lib/Target/ARM/ |
| D | ARMBaseRegisterInfo.cpp | 855 unsigned DstSubReg, in shouldCoalesce()
|
| /external/llvm/include/llvm/Target/ |
| D | TargetRegisterInfo.h | 923 unsigned DstSubReg, in shouldCoalesce()
|
| /external/swiftshader/third_party/llvm-10.0/llvm/include/llvm/CodeGen/ |
| D | TargetRegisterInfo.h | 950 unsigned DstSubReg, in shouldCoalesce()
|
| /external/llvm-project/llvm/include/llvm/CodeGen/ |
| D | TargetRegisterInfo.h | 968 unsigned DstSubReg, in shouldCoalesce()
|
| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/ |
| D | SIRegisterInfo.cpp | 1705 unsigned DstSubReg, in shouldCoalesce()
|
| /external/llvm-project/llvm/lib/Target/AMDGPU/ |
| D | SIRegisterInfo.cpp | 1961 unsigned DstSubReg, in shouldCoalesce()
|
| /external/llvm-project/llvm/lib/CodeGen/LiveDebugValues/ |
| D | InstrRefBasedImpl.cpp | 1830 unsigned DstSubReg = TRI->getSubReg(DstRegNum, SubRegIdx); in performCopy() local
|