1 /* 2 * Copyright (c) 2020, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef ARM_TRUSTED_FIRMWARE_EXPORT_COMMON_EP_INFO_EXP_H 8 #define ARM_TRUSTED_FIRMWARE_EXPORT_COMMON_EP_INFO_EXP_H 9 10 /* EXPORT HEADER -- See include/export/README for details! -- EXPORT HEADER */ 11 12 #include "../lib/utils_def_exp.h" 13 #include "param_header_exp.h" 14 15 /******************************************************************************* 16 * Constants that allow assembler code to access members of and the 17 * 'entry_point_info' structure at their correct offsets. 18 ******************************************************************************/ 19 #define ENTRY_POINT_INFO_PC_OFFSET U(0x08) 20 #ifdef __aarch64__ 21 #define ENTRY_POINT_INFO_ARGS_OFFSET U(0x18) 22 #else 23 #define ENTRY_POINT_INFO_LR_SVC_OFFSET U(0x10) 24 #define ENTRY_POINT_INFO_ARGS_OFFSET U(0x14) 25 #endif 26 27 /* Security state of the image. */ 28 #define EP_SECURITY_MASK UL(0x1) 29 #define EP_SECURITY_SHIFT UL(0) 30 #define EP_SECURE UL(0x0) 31 #define EP_NON_SECURE UL(0x1) 32 33 /* Endianness of the image. */ 34 #define EP_EE_MASK U(0x2) 35 #define EP_EE_SHIFT U(1) 36 #define EP_EE_LITTLE U(0x0) 37 #define EP_EE_BIG U(0x2) 38 #define EP_GET_EE(x) ((x) & EP_EE_MASK) 39 #define EP_SET_EE(x, ee) ((x) = ((x) & ~EP_EE_MASK) | (ee)) 40 41 /* Enable or disable access to the secure timer from secure images. */ 42 #define EP_ST_MASK U(0x4) 43 #define EP_ST_SHIFT U(2) 44 #define EP_ST_DISABLE U(0x0) 45 #define EP_ST_ENABLE U(0x4) 46 #define EP_GET_ST(x) ((x) & EP_ST_MASK) 47 #define EP_SET_ST(x, ee) ((x) = ((x) & ~EP_ST_MASK) | (ee)) 48 49 /* Determine if an image is executable or not. */ 50 #define EP_EXE_MASK U(0x8) 51 #define EP_EXE_SHIFT U(3) 52 #define EP_NON_EXECUTABLE U(0x0) 53 #define EP_EXECUTABLE U(0x8) 54 #define EP_GET_EXE(x) ((x) & EP_EXE_MASK) 55 #define EP_SET_EXE(x, ee) ((x) = ((x) & ~EP_EXE_MASK) | (ee)) 56 57 /* Flag to indicate the first image that is executed. */ 58 #define EP_FIRST_EXE_MASK U(0x10) 59 #define EP_FIRST_EXE_SHIFT U(4) 60 #define EP_FIRST_EXE U(0x10) 61 #define EP_GET_FIRST_EXE(x) ((x) & EP_FIRST_EXE_MASK) 62 #define EP_SET_FIRST_EXE(x, ee) ((x) = ((x) & ~EP_FIRST_EXE_MASK) | (ee)) 63 64 #ifndef __ASSEMBLER__ 65 66 typedef struct aapcs64_params { 67 uint64_t arg0; 68 uint64_t arg1; 69 uint64_t arg2; 70 uint64_t arg3; 71 uint64_t arg4; 72 uint64_t arg5; 73 uint64_t arg6; 74 uint64_t arg7; 75 } aapcs64_params_t; 76 77 typedef struct aapcs32_params { 78 uint32_t arg0; 79 uint32_t arg1; 80 uint32_t arg2; 81 uint32_t arg3; 82 } aapcs32_params_t; 83 84 /***************************************************************************** 85 * This structure represents the superset of information needed while 86 * switching exception levels. The only two mechanisms to do so are 87 * ERET & SMC. Security state is indicated using bit zero of header 88 * attribute 89 * NOTE: BL1 expects entrypoint followed by spsr at an offset from the start 90 * of this structure defined by the macro `ENTRY_POINT_INFO_PC_OFFSET` while 91 * processing SMC to jump to BL31. 92 *****************************************************************************/ 93 typedef struct entry_point_info { 94 param_header_t h; 95 uintptr_t pc; 96 uint32_t spsr; 97 #ifdef __aarch64__ 98 aapcs64_params_t args; 99 #else 100 uintptr_t lr_svc; 101 aapcs32_params_t args; 102 #endif 103 } entry_point_info_t; 104 105 #endif /*__ASSEMBLER__*/ 106 107 #endif /* ARM_TRUSTED_FIRMWARE_EXPORT_COMMON_EP_INFO_EXP_H */ 108