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1 /* Copyright 2018 The TensorFlow Authors. All Rights Reserved.
2 
3 Licensed under the Apache License, Version 2.0 (the "License");
4 you may not use this file except in compliance with the License.
5 You may obtain a copy of the License at
6 
7     http://www.apache.org/licenses/LICENSE-2.0
8 
9 Unless required by applicable law or agreed to in writing, software
10 distributed under the License is distributed on an "AS IS" BASIS,
11 WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
12 See the License for the specific language governing permissions and
13 limitations under the License.
14 ==============================================================================*/
15 
16 #ifndef TENSORFLOW_COMPILER_XLA_SERVICE_LLVM_IR_SORT_UTIL_H_
17 #define TENSORFLOW_COMPILER_XLA_SERVICE_LLVM_IR_SORT_UTIL_H_
18 
19 #include <vector>
20 
21 #include "absl/strings/string_view.h"
22 #include "absl/types/span.h"
23 #include "llvm/IR/Value.h"
24 #include "tensorflow/compiler/xla/service/gpu/launch_dimensions.h"
25 #include "tensorflow/compiler/xla/service/llvm_ir/ir_array.h"
26 #include "tensorflow/core/lib/core/status.h"
27 #include "tensorflow/core/platform/types.h"
28 
29 namespace xla {
30 namespace llvm_ir {
31 using EmitCallToNestedComputationCallback =
32     std::function<Status(absl::Span<llvm::Value* const>, llvm::Value*)>;
33 // Emits llvm IR to do pairwise comparisons/swaps in the 'dimension_to_sort'
34 // dimension of each array in 'values_arrays'. All other dimensions are kept
35 // as-is. This implements the inner loop of BitonicSort. It is assumed that
36 // 'xor_masks' contains only powers of 2, or values 2^k - 1 (k > 0).
37 Status EmitSortInPlace(
38     int64 dimension_to_sort, const std::vector<IrArray>& values_arrays,
39     absl::string_view name, absl::Span<const int64> xor_masks,
40     llvm::IRBuilder<>* b, const gpu::LaunchDimensions& launch_dimensions,
41     int64 num_iterations_in_sort_dim, int64 tile_size,
42     const EmitCallToNestedComputationCallback& emit_compare_callback);
43 }  // namespace llvm_ir
44 }  // namespace xla
45 
46 #endif  // TENSORFLOW_COMPILER_XLA_SERVICE_LLVM_IR_SORT_UTIL_H_
47