| /external/vixl/examples/aarch64/ |
| D | add4-double.cc | 47 __ Fadd(d0, d0, d1); in GenerateAdd4Double() local
48 __ Fadd(d2, d2, d3); in GenerateAdd4Double() local
49 __ Fadd(d0, d0, d2); in GenerateAdd4Double() local
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| D | add3-double.cc | 40 __ Fadd(d0, d0, d1); // d0 <- x + y in GenerateAdd3Double() local
41 __ Fadd(d0, d0, d2); // d0 <- d0 + z in GenerateAdd3Double() local
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| D | custom-disassembler.cc | 130 __ Fadd(d30, d16, d17); in GenerateCustomDisassemblerTestCode() local
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| /external/vixl/test/aarch64/ |
| D | test-assembler-fp-aarch64.cc | 451 __ Fadd(s0, s17, s18); in TEST() local
452 __ Fadd(s1, s18, s19); in TEST() local
453 __ Fadd(s2, s14, s18); in TEST() local
454 __ Fadd(s3, s15, s18); in TEST() local
455 __ Fadd(s4, s16, s18); in TEST() local
456 __ Fadd(s5, s15, s16); in TEST() local
457 __ Fadd(s6, s16, s15); in TEST() local
459 __ Fadd(d7, d30, d31); in TEST() local
460 __ Fadd(d8, d29, d31); in TEST() local
461 __ Fadd(d9, d26, d31); in TEST() local
[all …]
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| D | test-simulator-aarch64.cc | 5057 __ Fadd(temp, temp, input_1.D()); in GenerateSum() local
5058 __ Fadd(result, temp, input_3); in GenerateSum() local
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| D | test-assembler-neon-aarch64.cc | 3690 __ Fadd(v8.V4H(), v1.V4H(), v0.V4H()); in TEST() local
3691 __ Fadd(v9.V8H(), v3.V8H(), v2.V8H()); in TEST() local
3692 __ Fadd(v10.V4H(), v4.V4H(), v3.V4H()); in TEST() local
3694 __ Fadd(v11.V4H(), v6.V4H(), v1.V4H()); in TEST() local
3695 __ Fadd(v12.V4H(), v7.V4H(), v7.V4H()); in TEST() local
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| D | test-assembler-sve-aarch64.cc | 15212 __ Fadd(z2.VnH(), p0m, z2.VnH(), 0.5); in TEST_SVE() local
15231 __ Fadd(z12.VnS(), p0m, z12.VnS(), 0.5); in TEST_SVE() local
15250 __ Fadd(z22.VnD(), p0m, z22.VnD(), 0.5); in TEST_SVE() local
15271 __ Fadd(z1.VnS(), p1.Merging(), z1.VnS(), 1.0); in TEST_SVE() local
17868 __ Fadd(zt_fp_1, zt_fp_1, fp_one); in TestFpCompareHelper() local
17872 __ Fadd(zt_fp_2, zt_fp_2, fp_one); in TestFpCompareHelper() local
17876 __ Fadd(zt_fp_3, zt_fp_3, fp_one); in TestFpCompareHelper() local
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| D | test-assembler-aarch64.cc | 13557 __ Fadd(v0.V4S(), v1.V4S(), v2.V4S()); // Requires {FP, NEON}. in SimulationCPUFeaturesScopeHelper() local
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| /external/vixl/benchmarks/aarch64/ |
| D | bench-utils.cc | 366 __ Fadd(PickV(size), PickV(size), PickV(size)); in GenerateFPSequence() local
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| /external/vixl/src/aarch64/ |
| D | macro-assembler-sve-aarch64.cc | 640 void MacroAssembler::Fadd(const ZRegister& zd, in Fadd() function in vixl::aarch64::MacroAssembler
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| D | macro-assembler-aarch64.h | 1409 void Fadd(const VRegister& vd, const VRegister& vn, const VRegister& vm) { in Fadd() function
4149 void Fadd(const ZRegister& zd, in Fadd() function
4162 void Fadd(const ZRegister& zd, const ZRegister& zn, const ZRegister& zm) { in Fadd() function
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| /external/llvm/lib/CodeGen/SelectionDAG/ |
| D | LegalizeDAG.cpp | 2414 SDValue Fadd = DAG.getNode(ISD::FADD, dl, MVT::f64, Fmul, Fcvt2); in ExpandLegalINT_TO_FP() local
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| /external/llvm-project/llvm/lib/CodeGen/SelectionDAG/ |
| D | LegalizeDAG.cpp | 3991 SDValue Fadd = DAG.getNode(ISD::STRICT_FADD, dl, Node->getVTList(), in ExpandNode() local
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